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10 changes: 4 additions & 6 deletions Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.dsc
Original file line number Diff line number Diff line change
Expand Up @@ -69,6 +69,7 @@
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
FdtLib|MdePkg/Library/BaseFdtLib/BaseFdtLib.inf
SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
Expand Down Expand Up @@ -145,13 +146,14 @@
# RISC-V Architectural Libraries
RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
RiscVMmuLib|UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf

TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
RealTimeClockLib|EmbeddedPkg//Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf

[LibraryClasses.common.SEC]
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
!ifdef $(DEBUG_ON_SERIAL_PORT)
DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
!else
Expand Down Expand Up @@ -407,7 +409,6 @@
HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
PrePiHobListPointerLib|OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
FdtLib|MdePkg/Library/BaseFdtLib/BaseFdtLib.inf # Map to deprecated library for this module only
}

#
Expand Down Expand Up @@ -467,10 +468,7 @@
#
# RISC-V Platform module
#
Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf {
<LibraryClasses>
SerialPortLib|Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
}
Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf

#
# RISC-V Core module
Expand Down
3 changes: 0 additions & 3 deletions Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
Original file line number Diff line number Diff line change
Expand Up @@ -14,9 +14,6 @@
PACKAGE_GUID = AD6E43CA-7FED-4CEA-8151-68B2C5F12B3A
PACKAGE_VERSION = 1.0

[Includes]
Include
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@benjamindoron benjamindoron Mar 5, 2026

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That's probably the other platform's fault. It's typical for platforms to do this, it's how they bind #include directives to a path. Does the other board perhaps !include this file in its DEC/DSC? That would likely create issues, yes


[LibraryClasses]

[Guids]
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -46,6 +46,7 @@
DebugLib
DevicePathLib
DxeServicesTableLib
IoLib
MemoryAllocationLib
PcdLib
UefiBootServicesTableLib
Expand Down
4 changes: 2 additions & 2 deletions Platform/Sophgo/SG2042_EVB_Board/SG2042.dsc
Original file line number Diff line number Diff line change
Expand Up @@ -144,9 +144,8 @@

# RISC-V Architectural Libraries
RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
RiscVFpuLib|UefiCpuPkg/Library/BaseRiscVFpuLib/BaseRiscVFpuLib.inf
RiscVMmuLib|UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf

TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
Expand All @@ -161,6 +160,7 @@
!else
DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
!endif
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
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This addition goes beyond what is described in the commit message.
Please add a description of why it's needed.

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update commit message


ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
Expand Down
10 changes: 5 additions & 5 deletions Silicon/Bosc/NanHuPkg/Sec/Memory.c
Original file line number Diff line number Diff line change
Expand Up @@ -123,7 +123,7 @@ GetNumCells (
return -FDT_ERR_BADNCELLS;
}

Val = fdt32_to_cpu (*Prop);
Val = Fdt32ToCpu (*Prop);
Comment thread
wxjstz marked this conversation as resolved.
if (Val > FDT_MAX_NCELLS) {
return -FDT_ERR_BADNCELLS;
}
Expand Down Expand Up @@ -188,17 +188,17 @@ AddReservedMemoryMap (
RegProp = FdtGetProp (FdtPointer, SubNode, "reg", &Len);

if ((RegProp != 0) && (Len == ((NumAddrCells + NumSizeCells) * sizeof (INT32)))) {
Addr = fdt32_to_cpu (RegProp[0]);
Addr = Fdt32ToCpu (RegProp[0]);

if (NumAddrCells > 1) {
Addr = (Addr << 32) | fdt32_to_cpu (RegProp[1]);
Addr = (Addr << 32) | Fdt32ToCpu (RegProp[1]);
}

RegProp += NumAddrCells;
Size = fdt32_to_cpu (RegProp[0]);
Size = Fdt32ToCpu (RegProp[0]);

if (NumSizeCells > 1) {
Size = (Size << 32) | fdt32_to_cpu (RegProp[1]);
Size = (Size << 32) | Fdt32ToCpu (RegProp[1]);
}

DEBUG ((
Expand Down
10 changes: 6 additions & 4 deletions Silicon/Bosc/NanHuPkg/Sec/SecMain.c
Original file line number Diff line number Diff line change
Expand Up @@ -57,7 +57,8 @@ SecStartup (
)
{
EFI_HOB_HANDOFF_INFO_TABLE *HobList;
EFI_RISCV_FIRMWARE_CONTEXT FirmwareContext;
RISCV_SEC_HANDOFF_DATA SecHandoffData;
const EFI_GUID SecHobDataGuid = RISCV_SEC_HANDOFF_HOB_GUID;
EFI_STATUS Status;
UINT64 UefiMemoryBase;
UINT64 StackBase;
Expand All @@ -76,9 +77,6 @@ SecStartup (
DeviceTreeAddress
));

FirmwareContext.BootHartId = BootHartId;
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We are migrating from some sort of design to some other sort of design.
This is not the same as "add this hob which is required".
Can you expand the commit message slightly?

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update commit message

SetFirmwareContextPointer (&FirmwareContext);

StackBase = (UINT64)FixedPcdGet32 (PcdTemporaryRamBase);
StackSize = FixedPcdGet32 (PcdTemporaryRamSize);
UefiMemoryBase = StackBase + StackSize - SIZE_32MB;
Expand All @@ -96,6 +94,10 @@ SecStartup (

BuildStackHob (StackBase, StackSize);

SecHandoffData.BootHartId = BootHartId;
SecHandoffData.FdtPointer = DeviceTreeAddress;
BuildGuidDataHob (&SecHobDataGuid, &SecHandoffData, sizeof(SecHandoffData));

//
// Process all libraries constructor function linked to SecMain.
//
Expand Down
1 change: 1 addition & 0 deletions Silicon/Bosc/NanHuPkg/Sec/SecMain.h
Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,7 @@
#include <Library/PrePiHobListPointerLib.h>
#include <Library/SerialPortLib.h>
#include <Register/RiscV64/RiscVImpl.h>
#include <Guid/RiscVSecHobData.h>

/**
Entry point to the C language phase of SEC. After the SEC assembly
Expand Down
10 changes: 5 additions & 5 deletions Silicon/Sophgo/SG2042Pkg/Sec/Memory.c
Original file line number Diff line number Diff line change
Expand Up @@ -123,7 +123,7 @@ GetNumCells (
return -FDT_ERR_BADNCELLS;
}

Val = fdt32_to_cpu (*Prop);
Val = Fdt32ToCpu (*Prop);
if (Val > FDT_MAX_NCELLS) {
return -FDT_ERR_BADNCELLS;
}
Expand Down Expand Up @@ -188,17 +188,17 @@ AddReservedMemoryMap (
RegProp = FdtGetProp (FdtPointer, SubNode, "reg", &Len);

if ((RegProp != 0) && (Len == ((NumAddrCells + NumSizeCells) * sizeof (INT32)))) {
Addr = fdt32_to_cpu (RegProp[0]);
Addr = Fdt32ToCpu (RegProp[0]);

if (NumAddrCells > 1) {
Addr = (Addr << 32) | fdt32_to_cpu (RegProp[1]);
Addr = (Addr << 32) | Fdt32ToCpu (RegProp[1]);
}

RegProp += NumAddrCells;
Size = fdt32_to_cpu (RegProp[0]);
Size = Fdt32ToCpu (RegProp[0]);

if (NumSizeCells > 1) {
Size = (Size << 32) | fdt32_to_cpu (RegProp[1]);
Size = (Size << 32) | Fdt32ToCpu (RegProp[1]);
}

DEBUG ((
Expand Down
9 changes: 5 additions & 4 deletions Silicon/Sophgo/SG2042Pkg/Sec/SecMain.c
Original file line number Diff line number Diff line change
Expand Up @@ -57,7 +57,8 @@ SecStartup (
)
{
EFI_HOB_HANDOFF_INFO_TABLE *HobList;
EFI_RISCV_FIRMWARE_CONTEXT FirmwareContext;
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Exactly the same comments as on Bosc/XiangshanSeriesPkg applies to this commit also.

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update commit message

RISCV_SEC_HANDOFF_DATA SecHandoffData;
const EFI_GUID SecHobDataGuid = RISCV_SEC_HANDOFF_HOB_GUID;
EFI_STATUS Status;
UINT64 UefiMemoryBase;
UINT64 StackBase;
Expand All @@ -76,9 +77,6 @@ SecStartup (
DeviceTreeAddress
));

FirmwareContext.BootHartId = BootHartId;
SetFirmwareContextPointer (&FirmwareContext);

StackBase = (UINT64)FixedPcdGet32 (PcdTemporaryRamBase);
StackSize = FixedPcdGet32 (PcdTemporaryRamSize);
UefiMemoryBase = StackBase + StackSize - SIZE_32MB;
Expand All @@ -96,6 +94,9 @@ SecStartup (

BuildStackHob (StackBase, StackSize);

SecHandoffData.BootHartId = BootHartId;
SecHandoffData.FdtPointer = DeviceTreeAddress;
BuildGuidDataHob (&SecHobDataGuid, &SecHandoffData, sizeof(SecHandoffData));
//
// Process all libraries constructor function linked to SecMain.
//
Expand Down
1 change: 1 addition & 0 deletions Silicon/Sophgo/SG2042Pkg/Sec/SecMain.h
Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,7 @@
#include <Library/PrePiHobListPointerLib.h>
#include <Library/SerialPortLib.h>
#include <Register/RiscV64/RiscVImpl.h>
#include <Guid/RiscVSecHobData.h>

/**
Entry point to the C language phase of SEC. After the SEC assembly
Expand Down