OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

Python packages providing a library for Verification Stimulus and Coverage

Constrained random stimuli generation for C++ and SystemC

A Python package for creating and solving constrained randomization problems.

RV32IM RISC-V CPU core with a full UVM verification environment and ISA-compliance via Spike (DPI-C): constrained-random, SVA, coverage, Python debug tools, and CI.

SystemVerilog and UVM verification of an 8x8 SRAM memory controller with coverage, scoreboard, regression scripts, and bug-demo dashboard.

UVM-based verification environment for a 5-stage RV32I RISC-V pipeline using constrained-random testing, DPI-C golden reference modeling, assertions, scoreboarding, functional coverage, and 20-seed QuestaSim regression debugging.

UVM testbench for verifying a packet router using the YAPP (Yet Another Packet Protocol)

SRAM subsystem verification using SystemVerilog UVM, SVA assertions, scoreboard, functional coverage, and 20-seed QuestaSim regression evidence from EDA Playground.

Backpressure-safe 1-stage valid-ready pipeline in SystemVerilog with constrained-random verification, assertions (SVA), and waveform validation.

AXI4 Memory Controller UVM Verification Environment with real Siemens Questa seed-1 simulation logs, scoreboard checks, functional coverage summaries, and documented burst-read debug fix.

Explorations in Uniform Sampling of SMT2 Constraints

Multi-state Mealy/Moore FSM in SystemVerilog with SVA assertions, constrained-random testbenches, and functional coverage — synthesizable on Xilinx FPGAs

AXI4 SRAM controller verification environment using SystemVerilog, UVM-lite, SVA, constrained-random testing, and functional coverage.