clk: qcom: gcc-shikra: Add support for the USB3 DP PHY reset#1231
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clk: qcom: gcc-shikra: Add support for the USB3 DP PHY reset#1231imrashai wants to merge 105 commits into
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Document the IDs used by Shikra SoC IoT variants: - CQ2390M: Shikra Retail with modem - CQ2390S: Shikra Retail without modem - IQ2390S: Shikra Industrial without modem Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add SoC ID for Shikra IoT variants: CQ2390M, CQ2390S and IQ2390S. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Qualcomm Shikra SoC implements arm,mmu-500. Document its compatible. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Document the SCM compatible on the Shikra SoC. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Document the device tree binding for the Shikra EVK platform, which is built around a modular System-on-Module (SoM) mounted on a common carrier board. The SoM integrates the Shikra SoC, PMICs, and essential GPIOs, while the EVK carrier board provides additional peripherals such as UART and USB interfaces. Shikra EVK supports three SoM variants: retail with modem, retail without modem, and an industrial non-modem variant. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add compatible for Shikra SoC IMEM. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Document the Top Level Mode Multiplexer on the Shikra platform. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add pinctrl driver for TLMM block found in the Shikra SoC. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Document the RPM Power Domains on the Shikra Platform. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
Shikra has the same RPM power domains as QCM2290. Add shikra support by reusing QCM2290 power domains. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
Document the pm8150 compatible string and available regulators in the QCOM SMD RPM regulator documentation. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
The PM8150 is found on boards with shikra SoCs and It provides 10 SMPS and 18 LDO regulators. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
Add the rpmpd compatable string for shikra. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
Qualcomm Shikra SoC implements qcom,smmu-500 for adreno-smmu. Document its corresponding compatible. Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Add "qcom,shikra-apcs-hmss-global" compatibility string in qcom_apcs_ipc mailbox driver to match apcs_glb device node. Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
Document compatible string for the QFPROM on Shikra platform. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add the qcom,shikra-rpm-proc compatible string to the Qualcomm RPM remote processor device tree binding. Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add compatible for the Qualcomm Shikra APCS block to the Qualcomm APCS binding. Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Document the compatible for Shikra. Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Document the qcom,rpmcc-shikra compatible. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Add support for qcom global clock controller bindings for Shikra platform. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Add support for RPM-managed clocks on the Shikra platform. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Add support for Global clock controller for Shikra Qualcomm SoC. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Enable the GCC driver on the Qualcomm Shikra EVK boards. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Add devicetree binding for watchdog present on Qualcomm's Shikra SoC. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Document the GPI DMA engine on Shikra platform. Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Update dt-bindings to add Shikra to QMP Phy list. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Update dt-bindings to add Shikra to QUSB2 Phy list. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Introduce the compatible definition for Shikra QCOM SNPS DWC3. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Add init sequence and phy configuration for Shikra. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
…sent Some clock controller descriptors do not provide any reset lines. Avoid registering a reset controller when desc->num_resets is zero by making the registration conditional. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Some Qualcomm clock controller descriptors may contain NULL entries in the clk_hws array. Skip such entries when registering clock hardware to avoid passing NULL pointers to the clock framework. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Add GCC LPASS clocks support for Qualcomm Shikra SoC. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
The GCC LPASS clocks must be enabled to access audio core clock controller registers. Hence, mark them as critical on Qualcomm Shikra SoCs. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
…ller Add device tree bindings for the Audio Core clock controller on Qualcomm Shikra SoC. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
… SoC Add support for Audio core clock controller on Qualcomm Shikra SoC. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Shikra shares the same power domain topology as sm6125. Remove the dedicated shikra_rpmpds[] and update shikra_desc to reuse sm6125_rpmpds[] with RPM_SMD_LEVEL_TURBO_NO_CPR. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
All Shikra SoC variants (CQM, CQS, IQS) share the same protection domain requirements: mpss_wlan_pd only. audio_pd is not required on any of these variants. Introduce shikra_cqm_domains with mpss_wlan_pd and wire all three compatibles (qcom,shikra-cqm, qcom,shikra-cqs, qcom,shikra-iqs) to it. Signed-off-by: Anurag Pateriya <apateriy@qti.qualcomm.com>
The DT bindings for inline-crypto engine do not specify the UFS_PHY_GDSC power-domain and iface clock. Without enabling the iface clock and the associated power-domain the ICE hardware cannot function correctly and leads to unclocked hardware accesses being observed during probe. Fix the DT bindings for inline-crypto engine to require the UFS_PHY_GDSC power-domain and iface clock for new devices (Eliza and Milos) introduced in the current release (7.1) with yet-to-stabilize ABI, while preserving backward compatibility for older devices. Fixes: 618195a ("dt-bindings: crypto: qcom,inline-crypto-engine: Document the Eliza ICE") Fixes: 85faec1 ("dt-bindings: crypto: qcom,inline-crypto-engine: document the Milos ICE") Reviewed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Since Qualcomm inline-crypto engine (ICE) is now a dedicated driver de-coupled from the QCOM UFS driver, it explicitly votes for its required clocks during probe. For scenarios where the 'clk_ignore_unused' flag is not passed on the kernel command line, to avoid potential unclocked ICE hardware register access during probe the ICE driver should additionally vote on the 'iface' clock. Also update the suspend and resume callbacks to handle un-voting and voting on the 'iface' clock. Fixes: 2afbf43 ("soc: qcom: Make the Qualcomm UFS/SDCC ICE a dedicated driver") Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
The Shikra SoC board compatibles use a `-som` suffix (qcom,shikra-cqm-som, qcom,shikra-cqs-som, qcom,shikra-iqs-som). Update the pd-mapper entries added in the previous commit to match. Fixes: 3aa65ff ("soc: qcom: pd-mapper: Add shikra PD support for CQM/CQS/IQS") Co-Authored-By: Claude Sonnet 4.6 (1M context) <noreply@anthropic.com> Signed-off-by: Anurag Pateriya <apateriy@qti.qualcomm.com>
Consolidate $ref and if/then blocks under a single allOf to ensure all schema constraints are correctly enforced. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
Add the Qualcomm Shikra SoC compatible string for the CPU-to-DDR bandwidth monitor. Shikra has a BWMONv5 for CPU. Signed-off-by: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Document the EPSS L3 interconnect provider binding for Qualcomm Shikra SoC. The Shikra EPSS L3 block is similar to existing Qualcomm EPSS/OSM L3 providers, but supports only up to 12 frequency lookup table entries. Introduce Shikra specific bindings to represent this constrained EPSS variant. Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Add Epoch Subsystem (EPSS) L3 interconnect provider support on Qualcomm Shikra SoC. The EPSS L3 block on Shikra SoC is similar to existing Qualcomm EPSS/OSM L3 providers, but supports only up to 12 frequency lookup table entries. Reading beyond the supported LUT entries can expose incorrect frequencies. Add shikra-specifc EPSS descriptor shikra_epss_l3_perf_state that reuses existing EPSS configuration with appropriate LUT entries limit. Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Shikra uses the same CAMSS IP as QCM2290. Extend the existing qcom,qcm2290-camss binding to add the qcom,shikra-camss compatible string. Co-developed-by: Vikram Sharma <vikramsa@qti.qualcomm.com> Signed-off-by: Vikram Sharma <vikramsa@qti.qualcomm.com> Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
Add Shikra compatible consistent with CAMSS CCI interfaces. It requires only two clocks. Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
Add CAMSS driver support for Shikra SoC. Add high level resource definitions for 2 CSIPHY, 2 CSID and 2 VFE instances along with the interconnect bandwidth votes for AHB, HF and SF MNOC paths. Co-developed-by: Vikram Sharma <vikramsa@qti.qualcomm.com> Signed-off-by: Vikram Sharma <vikramsa@qti.qualcomm.com> Signed-off-by: Prashant Shrotriya <pshrotri@qti.qualcomm.com>
SMEM_SMSM_SIZE_INFO (id 419) is not populated by the boot firmware on Shikra. The SMSM driver falls back to SMSM_DEFAULT_NUM_HOSTS when this segment is absent, which causes SMEM_SMSM_CPU_INTR_MASK (id 333) to be allocated with the wrong size. The upstream default of 3 allocates 8*3*4 = 96 bytes. Shikra modem firmware expects 8*5*4 = 160 bytes, matching the num_hosts=5 used by the downstream kernel. The size mismatch causes the modem to crash on boot with "smsm.c: Bad pointer from smem_alloc". Increasing the host count only results in a larger allocation, so this change is safe for existing platforms. Increase the default to 5 to match the modem firmware expectation. Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
The driver hardcodes IRQF_TRIGGER_HIGH when registering the BAM interrupt, which overrides the trigger type specified in the device tree. This is incorrect for platforms like Shikra where the A2 BAM requires edge-triggered interrupts. Use IRQF_TRIGGER_NONE instead, which causes the kernel to use the trigger type already configured by platform_get_irq() when it parsed the device tree interrupts property. This makes the driver platform-agnostic. Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
This driver provides access to modem data channels on platforms using the A2 BAM hardware, including Shikra. Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
Add support for the Adreno A704 GPU (chip ID 0x07000400). It belongs to the A610 family and shares its configuration with the A702, including HWCG, UBWC settings, and CP memory pool size. Introduce adreno_is_a704() and include A704 in adreno_is_a610_family(). Signed-off-by: Aditya Sherawat <asherawa@qti.qualcomm.com>
The Shikra SoC uses an Adreno A704 GPU identified by chip ID 0x07000400. Signed-off-by: Aditya Sherawat <asherawa@qti.qualcomm.com>
Drop generic compatible approach, and add Shikra specific bindings. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Update the compatible string to "qcom,shikra-epss" as per the latest bindings. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Add ftrace tracepoints to SMSM for observability of state bit updates, IPC kicks, interrupt handling, and IRQ mask/unmask operations. Introduce a trace header and wire CFLAGS_smsm.o so the trace header is found via -I$(src). Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
Add ftrace tracepoints to the BAM-DMUX driver for observability of channel open/close (local and remote), RX callbacks, power on/off transitions, power control IRQs, and each step of the runtime resume sequence. Introduce a trace header and wire CFLAGS_qcom_bam_dmux.o so the trace header is found via -I$(src). Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
Provide the GCC USB3 DP PHY reset definition in dt-bindings for the Qualcomm Shikra SoC in order to enable adding the USB nodes in DTS. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Add GCC USB3 DP PHY reset support for Qualcomm Shikra SoC. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
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Provide the GCC USB3 DP PHY reset definition in dt-bindings for the
Qualcomm Shikra SoC in order to enable adding the USB nodes in DTS.