arm64: dts: qcom: lemans: add AEST error nodes#1215
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FROMLIST , Link: missing ?
Add AEST RAS error source nodes for the Lemans SoC. The DT describes a processor error source covering all CPU cores and a shared L3 cache error source for the cluster. These nodes model the hardware error reporting blocks and associated interrupts as required by the Arm AEST specification. Link: https://lore.kernel.org/lkml/20260505-aest-devicetree-support-v1-7-d5d6ffacf0a5@oss.qualcomm.com/ Co-developed-by: Faruque Ansari <faruque.ansari@oss.qualcomm.com> Signed-off-by: Faruque Ansari <faruque.ansari@oss.qualcomm.com> Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com>
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@shashim-quic Ack, I have updated FROMLIST and link. Apologize I had missed this ... |
PR #1215 — validate-patchPR: #1215
Final Summary
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PR #1215 — checker-log-analyzerPR: #1215
Detailed report: Full report
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Add AEST RAS error source nodes for the Lemans SoC.
The DT describes a processor error source covering all CPU cores and a shared L3 cache error source for the cluster. These nodes model the hardware error reporting blocks and associated interrupts as required by the Arm AEST specification.
Co-developed-by: Faruque Ansari faruque.ansari@oss.qualcomm.com