Rg/pulp cluster pr

bin/slm_hyper.py

@@ -1,7 +1,6 @@
 #!/usr/bin/python3
 
 #Written by ABA to update the format of the slm file to be compliant with hyperflash model used in testbench
-import numpy as np
 import os
 import os.path
 import argparse
@@ -24,7 +23,10 @@
 with open(args.input_file, "rU") as fi:
     data = list(map(lambda x:x.split(delimiter), fi.read().strip().split("\n")))
 fo=open(args.output_file, "w")
-A=np.array(data)
+
+# Write the header
 fo.write('@000000\n')
-for i in range(0, A.shape[0],2):
-    fo.write('%s%s\n' %(A[i+1][1],A[i][1]))
+
+# Iterate over rows in pairs
+for i in range(0, len(data)-1, 2):  # subtract 1 to avoid IndexError if odd number of rows
+    fo.write(f'{data[i+1][1]}{data[i][1]}\n')

drivers/host_uart.c

@@ -0,0 +1,49 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Nils Wistoff <nwistoff@iis.ee.ethz.ch>
+// Paul Scheffler <paulsc@iis.ee.ethz.ch>
+
+// Adapted from Cheshire
+
+#include "host_uart.h"
+
+static inline volatile uint8_t *reg8(void *base, int offs) {
+    return (volatile uint8_t *)(base + offs);
+}
+
+static inline void fence() {
+    asm volatile("fence" ::: "memory");
+}
+
+int uart_read_ready(void *uart_base) {
+    return *reg8(uart_base, UART_LINE_STATUS_REG_OFFSET) & (1 << UART_LINE_STATUS_DATA_READY_BIT);
+}
+
+static inline int __uart_write_ready(void *uart_base) {
+    return *reg8(uart_base, UART_LINE_STATUS_REG_OFFSET) & (1 << UART_LINE_STATUS_THR_EMPTY_BIT);
+}
+
+static inline int __uart_write_idle(void *uart_base) {
+    return __uart_write_ready(uart_base) &&
+           *reg8(uart_base, UART_LINE_STATUS_REG_OFFSET) & (1 << UART_LINE_STATUS_TMIT_EMPTY_BIT);
+}
+
+void uart_write(void *uart_base, uint8_t byte) {
+    while (!__uart_write_ready(uart_base))
+        ;
+    *reg8(uart_base, UART_THR_REG_OFFSET) = byte;
+}
+
+void uart_write_flush(void *uart_base) {
+    fence();
+    while (!__uart_write_idle(uart_base))
+        ;
+}
+
+uint8_t uart_read(void *uart_base) {
+    while (!uart_read_ready(uart_base))
+        ;
+    return *reg8(uart_base, UART_RBR_REG_OFFSET);
+}

drivers/include/host_uart.h

@@ -0,0 +1,42 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Nils Wistoff <nwistoff@iis.ee.ethz.ch>
+// Paul Scheffler <paulsc@iis.ee.ethz.ch>
+
+// Adapted from Cheshire
+
+#pragma once
+
+#include <stdint.h>
+
+// Register offsets
+#define UART_RBR_REG_OFFSET 0
+#define UART_THR_REG_OFFSET 0
+#define UART_INTR_ENABLE_REG_OFFSET 4
+#define UART_INTR_IDENT_REG_OFFSET 8
+#define UART_FIFO_CONTROL_REG_OFFSET 8
+#define UART_LINE_CONTROL_REG_OFFSET 12
+#define UART_MODEM_CONTROL_REG_OFFSET 16
+#define UART_LINE_STATUS_REG_OFFSET 20
+#define UART_MODEM_STATUS_REG_OFFSET 24
+#define UART_DLAB_LSB_REG_OFFSET 0
+#define UART_DLAB_MSB_REG_OFFSET 4
+
+// Register fields
+#define UART_LINE_STATUS_DATA_READY_BIT 0
+#define UART_LINE_STATUS_THR_EMPTY_BIT 5
+#define UART_LINE_STATUS_TMIT_EMPTY_BIT 6
+
+int uart_read_ready(void *uart_base);
+
+void uart_write(void *uart_base, uint8_t byte);
+
+void uart_write_str(void *uart_base, void *src, uint64_t len);
+
+void uart_write_flush(void *uart_base);
+
+uint8_t uart_read(void *uart_base);
+
+void uart_read_str(void *uart_base, void *dst, uint64_t len);

include/archi/chips/astral-cluster/memory_map.h

@@ -60,6 +60,7 @@
 #define ARCHI_FC_ITC_ADDR            ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ITC_OFFSET )
 #define ARCHI_FC_TIMER_ADDR          ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET )
 #define ARCHI_STDOUT_ADDR            0x03002000
+#define ARCHI_HOST_UART_ADDR         0x03002000
 
 #define ARCHI_FLL_AREA_SIZE          0x00000010
 

include/archi/chips/carfield-cluster/memory_map.h

@@ -100,6 +100,7 @@
 #define ARCHI_MCHAN_EXT_OFFSET           0x00001800
 #define ARCHI_HMR_OFFSET                 0x00002000
 #define ARCHI_TCDM_SCRUBBER_OFFSET       0x00002400
+#define ARCHI_HWPE_HCI_ECC_OFFSET        0x00002800
 
 #define ARCHI_CLUSTER_PERIPHERALS_ADDR             ( ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET )
 #define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET )
@@ -111,6 +112,7 @@
 #define ARCHI_MCHAN_EXT_ADDR                       ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_MCHAN_EXT_OFFSET )
 #define ARCHI_HMR_ADDR                             ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_HMR_OFFSET )
 #define ARCHI_TCDM_SCRUBBER_ADDR                   ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_TCDM_SCRUBBER_OFFSET )
+#define ARCHI_HWPE_HCI_ECC_ADDR                    ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_HWPE_HCI_ECC_OFFSET )
 
 #define ARCHI_CLUSTER_CTRL_GLOBAL_ADDR(cid)        ( ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_CTRL_OFFSET )
 #define ARCHI_ICACHE_CTRL_GLOBAL_ADDR(cid)         ( ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_ICACHE_CTRL_OFFSET )
@@ -120,6 +122,7 @@
 #define ARCHI_IDMA_EXT_GLOBAL_ADDR(cid)            ( ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_IDMA_EXT_OFFSET )
 #define ARCHI_HMR_GLOBAL_ADDR(cid)                 ( ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_HMR_OFFSET )
 #define ARCHI_TCDM_SCRUBBER_GLOBAL_ADDR(cid)       ( ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_TCDM_SCRUBBER_OFFSET )
+#define ARCHI_HWPE_HCI_ECC_GLOBAL_ADDR(cid)        ( ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_HWPE_HCI_ECC_OFFSET )
 
 
 /*

include/archi/chips/carfield-cluster/properties.h

@@ -89,7 +89,7 @@
 #define ARCHI_HAS_CLUSTER   1
 #define ARCHI_L1_TAS_BIT    20
 #ifndef ARCHI_CLUSTER_NB_PE
-#define ARCHI_CLUSTER_NB_PE 12
+#define ARCHI_CLUSTER_NB_PE 8
 #endif
 #define ARCHI_NB_CLUSTER    1
 

include/archi/chips/carfield-cluster/pulp.h

@@ -47,5 +47,6 @@
 #include "archi/udma/udma_v3.h"
 #include "archi/hmr/hmr_v1.h"
 #include "archi/tcdm_scrubber/tcdm_scrubber.h"
+#include "archi/hwpe_hci_ecc/hwpe_hci_ecc.h"
 
 #endif

include/archi/chips/pulp_cluster/memory_map.h

@@ -113,6 +113,7 @@
 #define ARCHI_HMR_ADDR                             ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_HMR_OFFSET )
 #define ARCHI_TCDM_SCRUBBER_ADDR                   ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_TCDM_SCRUBBER_OFFSET )
 #define ARCHI_HWPE_HCI_ECC_ADDR                    ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_HWPE_HCI_ECC_OFFSET )
+#define ARCHI_IDMA_EXT_ADDR                         ARCHI_MCHAN_EXT_ADDR
 
 #define ARCHI_CLUSTER_CTRL_GLOBAL_ADDR(cid)        ( ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_CTRL_OFFSET )
 #define ARCHI_ICACHE_CTRL_GLOBAL_ADDR(cid)         ( ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_ICACHE_CTRL_OFFSET )
@@ -132,11 +133,14 @@
 
 #define ARCHI_EU_DEMUX_OFFSET                 ( 0x00000 )
 #define ARCHI_MCHAN_DEMUX_OFFSET              ( 0x00400 )
+#define ARCHI_IDMA_DEMUX_OFFSET               ARCHI_MCHAN_DEMUX_OFFSET
 
 
 #define ARCHI_DEMUX_PERIPHERALS_ADDR          ( ARCHI_CLUSTER_ADDR + ARCHI_DEMUX_PERIPHERALS_OFFSET )
 
 #define ARCHI_EU_DEMUX_ADDR                   ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_EU_DEMUX_OFFSET )
 #define ARCHI_MCHAN_DEMUX_ADDR                ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET )
 
+#define ARCHI_IDMA_DEMUX_ADDR                 ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_IDMA_DEMUX_OFFSET )
+
 #endif

include/archi/chips/pulp_cluster/properties.h

@@ -18,6 +18,8 @@
 #ifndef __ARCHI_CHIPS_PULP_PROPERTIES_H__
 #define __ARCHI_CHIPS_PULP_PROPERTIES_H__
 
+#define ARCHI_HAS_DMA_DEMUX 1
+
 /*
  * FPGA
  */

include/archi/chips/pulp_cluster/pulp.h

@@ -37,8 +37,12 @@
 #include "archi/chips/pulp_cluster/memory_map.h"
 #include "archi/chips/pulp_cluster/apb_soc.h"
 #include "archi/stdout/stdout_v3.h"
+
 #include "archi/dma/mchan_v7.h"
 
+#include "archi/dma/idma_v2.h"
+
+
 #include "archi/udma/cpi/udma_cpi_v1.h"
 #include "archi/udma/i2c/udma_i2c_v2.h"
 #include "archi/udma/i2s/udma_i2s_v2.h"

include/archi/dma/idma_v2.h

@@ -0,0 +1,106 @@
+// Generated register defines for idma_reg32_3d
+
+// Copyright information found in source file:
+// Copyright 2023 ETH Zurich and University of Bologna.
+
+// Licensing information found in source file:
+// 
+// SPDX-License-Identifier: SHL-0.51
+
+#ifndef _IDMA_REG32_3D_REG_DEFS_
+#define _IDMA_REG32_3D_REG_DEFS_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+// Number of dimensions available
+#define IDMA_REG32_3D_PARAM_NUM_DIMS 3
+
+// Register width
+#define IDMA_REG32_3D_PARAM_REG_WIDTH 32
+
+// Configuration Register for DMA settings
+#define IDMA_REG32_3D_CONF_REG_OFFSET 0x0
+#define IDMA_REG32_3D_CONF_DECOUPLE_AW_BIT 0
+#define IDMA_REG32_3D_CONF_DECOUPLE_RW_BIT 1
+#define IDMA_REG32_3D_CONF_SRC_REDUCE_LEN_BIT 2
+#define IDMA_REG32_3D_CONF_DST_REDUCE_LEN_BIT 3
+#define IDMA_REG32_3D_CONF_SRC_MAX_LLEN_MASK 0x7
+#define IDMA_REG32_3D_CONF_SRC_MAX_LLEN_OFFSET 4
+#define IDMA_REG32_3D_CONF_SRC_MAX_LLEN_FIELD \
+  ((bitfield_field32_t) { .mask = IDMA_REG32_3D_CONF_SRC_MAX_LLEN_MASK, .index = IDMA_REG32_3D_CONF_SRC_MAX_LLEN_OFFSET })
+#define IDMA_REG32_3D_CONF_DST_MAX_LLEN_MASK 0x7
+#define IDMA_REG32_3D_CONF_DST_MAX_LLEN_OFFSET 7
+#define IDMA_REG32_3D_CONF_DST_MAX_LLEN_FIELD \
+  ((bitfield_field32_t) { .mask = IDMA_REG32_3D_CONF_DST_MAX_LLEN_MASK, .index = IDMA_REG32_3D_CONF_DST_MAX_LLEN_OFFSET })
+#define IDMA_REG32_3D_CONF_ENABLE_ND_MASK 0x3
+#define IDMA_REG32_3D_CONF_ENABLE_ND_OFFSET 10
+#define IDMA_REG32_3D_CONF_ENABLE_ND_FIELD \
+  ((bitfield_field32_t) { .mask = IDMA_REG32_3D_CONF_ENABLE_ND_MASK, .index = IDMA_REG32_3D_CONF_ENABLE_ND_OFFSET })
+#define IDMA_REG32_3D_CONF_SRC_PROTOCOL_MASK 0x7
+#define IDMA_REG32_3D_CONF_SRC_PROTOCOL_OFFSET 12
+#define IDMA_REG32_3D_CONF_SRC_PROTOCOL_FIELD \
+  ((bitfield_field32_t) { .mask = IDMA_REG32_3D_CONF_SRC_PROTOCOL_MASK, .index = IDMA_REG32_3D_CONF_SRC_PROTOCOL_OFFSET })
+#define IDMA_REG32_3D_CONF_DST_PROTOCOL_MASK 0x7
+#define IDMA_REG32_3D_CONF_DST_PROTOCOL_OFFSET 15
+#define IDMA_REG32_3D_CONF_DST_PROTOCOL_FIELD \
+  ((bitfield_field32_t) { .mask = IDMA_REG32_3D_CONF_DST_PROTOCOL_MASK, .index = IDMA_REG32_3D_CONF_DST_PROTOCOL_OFFSET })
+
+// DMA Status
+#define IDMA_REG32_3D_STATUS_0_REG_OFFSET 0x4
+#define IDMA_REG32_3D_STATUS_0_BUSY_0_MASK 0x3ff
+#define IDMA_REG32_3D_STATUS_0_BUSY_0_OFFSET 0
+#define IDMA_REG32_3D_STATUS_0_BUSY_0_FIELD \
+  ((bitfield_field32_t) { .mask = IDMA_REG32_3D_STATUS_0_BUSY_0_MASK, .index = IDMA_REG32_3D_STATUS_0_BUSY_0_OFFSET })
+
+// DMA Status
+#define IDMA_REG32_3D_STATUS_1_REG_OFFSET 0x8
+#define IDMA_REG32_3D_STATUS_1_BUSY_1_MASK 0x3ff
+#define IDMA_REG32_3D_STATUS_1_BUSY_1_OFFSET 0
+#define IDMA_REG32_3D_STATUS_1_BUSY_1_FIELD \
+  ((bitfield_field32_t) { .mask = IDMA_REG32_3D_STATUS_1_BUSY_1_MASK, .index = IDMA_REG32_3D_STATUS_1_BUSY_1_OFFSET })
+
+// Next ID, launches transfer, returns 0 if transfer not set up properly.
+#define IDMA_REG32_3D_NEXT_ID_0_REG_OFFSET 0xc
+
+// Next ID, launches transfer, returns 0 if transfer not set up properly.
+#define IDMA_REG32_3D_NEXT_ID_1_REG_OFFSET 0x10
+
+// Get ID of finished transactions.
+#define IDMA_REG32_3D_DONE_ID_0_REG_OFFSET 0x14
+
+// Get ID of finished transactions.
+#define IDMA_REG32_3D_DONE_ID_1_REG_OFFSET 0x18
+
+// Low destination address
+#define IDMA_REG32_3D_DST_ADDR_LOW_REG_OFFSET 0xd0
+
+// Low source address
+#define IDMA_REG32_3D_SRC_ADDR_LOW_REG_OFFSET 0xd8
+
+// Low transfer length in byte
+#define IDMA_REG32_3D_LENGTH_LOW_REG_OFFSET 0xe0
+
+// Low destination stride dimension 2
+#define IDMA_REG32_3D_DST_STRIDE_2_LOW_REG_OFFSET 0xe8
+
+// Low source stride dimension 2
+#define IDMA_REG32_3D_SRC_STRIDE_2_LOW_REG_OFFSET 0xf0
+
+// Low number of repetitions dimension 2
+#define IDMA_REG32_3D_REPS_2_LOW_REG_OFFSET 0xf8
+
+// Low destination stride dimension 3
+#define IDMA_REG32_3D_DST_STRIDE_3_LOW_REG_OFFSET 0x100
+
+// Low source stride dimension 3
+#define IDMA_REG32_3D_SRC_STRIDE_3_LOW_REG_OFFSET 0x108
+
+// Low number of repetitions dimension 3
+#define IDMA_REG32_3D_REPS_3_LOW_REG_OFFSET 0x110
+
+#ifdef __cplusplus
+}  // extern "C"
+#endif
+#endif  // _IDMA_REG32_3D_REG_DEFS_
+// End generated register defines for idma_reg32_3d

include/hal/chips/carfield-cluster/pulp.h

@@ -43,5 +43,6 @@
 #include "hal/udma/uart/udma_uart_v1.h"
 #include "hal/hmr/hmr_v1.h"
 #include "hal/tcdm_scrubber/tcdm_scrubber.h"
+#include "hal/hwpe_hci_ecc/hwpe_hci_ecc.h"
 
 #endif

include/hal/chips/pulp_cluster/pulp.h

@@ -26,7 +26,6 @@
 #endif // __ibex__
 #include "hal/eu/eu_v3.h"
 #include "hal/itc/itc_v1.h"
-#include "hal/dma/mchan_v7.h"
 #include "hal/timer/timer_v2.h"
 #include "hal/soc_eu/soc_eu_v2.h"
 #include "hal/cluster_ctrl/cluster_ctrl_v2.h"
@@ -45,4 +44,8 @@
 #include "hal/tcdm_scrubber/tcdm_scrubber.h"
 #include "hal/hwpe_hci_ecc/hwpe_hci_ecc.h"
 
+#include "hal/dma/mchan_v7.h"
+
+#include "hal/dma/idma_v2.h"
+
 #endif

include/hal/cluster_ctrl/cluster_ctrl_v2.h

@@ -71,4 +71,12 @@ static inline void hal_cluster_ctrl_return_set_remote(int cid, int value){
   pulp_write32(ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid)+ARCHI_CLUSTER_CTRL_OFFSET+ARCHI_CLUSTER_CTRL_RETURN, value | 1 << ARCHI_CLUSTER_CTRL_RETURN_SHIFT_BITS);
 }
 
+static inline void plp_ctrl_cluster_cfg_set(unsigned int mask) {
+  pulp_write32(ARCHI_CLUSTER_CTRL_ADDR + ARCHI_CLUSTER_CTRL_CLUSTER_CFG, mask);
+}
+
+static inline int plp_ctrl_cluster_cfg_get() {
+  return pulp_read32(ARCHI_CLUSTER_CTRL_ADDR + ARCHI_CLUSTER_CTRL_CLUSTER_CFG);
+}
+
 #endif