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    85 repositories

    • sky130-fabulous-testchip

      Public
      A test chip featuring three different FPGA fabrics and custom padring, compatible with Caravel's bondpads.
      SystemVerilog
      •1•0•0•0•Updated Apr 28, 2026Apr 28, 2026

    • ip_unit

      Public
      IP unit monorepo (cocotb/pyuvm verification)
      Verilog
      •0•0•0•0•Updated Apr 26, 2026Apr 26, 2026

    • CF_I2C

      Public
      Verilog
      •
      Other
      •1•0•6•4•Updated Apr 26, 2026Apr 26, 2026

    • CF_SPI

      Public
      Verilog
      •
      Other
      •1•0•5•8•Updated Apr 26, 2026Apr 26, 2026

    • CF_UART

      Public
      Verilog
      •
      Other
      •1•0•8•3•Updated Apr 26, 2026Apr 26, 2026

    • CF_I2S

      Public
      Verilog
      •
      Other
      •1•0•6•2•Updated Apr 26, 2026Apr 26, 2026

    • cf-precheck

      Public
      Shell
      •
      Apache License 2.0
      •1•2•41•0•Updated Apr 24, 2026Apr 24, 2026

    • caravel_user_project

      Public template
      Verilog
      •
      Apache License 2.0
      •15•17•57•4•Updated Apr 23, 2026Apr 23, 2026

    • CF_TMR32

      Public
      Python
      •
      Other
      •1•0•2•5•Updated Apr 23, 2026Apr 23, 2026

    • CF_SHA256

      Public
      Verilog
      •5•0•0•0•Updated Apr 23, 2026Apr 23, 2026

    • cf-cli

      Public
      Python
      •
      Apache License 2.0
      •2•0•0•0•Updated Apr 21, 2026Apr 21, 2026

    • cf_verify

      Public
      Universal IP Verification Framework for ChipFoundry IPs — pyuvm + cocotb
      Python
      •0•0•0•0•Updated Apr 14, 2026Apr 14, 2026

    • caravel-lite

      Public
      Verilog
      •
      Apache License 2.0
      •1•0•5•0•Updated Mar 30, 2026Mar 30, 2026

    • caravel

      Public
      Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
      Verilog
      •
      Apache License 2.0
      •105•4•0•0•Updated Mar 30, 2026Mar 30, 2026

    • ipm

      Public
      Python
      •
      Apache License 2.0
      •3•4•7•1•Updated Mar 6, 2026Mar 6, 2026

    • openframe_webinar_demo

      Public
      Python
      •
      Apache License 2.0
      •0•0•0•0•Updated Feb 11, 2026Feb 11, 2026

    • CF_gpio_config

      Public
      Verilog
      •
      Apache License 2.0
      •1•0•0•0•Updated Feb 10, 2026Feb 10, 2026

    • multi-die_openframe_template

      Public
      Verilog
      •
      Apache License 2.0
      •0•0•0•0•Updated Feb 9, 2026Feb 9, 2026

    • openframe_user_project

      Public template
      Verilog
      •
      Apache License 2.0
      •5•9•1•2•Updated Feb 9, 2026Feb 9, 2026

    • caravel_mgmt_soc_litex

      Public
      Verilog
      •
      Apache License 2.0
      •28•1•0•6•Updated Feb 9, 2026Feb 9, 2026

    • caravel-sim-infrastructure

      Public
      HTML
      •
      Apache License 2.0
      •1•0•4•6•Updated Feb 9, 2026Feb 9, 2026

    • chipdiscover-verilog-example

      Public
      Verilog
      •
      Apache License 2.0
      •0•0•0•0•Updated Feb 1, 2026Feb 1, 2026

    • tt-support-tools

      Public
      tools used by project repos to test configuration, generate OpenLane run summaries and documentation
      Python
      •
      Apache License 2.0
      •34•0•0•0•Updated Feb 1, 2026Feb 1, 2026

    • frigate

      Public
      Verilog
      •
      Apache License 2.0
      •14•3•0•0•Updated Jan 22, 2026Jan 22, 2026

    • caravel_board

      Public
      C
      •0•0•10•1•Updated Jan 16, 2026Jan 16, 2026

    • sky130_ef_ip__adc3v_12bit

      Public
      Verilog
      •
      Apache License 2.0
      •1•3•0•0•Updated Jan 12, 2026Jan 12, 2026

    • CF_SRAM_1024x32

      Public
      Verilog
      •
      Apache License 2.0
      •1•1•0•0•Updated Dec 16, 2025Dec 16, 2025

    • CF_SRAM_16384x32

      Public
      Commercial 16384x32 SRAM (64KB) - Wishbone compliant memory macro
      Verilog
      •
      Apache License 2.0
      •0•1•0•0•Updated Dec 9, 2025Dec 9, 2025

    • CF_SRAM_8192x32

      Public
      32KB SRAM macro (8192 words × 32 bits) built from 8 × 1024x32 SRAM macros with Wishbone B4 interface
      Verilog
      •
      Apache License 2.0
      •0•0•0•0•Updated Dec 8, 2025Dec 8, 2025

    • nydesign-cc2509

      Public
      Tiny Tapeout SKY 25b shuttle using sky130A PDK on ChipFoundry CC2511 MPW
      Verilog
      •
      Apache License 2.0
      •12•0•0•0•Updated Dec 6, 2025Dec 6, 2025
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