Add: port comm + deferred completion to a5 onboard

[jvjhfhg]

• Mirror comm_hccl.cpp from a2a3 onboard host (HCCL backend with DIY IPC windows). SDMA workspace overlay is added in the follow-up commit so this base alone does not depend on PTO_ISA_ROOT or libnnopbase, and does not invoke aclnnShmemSdmaStarsQuery at comm_init -- which keeps non-SDMA comm demos unaffected by the current CANN-9.x SDMA-on-a5 gap.
• Graft ensure_acl_ready / create_comm_stream / destroy_comm_stream into a5 DeviceRunner and gate aclrtResetDevice + aclFinalize on acl_ready_ in finalize(); preserve raw rtDeviceReset for pure rt-layer callers.
• Replace pto_runtime_c_api.cpp comm/ACL stubs with forwarding implementations; comm_* C ABI now comes from comm_hccl.cpp.
• Upgrade a5 trb deferred-completion runtime from counter-only to pluggable backend-ops design: CompletionCondition gains completion_type/addr/retired fields, CompletionBackendOps table routes COMPLETION_TYPE_{COUNTER,SDMA_EVENT_RECORD}, scheduler invalidates counter cache lines before polling and retires satisfied conditions.
• Copy backend/sdma/{kernel,scheduler}.h to a5 (kernel-side, dormant until a kernel registers a SDMA condition; a5 pto-isa already exposes SDMA via PTO_NPU_ARCH_A5).
• a5 onboard CMakeLists adds hcomm find_library (FATAL_ERROR on miss).
• Fix Stride ambiguity in async_notify_demo kernels (pto:: qualifier to disambiguate from bisheng's enum class Stride).
• Enable a5 in allreduce_distributed and test_platform_comm platform marks; parametrize the latter via st_platform.
• Convert ported runtime headers to #pragma once on both arches so aicore_completion_mailbox.h / pto_completion_token.h / pto_async_{wait,kernel_api}.h / backend/sdma/*.h are now byte- identical across a2a3 and a5.

Verified: a2a3 onboard, a5 onboard, a5 sim trb runtime builds all clean. No hardware tests run.

[gemini-code-assist]

Code Review

This pull request implements the HCCL backend for distributed communication on the a5 platform, replacing previous stubs with a functional implementation using ACL IPC primitives. It introduces a symmetric memory pool, updates the DeviceRunner for ACL lifecycle management, and refactors the runtime scheduler to support both counter-based and SDMA event record completion types. Additionally, header guards are modernized to "#pragma once" across several files. Feedback identifies a high-severity issue in the scheduler where the async_ctx.completion_entries array lacks necessary cache invalidation before processing, potentially leading to stale data reads from Global Memory.