Vp46xx reset pin backport#899
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The button sits on a single function pin of the IT8786. Enabled the chip's GPIO block in devicetree.cb, and configured the GP80 pin as an input in bootblock. Mapped to /dev/port at `0xa07` bit `2`. Upstream-Status: Inappropriate [Dasharo downstream] Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Add a generic driver to configure GPIOs and LEDs on common ITE SuperIOs. The driver supports most ITE SuperIOs, except Embedded Controllers. The driver allows configuring every GPIO property with pin granularity. Verified against datasheets of all ITE SIOs currently supported by coreboot, except IT8721F (assumed to be the same as IT8720F), IT8623E and IT8629E. Change-Id: If610d2809b56c63444c3406c26fad412c94136a5 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83355 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Partial cherry-pick of 1667957 by Michał Żygowski Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com> Co-authored-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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