Skip to content

Fix specification of FP16 scalar conversion to/from fixed point #435

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
momchil-velikov wants to merge 1 commit into
base: main
Choose a base branch
from
+16 −16
Open

Fix specification of FP16 scalar conversion to/from fixed point #435

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
16 changes: 8 additions & 8 deletions neon_intrinsics/advsimd.md
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5166,17 +5166,17 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
| <code>uint32_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_u32_f16" target="_blank">vcvtph_u32_f16</a>(float16_t a)</code> | `a -> Hn` | `FCVTPU Sd/Wd,Hn` | `Sd/Wd -> result` | `A64` |
| <code>uint64_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_u64_f16" target="_blank">vcvtph_u64_f16</a>(float16_t a)</code> | `a -> Hn` | `FCVTPU Dd/Xd,Hn` | `Dd/Xd -> result` | `A64` |
| <code>float16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s16" target="_blank">vcvth_n_f16_s16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int16_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int n)</code> | `a -> Hn`<br>`1 <= n <= 16` | `SCVTF Hd,Hn,#n` | `Hd -> result` | `A64` |
| <code>float16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s32" target="_blank">vcvth_n_f16_s32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int32_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int n)</code> | `a -> Hn`<br>`1 <= n <= 16` | `SCVTF Hd,Hn,#n` | `Hd -> result` | `A32/A64` |
| <code>float16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s64" target="_blank">vcvth_n_f16_s64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int64_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int n)</code> | `a -> Hn`<br>`1 <= n <= 16` | `SCVTF Hd,Hn,#n` | `Hd -> result` | `A64` |
| <code>float16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s32" target="_blank">vcvth_n_f16_s32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int32_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int n)</code> | `a -> Hn`<br>`1 <= n <= 16` | `SCVTF Hd,Wn,#n` | `Hd -> result` | `A64` |
| <code>float16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s64" target="_blank">vcvth_n_f16_s64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int64_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int n)</code> | `a -> Hn`<br>`1 <= n <= 16` | `SCVTF Hd,Xn,#n` | `Hd -> result` | `A64` |
| <code>float16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u16" target="_blank">vcvth_n_f16_u16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; uint16_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int n)</code> | `a -> Hn`<br>`1 <= n <= 16` | `UCVTF Hd,Hn,#n` | `Hd -> result` | `A64` |
| <code>float16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u32" target="_blank">vcvth_n_f16_u32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; uint32_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int n)</code> | `a -> Hn`<br>`1 <= n <= 16` | `UCVTF Hd,Hn,#n` | `Hd -> result` | `A32/A64` |
| <code>float16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u64" target="_blank">vcvth_n_f16_u64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; uint64_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int n)</code> | `a -> Hn`<br>`1 <= n <= 16` | `UCVTF Hd,Hn,#n` | `Hd -> result` | `A64` |
| <code>float16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u32" target="_blank">vcvth_n_f16_u32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; uint32_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int n)</code> | `a -> Hn`<br>`1 <= n <= 16` | `UCVTF Hd,Wn,#n` | `Hd -> result` | `A64` |
| <code>float16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u64" target="_blank">vcvth_n_f16_u64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; uint64_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int n)</code> | `a -> Hn`<br>`1 <= n <= 16` | `UCVTF Hd,Xn,#n` | `Hd -> result` | `A64` |
| <code>int16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s16_f16" target="_blank">vcvth_n_s16_f16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float16_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int n)</code> | `a -> Hn`<br>`1 <= n <= 16` | `FCVTZS Hd,Hn,#n` | `Hd -> result` | `A64` |
| <code>int32_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s32_f16" target="_blank">vcvth_n_s32_f16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float16_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int n)</code> | `a -> Hn`<br>`1 <= n <= 16` | `FCVTZS Hd,Hn,#n` | `Hd -> result` | `A32/A64` |
| <code>int64_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s64_f16" target="_blank">vcvth_n_s64_f16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float16_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int n)</code> | `a -> Hn`<br>`1 <= n <= 16` | `FCVTZS Hd,Hn,#n` | `Hd -> result` | `A64` |
| <code>int32_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s32_f16" target="_blank">vcvth_n_s32_f16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float16_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int n)</code> | `a -> Hn`<br>`1 <= n <= 16` | `FCVTZS Wd,Hn,#n` | `Hd -> result` | `A64` |
| <code>int64_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s64_f16" target="_blank">vcvth_n_s64_f16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float16_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int n)</code> | `a -> Hn`<br>`1 <= n <= 16` | `FCVTZS Xd,Hn,#n` | `Hd -> result` | `A64` |
| <code>uint16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u16_f16" target="_blank">vcvth_n_u16_f16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float16_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int n)</code> | `a -> Hn`<br>`1 <= n <= 16` | `FCVTZU Hd,Hn,#n` | `Hd -> result` | `A64` |
| <code>uint32_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u32_f16" target="_blank">vcvth_n_u32_f16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float16_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int n)</code> | `a -> Hn`<br>`1 <= n <= 16` | `FCVTZU Hd,Hn,#n` | `Hd -> result` | `A32/A64` |
| <code>uint64_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u64_f16" target="_blank">vcvth_n_u64_f16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float16_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int n)</code> | `a -> Hn`<br>`1 <= n <= 16` | `FCVTZU Hd,Hn,#n` | `Hd -> result` | `A64` |
| <code>uint32_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u32_f16" target="_blank">vcvth_n_u32_f16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float16_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int n)</code> | `a -> Hn`<br>`1 <= n <= 16` | `FCVTZU Wd,Hn,#n` | `Hd -> result` | `A64` |
| <code>uint64_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u64_f16" target="_blank">vcvth_n_u64_f16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float16_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int n)</code> | `a -> Hn`<br>`1 <= n <= 16` | `FCVTZU Xd,Hn,#n` | `Hd -> result` | `A64` |

### Logical

Expand Down
16 changes: 8 additions & 8 deletions tools/intrinsic_db/advsimd.csv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4156,17 +4156,17 @@ uint16_t vcgth_f16(float16_t a, float16_t b) a -> Hn;b -> Hm FCMGT Hd,Hn,Hm Hd -
uint16_t vcleh_f16(float16_t a, float16_t b) a -> Hn;b -> Hm FCMGE Hd,Hn,Hm Hd -> result A64
uint16_t vclth_f16(float16_t a, float16_t b) a -> Hn;b -> Hm FCMGT Hd,Hn,Hm Hd -> result A64
float16_t vcvth_n_f16_s16(int16_t a, __builtin_constant_p(n)) a -> Hn;1 <= n <= 16 SCVTF Hd,Hn,#n Hd -> result A64
float16_t vcvth_n_f16_s32(int32_t a, __builtin_constant_p(n)) a -> Hn;1 <= n <= 16 SCVTF Hd,Hn,#n Hd -> result A32/A64
float16_t vcvth_n_f16_s64(int64_t a, __builtin_constant_p(n)) a -> Hn;1 <= n <= 16 SCVTF Hd,Hn,#n Hd -> result A64
float16_t vcvth_n_f16_s32(int32_t a, __builtin_constant_p(n)) a -> Hn;1 <= n <= 16 SCVTF Hd,Wn,#n Hd -> result A64
float16_t vcvth_n_f16_s64(int64_t a, __builtin_constant_p(n)) a -> Hn;1 <= n <= 16 SCVTF Hd,Xn,#n Hd -> result A64
float16_t vcvth_n_f16_u16(uint16_t a, __builtin_constant_p(n)) a -> Hn;1 <= n <= 16 UCVTF Hd,Hn,#n Hd -> result A64
float16_t vcvth_n_f16_u32(uint32_t a, __builtin_constant_p(n)) a -> Hn;1 <= n <= 16 UCVTF Hd,Hn,#n Hd -> result A32/A64
float16_t vcvth_n_f16_u64(uint64_t a, __builtin_constant_p(n)) a -> Hn;1 <= n <= 16 UCVTF Hd,Hn,#n Hd -> result A64
float16_t vcvth_n_f16_u32(uint32_t a, __builtin_constant_p(n)) a -> Hn;1 <= n <= 16 UCVTF Hd,Wn,#n Hd -> result A64
float16_t vcvth_n_f16_u64(uint64_t a, __builtin_constant_p(n)) a -> Hn;1 <= n <= 16 UCVTF Hd,Xn,#n Hd -> result A64
int16_t vcvth_n_s16_f16(float16_t a, __builtin_constant_p(n)) a -> Hn;1 <= n <= 16 FCVTZS Hd,Hn,#n Hd -> result A64
int32_t vcvth_n_s32_f16(float16_t a, __builtin_constant_p(n)) a -> Hn;1 <= n <= 16 FCVTZS Hd,Hn,#n Hd -> result A32/A64
int64_t vcvth_n_s64_f16(float16_t a, __builtin_constant_p(n)) a -> Hn;1 <= n <= 16 FCVTZS Hd,Hn,#n Hd -> result A64
int32_t vcvth_n_s32_f16(float16_t a, __builtin_constant_p(n)) a -> Hn;1 <= n <= 16 FCVTZS Wd,Hn,#n Hd -> result A64
int64_t vcvth_n_s64_f16(float16_t a, __builtin_constant_p(n)) a -> Hn;1 <= n <= 16 FCVTZS Xd,Hn,#n Hd -> result A64
uint16_t vcvth_n_u16_f16(float16_t a, __builtin_constant_p(n)) a -> Hn;1 <= n <= 16 FCVTZU Hd,Hn,#n Hd -> result A64
uint32_t vcvth_n_u32_f16(float16_t a, __builtin_constant_p(n)) a -> Hn;1 <= n <= 16 FCVTZU Hd,Hn,#n Hd -> result A32/A64
uint64_t vcvth_n_u64_f16(float16_t a, __builtin_constant_p(n)) a -> Hn;1 <= n <= 16 FCVTZU Hd,Hn,#n Hd -> result A64
uint32_t vcvth_n_u32_f16(float16_t a, __builtin_constant_p(n)) a -> Hn;1 <= n <= 16 FCVTZU Wd,Hn,#n Hd -> result A64
uint64_t vcvth_n_u64_f16(float16_t a, __builtin_constant_p(n)) a -> Hn;1 <= n <= 16 FCVTZU Xd,Hn,#n Hd -> result A64
float16_t vdivh_f16(float16_t a, float16_t b) a -> Hn;b -> Hm FDIV Hd,Hn,Hm Hd -> result A32/A64
float16_t vmaxh_f16(float16_t a, float16_t b) a -> Hn;b -> Hm FMAX Hd,Hn,Hm Hd -> result A64
float16_t vmaxnmh_f16(float16_t a, float16_t b) a -> Hn;b -> Hm FMAXNM Hd,Hn,Hm Hd -> result A32/A64
Expand Down
Loading