diff --git a/cores/arduino/stm32/stm32_def_build.h b/cores/arduino/stm32/stm32_def_build.h index ae3d823f19..ae38cf1d69 100644 --- a/cores/arduino/stm32/stm32_def_build.h +++ b/cores/arduino/stm32/stm32_def_build.h @@ -446,10 +446,18 @@ #define CMSIS_STARTUP_FILE "startup_stm32u073xx.s" #elif defined(STM32U083xx) #define CMSIS_STARTUP_FILE "startup_stm32u083xx.s" + #elif defined(STM32U356xx) + #define CMSIS_STARTUP_FILE "startup_stm32u356xx.s" + #elif defined(STM32U366xx) + #define CMSIS_STARTUP_FILE "startup_stm32u366xx.s" #elif defined(STM32U375xx) #define CMSIS_STARTUP_FILE "startup_stm32u375xx.s" #elif defined(STM32U385xx) #define CMSIS_STARTUP_FILE "startup_stm32u385xx.s" + #elif defined(STM32U3B5xx) + #define CMSIS_STARTUP_FILE "startup_stm32u3b5xx.s" + #elif defined(STM32U3C5xx) + #define CMSIS_STARTUP_FILE "startup_stm32u3c5xx.s" #elif defined(STM32U535xx) #define CMSIS_STARTUP_FILE "startup_stm32u535xx.s" #elif defined(STM32U545xx) diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hsp.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hsp.c new file mode 100644 index 0000000000..cfb63cc209 --- /dev/null +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hsp.c @@ -0,0 +1,8 @@ +/* HAL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#ifdef STM32U3xx + #include "stm32u3xx_hal_hsp.c" +#endif +#pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lcd.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lcd.c index 34dc969921..606934cf29 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lcd.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lcd.c @@ -10,6 +10,8 @@ #include "stm32l4xx_hal_lcd.c" #elif STM32U0xx #include "stm32u0xx_hal_lcd.c" +#elif STM32U3xx + #include "stm32u3xx_hal_lcd.c" #elif STM32WBxx #include "stm32wbxx_hal_lcd.c" #elif STM32WL3x diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/Templates/partition_stm32u335xx.h b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/Templates/partition_stm32u335xx.h new file mode 100644 index 0000000000..ceb64e0b4e --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/Templates/partition_stm32u335xx.h @@ -0,0 +1,618 @@ +/** + ****************************************************************************** + * @file partition_stm32u335xx.h + * @author MCD Application Team + * @brief CMSIS STM32U335xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef PARTITION_STM32U335XX_H +#define PARTITION_STM32U335XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0803FFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 0 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x0BF80000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x0BFAFFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x0C01E000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x0C01FFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 1 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x10000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x17FFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x20000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x20003FFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x2000C000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x20013FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x40000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x4FFFFFFF /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x90000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x9FFFFFFF /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_PVM_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + + +/* +// Interrupts 32..63 +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + + +/* +// Interrupts 64..95 +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// COMP_IRQn <0=> Secure state <1=> Non-Secure state +// USB_FS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// TSC_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..125) +*/ +#define NVIC_INIT_ITNS3 1 + + +/* +// Interrupts 96..125 +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// ADF1_IRQn <0=> Secure state <1=> Non-Secure state +// PWR_IRQn <0=> Secure state <1=> Non-Secure state +// PWR_S_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + +} + +#endif /* PARTITION_STM32U335XX_H */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/Templates/partition_stm32u345xx.h b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/Templates/partition_stm32u345xx.h new file mode 100644 index 0000000000..41dbfab0f9 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/Templates/partition_stm32u345xx.h @@ -0,0 +1,619 @@ +/** + ****************************************************************************** + * @file partition_stm32u345xx.h + * @author MCD Application Team + * @brief CMSIS STM32U345xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef PARTITION_STM32U345XX_H +#define PARTITION_STM32U345XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0803FFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 0 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x0BF80000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x0BFAFFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x0C01E000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x0C01FFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 1 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x10000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x17FFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x20000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x20003FFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x2000C000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x20013FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x40000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x4FFFFFFF /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x90000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x9FFFFFFF /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_PVM_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + + +/* +// Interrupts 32..63 +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + + +/* +// Interrupts 64..95 +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// COMP_IRQn <0=> Secure state <1=> Non-Secure state +// USB_FS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// TSC_IRQn <0=> Secure state <1=> Non-Secure state +// AES_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..125) +*/ +#define NVIC_INIT_ITNS3 1 + + +/* +// Interrupts 96..125 +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// ADF1_IRQn <0=> Secure state <1=> Non-Secure state +// PWR_IRQn <0=> Secure state <1=> Non-Secure state +// PWR_S_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + +} + +#endif /* PARTITION_STM32U345XX_H */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/Templates/partition_stm32u356xx.h b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/Templates/partition_stm32u356xx.h new file mode 100644 index 0000000000..8fa28538d3 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/Templates/partition_stm32u356xx.h @@ -0,0 +1,630 @@ +/** + ****************************************************************************** + * @file partition_stm32u356xx.h + * @author MCD Application Team + * @brief CMSIS STM32U356xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef PARTITION_STM32U356XX_H +#define PARTITION_STM32U356XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x080FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 0 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x0BF80000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x0BFAFFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x0C07E000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x0C07FFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 1 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x10000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x17FFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x20010000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x2001FFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x20028000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x2002FFFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x40000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x4FFFFFFF /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x90000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x9FFFFFFF /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_PVM_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// SAES_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + + +/* +// Interrupts 32..63 +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + + +/* +// Interrupts 64..95 +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// COMP_IRQn <0=> Secure state <1=> Non-Secure state +// USB_FS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// TSC_IRQn <0=> Secure state <1=> Non-Secure state +// AES_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..125) +*/ +#define NVIC_INIT_ITNS3 1 + + +/* +// Interrupts 96..125 +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// I3C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// ADF1_IRQn <0=> Secure state <1=> Non-Secure state +// ADC2_IRQn <0=> Secure state <1=> Non-Secure state +// PWR_IRQn <0=> Secure state <1=> Non-Secure state +// PWR_S_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + +} + +#endif /* PARTITION_STM32U356XX_H */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/Templates/partition_stm32u366xx.h b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/Templates/partition_stm32u366xx.h new file mode 100644 index 0000000000..7af3b232b1 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/Templates/partition_stm32u366xx.h @@ -0,0 +1,630 @@ +/** + ****************************************************************************** + * @file partition_stm32u366xx.h + * @author MCD Application Team + * @brief CMSIS STM32U366xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef PARTITION_STM32U366XX_H +#define PARTITION_STM32U366XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x080FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 0 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x0BF80000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x0BFAFFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x0C07E000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x0C07FFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 1 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x10000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x17FFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x20010000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x2001FFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x20028000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x2002FFFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x40000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x4FFFFFFF /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x90000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x9FFFFFFF /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_PVM_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// SAES_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + + +/* +// Interrupts 32..63 +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + + +/* +// Interrupts 64..95 +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// COMP_IRQn <0=> Secure state <1=> Non-Secure state +// USB_FS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// TSC_IRQn <0=> Secure state <1=> Non-Secure state +// AES_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..125) +*/ +#define NVIC_INIT_ITNS3 1 + + +/* +// Interrupts 96..125 +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// I3C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// ADF1_IRQn <0=> Secure state <1=> Non-Secure state +// ADC2_IRQn <0=> Secure state <1=> Non-Secure state +// PWR_IRQn <0=> Secure state <1=> Non-Secure state +// PWR_S_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + +} + +#endif /* PARTITION_STM32U366XX_H */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/partition_stm32u3xx.h b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/partition_stm32u3xx.h index 7c572e0020..d8be2742e7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/partition_stm32u3xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/partition_stm32u3xx.h @@ -41,11 +41,14 @@ /** @addtogroup Secure_configuration_section * @{ */ - #if defined(STM32U375xx) #include "partition_stm32u375xx.h" #elif defined(STM32U385xx) #include "partition_stm32u385xx.h" +#elif defined(STM32U3B5xx) + #include "partition_stm32u3b5xx.h" +#elif defined(STM32U3C5xx) + #include "partition_stm32u3c5xx.h" #else #error "Please select first the target STM32U3xx device used in your application (in stm32u3xx.h file)" #endif diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u355xx.h b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u335xx.h similarity index 82% rename from system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u355xx.h rename to system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u335xx.h index e7f4b48608..93cb2c72ca 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u355xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u335xx.h @@ -1,8 +1,8 @@ /** ****************************************************************************** - * @file stm32u355xx.h + * @file stm32u335xx.h * @author MCD Application Team - * @brief CMSIS STM32U355xx Device Peripheral Access Layer Header File. + * @brief CMSIS STM32U335xx Device Peripheral Access Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals @@ -22,8 +22,8 @@ ****************************************************************************** */ -#ifndef STM32U355xx_H -#define STM32U355xx_H +#ifndef STM32U335xx_H +#define STM32U335xx_H #ifdef __cplusplus extern "C" { @@ -33,7 +33,7 @@ extern "C" { * @{ */ -/** @addtogroup STM32U355xx +/** @addtogroup STM32U335xx * @{ */ @@ -63,7 +63,7 @@ typedef enum PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ SysTick_IRQn = -1, /*!< -1 System Tick Timer */ - /* ================================== STM32U355xx Specific Interrupt Numbers ================================= */ + /* ================================== STM32U335xx Specific Interrupt Numbers ================================= */ WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ PVD_PVM_IRQn = 1, /*!< PVD and PVM through EXTI Line detection Interrupt */ RTC_IRQn = 2, /*!< RTC non-secure interrupt */ @@ -102,6 +102,8 @@ typedef enum GPDMA1_Channel7_IRQn = 36, /*!< GPDMA1 Channel 7 global interrupt */ ADC1_IRQn = 37, /*!< ADC1 global interrupt */ DAC1_IRQn = 38, /*!< DAC1 global interrupt */ + FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ TIM1_BRK_TERR_IERR_IRQn = 41, /*!< TIM1 Break, Transition error and Index error interrupt */ TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ TIM1_TRG_COM_DIR_IDX_IRQn = 43, /*!< TIM1 Trigger, Commutation, Direction change and Index interrupt */ @@ -120,7 +122,6 @@ typedef enum USART1_IRQn = 61, /*!< USART1 global interrupt */ USART3_IRQn = 63, /*!< USART3 global interrupt */ UART4_IRQn = 64, /*!< UART4 global interrupt */ - UART5_IRQn = 65, /*!< UART5 global interrupt */ LPUART1_IRQn = 66, /*!< LPUART1 global interrupt */ LPTIM1_IRQn = 67, /*!< LPTIM1 global interrupt */ LPTIM2_IRQn = 68, /*!< LPTIM2 global interrupt */ @@ -142,10 +143,9 @@ typedef enum FPU_IRQn = 95, /*!< FPU global interrupt */ HASH_IRQn = 96, /*!< HASH global interrupt */ LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */ - SPI3_IRQn = 99, /*!< SPI3 global interrupt */ ICACHE_IRQn = 107, /*!< Instruction cache global interrupt */ LPTIM4_IRQn = 110, /*!< LPTIM4 global interrupt */ - ADC2_IRQn = 113, /*!< ADC2 (12bits) global interrupt */ + ADF1_IRQn = 112, /*!< ADF1 interrupt */ PWR_IRQn = 123, /*!< PWR non-secure interrupt */ PWR_S_IRQn = 124 /*!< PWR secure interrupt */ } IRQn_Type; @@ -242,9 +242,9 @@ typedef struct __IO uint32_t AWD2HTR; /*!< ADC analog watchdog 2 high threshold register, Address offset: 0xB4 */ __IO uint32_t AWD3LTR; /*!< ADC analog watchdog 3 low threshold register, Address offset: 0xB8 */ __IO uint32_t AWD3HTR; /*!< ADC analog watchdog 3 high threshold register, Address offset: 0xBC */ - __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xC0 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0xC0 */ __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xC4 */ - uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0xC8 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0xC8 */ __IO uint32_t OR; /*!< ADC option register, Address offset: 0xD0 */ } ADC_TypeDef; @@ -330,16 +330,28 @@ typedef struct */ typedef struct { - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ - __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ - __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ - __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x18 - 0x1C */ - __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ - uint32_t RESERVED2; /*!< Reserved, 0x24 */ - __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1LFZR; /*!< Debug MCU APB1L freeze register, Address offset: 0x08 */ + __IO uint32_t APB1HFZR; /*!< Debug MCU APB1H freeze register, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x18 - 0x20 */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2[54]; /*!< Reserved, 0x24 - 0xFC */ + __IO uint32_t SR; /*!< Debug MCU status register, Address offset: 0xFC */ + __IO uint32_t DGB_AUTH_HOST; /*!< Debug MCU debug host authentication register, Address offset: 0x100 */ + __IO uint32_t DGB_AUTH_DEVICE; /*!< Debug MCU debug device authentication register, Address offset: 0x104 */ + uint32_t RESERVED3[946]; /*!< Reserved, 0x108 - 0xFD0 */ + __IO uint32_t PIDR4; /*!< Debug MCU CoreSight peripheral identity register 4, Address offset: 0xFD0 */ + __IO uint32_t PIDR0; /*!< Debug MCU CoreSight peripheral identity register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU CoreSight peripheral identity register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU CoreSight peripheral identity register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU CoreSight peripheral identity register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU CoreSight component identity register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU CoreSight component identity register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU CoreSight component identity register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU CoreSight component identity register 3, Address offset: 0xFFC */ } DBGMCU_TypeDef; /** @@ -402,6 +414,69 @@ typedef struct __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ } EXTI_TypeDef; +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128]; /*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58]; /*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; /** * @brief FLASH Registers @@ -759,10 +834,11 @@ typedef struct __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ uint32_t RESERVED4[2]; /*!< Reserved, Address offset: 0x78 -> 0x7C */ - uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x80 -> 0x84 */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ - uint32_t RESERVED6[8]; /*!< Reserved, Address offset: 0x90 -> 0xAC */ + uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x90 -> 0xAC */ __IO uint32_t I3CPUCR1; /*!< Power I3C pull-up control register 1, Address offset: 0xB0 */ __IO uint32_t I3CPUCR2; /*!< Power I3C pull-up control register 2, Address offset: 0xB4 */ } PWR_TypeDef; @@ -903,60 +979,6 @@ typedef struct __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ } RTC_TypeDef; -/** - * @brief Serial Audio Interface - */ -typedef struct -{ - uint32_t RESERVED[17]; /*!< Reserved, Address offset: 0x00 to 0x40 */ - __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ - __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ -} SAI_TypeDef; - -typedef struct -{ - __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ - __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ - __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ - __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ - __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ - __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ - __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ -} SAI_Block_TypeDef; - -/** - * @brief Secure digital input/output Interface - */ -typedef struct -{ - __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ - __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ - __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ - __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ - __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ - __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ - __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ - __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ - __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ - __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ - __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ - __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ - __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ - __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ - __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ - __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ - __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ - uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ - __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ - __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ - __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ - __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ - __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ - uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ -} SDMMC_TypeDef; /** * @brief SPI @@ -1166,14 +1188,6 @@ typedef struct __IO uint32_t RXBD; /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -14183,85 +14868,85 @@ typedef struct #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -14270,124 +14955,124 @@ typedef struct #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Pos (5UL) #define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_TAMPTSCR register ******************/ -#define RTC_TAMPTSCR_TAMP1TS_Pos (0U) +#define RTC_TAMPTSCR_TAMP1TS_Pos (0UL) #define RTC_TAMPTSCR_TAMP1TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP1TS_Pos) /*!< 0x00000001 */ #define RTC_TAMPTSCR_TAMP1TS RTC_TAMPTSCR_TAMP1TS_Msk -#define RTC_TAMPTSCR_TAMP2TS_Pos (1U) +#define RTC_TAMPTSCR_TAMP2TS_Pos (1UL) #define RTC_TAMPTSCR_TAMP2TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP2TS_Pos) /*!< 0x00000002 */ #define RTC_TAMPTSCR_TAMP2TS RTC_TAMPTSCR_TAMP2TS_Msk -#define RTC_TAMPTSCR_TAMP3TS_Pos (2U) +#define RTC_TAMPTSCR_TAMP3TS_Pos (2UL) #define RTC_TAMPTSCR_TAMP3TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP3TS_Pos) /*!< 0x00000004 */ #define RTC_TAMPTSCR_TAMP3TS RTC_TAMPTSCR_TAMP3TS_Msk -#define RTC_TAMPTSCR_TAMP4TS_Pos (3U) +#define RTC_TAMPTSCR_TAMP4TS_Pos (3UL) #define RTC_TAMPTSCR_TAMP4TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP4TS_Pos) /*!< 0x00000008 */ #define RTC_TAMPTSCR_TAMP4TS RTC_TAMPTSCR_TAMP4TS_Msk -#define RTC_TAMPTSCR_TAMP5TS_Pos (4U) +#define RTC_TAMPTSCR_TAMP5TS_Pos (4UL) #define RTC_TAMPTSCR_TAMP5TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP5TS_Pos) /*!< 0x00000010 */ #define RTC_TAMPTSCR_TAMP5TS RTC_TAMPTSCR_TAMP5TS_Msk -#define RTC_TAMPTSCR_ITAMPTS_Pos (16U) +#define RTC_TAMPTSCR_ITAMPTS_Pos (16UL) #define RTC_TAMPTSCR_ITAMPTS_Msk (0x1UL << RTC_TAMPTSCR_ITAMPTS_Pos) /*!< 0x00010000 */ #define RTC_TAMPTSCR_ITAMPTS RTC_TAMPTSCR_ITAMPTS_Msk /******************** Bits definition for RTC_TSIDR register ******************/ -#define RTC_TSIDR_TSID_Pos (0U) +#define RTC_TSIDR_TSID_Pos (0UL) #define RTC_TSIDR_TSID_Msk (0x3FUL << RTC_TSIDR_TSID_Pos) /*!< 0x0000003F */ #define RTC_TSIDR_TSID RTC_TSIDR_TSID_Msk #define RTC_TSIDR_TSID_0 (0x1UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000001 */ @@ -14398,802 +15083,59 @@ typedef struct #define RTC_TSIDR_TSID_5 (0x20UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000020 */ /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk -/******************************************************************************/ -/* */ -/* Serial Audio Interface */ -/* */ -/******************************************************************************/ -/******************* Bit definition for SAI_xCR1 register *******************/ -#define SAI_xCR1_MODE_Pos (0U) -#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ -#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p4 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32u3xx.h" /*!< STM32U3xx System */ + + +/* ================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================================================== */ +/** @addtogroup STM32U3xx_peripherals + * @{ + */ + +/** + * @brief ADC Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC channel preselection register, Address offset: 0x1C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + __IO uint32_t OFCFGR1; /*!< ADC offset configuration register 1, Address offset: 0x50 */ + __IO uint32_t OFCFGR2; /*!< ADC offset configuration register 2, Address offset: 0x54 */ + __IO uint32_t OFCFGR3; /*!< ADC offset configuration register 3, Address offset: 0x58 */ + __IO uint32_t OFCFGR4; /*!< ADC offset configuration register 4, Address offset: 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ + uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x90 */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + __IO uint32_t AWD1LTR; /*!< ADC analog watchdog 1 low threshold register, Address offset: 0xA8 */ + __IO uint32_t AWD1HTR; /*!< ADC analog watchdog 1 high threshold register, Address offset: 0xAC */ + __IO uint32_t AWD2LTR; /*!< ADC analog watchdog 2 low threshold register, Address offset: 0xB0 */ + __IO uint32_t AWD2HTR; /*!< ADC analog watchdog 2 high threshold register, Address offset: 0xB4 */ + __IO uint32_t AWD3LTR; /*!< ADC analog watchdog 3 low threshold register, Address offset: 0xB8 */ + __IO uint32_t AWD3HTR; /*!< ADC analog watchdog 3 high threshold register, Address offset: 0xBC */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xC4 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0xC8 */ + __IO uint32_t OR; /*!< ADC option register, Address offset: 0xD0 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for dual mode 32-bit, Address offset: 0x310 */ +} ADC_Common_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168]; /*!< Reserved, 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ +} AES_TypeDef; + + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control/status register , Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1LFZR; /*!< Debug MCU APB1L freeze register, Address offset: 0x08 */ + __IO uint32_t APB1HFZR; /*!< Debug MCU APB1H freeze register, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x18 - 0x20 */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2[54]; /*!< Reserved, 0x24 - 0xFC */ + __IO uint32_t SR; /*!< Debug MCU status register, Address offset: 0xFC */ + __IO uint32_t DGB_AUTH_HOST; /*!< Debug MCU debug host authentication register, Address offset: 0x100 */ + __IO uint32_t DGB_AUTH_DEVICE; /*!< Debug MCU debug device authentication register, Address offset: 0x104 */ + uint32_t RESERVED3[946]; /*!< Reserved, 0x108 - 0xFD0 */ + __IO uint32_t PIDR4; /*!< Debug MCU CoreSight peripheral identity register 4, Address offset: 0xFD0 */ + __IO uint32_t PIDR0; /*!< Debug MCU CoreSight peripheral identity register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU CoreSight peripheral identity register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU CoreSight peripheral identity register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU CoreSight peripheral identity register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU CoreSight component identity register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU CoreSight component identity register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU CoreSight component identity register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU CoreSight component identity register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @ brief Delay Block + */ +typedef struct +{ + __IO uint32_t CR; /*!< Delay Block Control Register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< Delay Block Configuration Register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128]; /*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58]; /*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t PDKEY1R; /*!< FLASH bank 1 power-down key register, Address offset: 0x18 */ + __IO uint32_t PDKEY2R; /*!< FLASH bank 2 power-down key register, Address offset: 0x1C */ + __IO uint32_t SR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t CR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCCR; /*!< FLASH ECC correction register, Address offset: 0x30 */ + __IO uint32_t ECCDR; /*!< FLASH ECC detection register, Address offset: 0x34 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x38 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t BOOT0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t BOOT1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SBOOT0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ + __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ + __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ + __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ + __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ + __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x70-0x7C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ + __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0x84 */ + __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0x88 */ + __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0x8C */ + uint32_t RESERVED5[4]; /*!< Reserved, Address offset: 0x90-0x9C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ + __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0xA4 */ + __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0xA8 */ + __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0xAC */ + uint32_t RESERVED6[4]; /*!< Reserved, Address offset: 0xB0-0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + __IO uint32_t SECHDPEXTR; /*!< FLASH HDP extension register, Address offset: 0xC8 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0xCC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ + __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xD4 */ + __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xD8 */ + __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xDC */ + uint32_t RESERVED8[4]; /*!< Reserved, Address offset: 0xE0-0xEC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ + __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0xF4 */ + __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0xF8 */ + __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0xFC */ + uint32_t RESERVED9[4]; /*!< Reserved, Address offset: 0x100-0x10C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x110 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x114 */ + __IO uint32_t OEM1KEYR3; /*!< FLASH OEM1 key register 3, Address offset: 0x118 */ + __IO uint32_t OEM1KEYR4; /*!< FLASH OEM1 key register 4, Address offset: 0x11C */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x120 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x124 */ + __IO uint32_t OEM2KEYR3; /*!< FLASH OEM2 key register 3, Address offset: 0x128 */ + __IO uint32_t OEM2KEYR4; /*!< FLASH OEM2 key register 4, Address offset: 0x12C */ + __IO uint32_t OEMKEYSR; /*!< FLASH OEM key status register, Address offset: 0x130 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[12]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x12C */ + uint32_t RESERVED3[52]; /*!< Reserved3, Address offset: 0x130-0x200 */ + __IO uint32_t PRIVCFGR[12]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x22C */ +} GTZC_MPCBB_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ +} GTZC_TZSC_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + __IO uint32_t SHA3CFGR; /*!< HASH SHA-3 configuration register, Address offset: 0x28 */ + uint32_t RESERVED[51]; /*!< Reserved, 0x2C-0xF4 */ + __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[50]; /*!< HASH digest registers, Address offset: 0x310-0x3D4 */ +} HASH_DIGEST_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; /*!< I2C Autonomous mode control register, Address offset: 0x2C */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + __IO uint32_t MISR; /*!< I3C Masked Interrupt Status register, Address offset: 0x5C */ + __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief MDF/ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED0[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t TRGISELR; /*!< MDF Trigger Input Selection Register, Address offset: 0x20 */ +} MDF_TypeDef; + +/** + * @brief MDF/ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x94-0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + uint32_t RESERVED1[1]; /*!< Reserved, 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED3[10]; /*!< Reserved, 0xC8-0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t BDCR; /*!< Power backup domain control register, Address offset: 0x24 */ + __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ + __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ + __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ + __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ + __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ + __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ + __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ + __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ + __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ + __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ + uint32_t RESERVED4[2]; /*!< Reserved, Address offset: 0x78 -> 0x7C */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ + __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ + __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ + uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x90 -> 0xAC */ + __IO uint32_t I3CPUCR1; /*!< Power I3C pull-up control register 1, Address offset: 0xB0 */ + __IO uint32_t I3CPUCR2; /*!< Power I3C pull-up control register 2, Address offset: 0xB4 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt status register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t PEAR; /*!< Parity error address register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt clear register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< Write protection register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< Write protection register 2, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t PARKEYR; /*!< Parity key register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< Erase key register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC Clock Control Register Address offset: 0x000 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x004 */ + __IO uint32_t ICSCR1; /*!< RCC Internal Clock Sources Calibration Register 1 Address offset: 0x008 */ + __IO uint32_t ICSCR2; /*!< RCC Internal Clock Sources Calibration Register 2 Address offset: 0x00C */ + __IO uint32_t ICSCR3; /*!< RCC Internal Clock Sources Calibration Register 3 Address offset: 0x010 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x014 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x018 */ + __IO uint32_t CFGR1; /*!< RCC Clock Configuration Register 1 Address offset: 0x01C */ + __IO uint32_t CFGR2; /*!< RCC Clock Configuration Register 2 Address offset: 0x020 */ + __IO uint32_t CFGR3; /*!< RCC Clock Configuration Register 3 Address offset: 0x024 */ + __IO uint32_t CFGR4; /*!< RCC Clock Configuration Register 4 Address offset: 0x028 */ + uint32_t RESERVED2[9]; /*!< Reserved Address offset: 0x02C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x050 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x054 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x058 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x05C */ + __IO uint32_t AHB1RSTR1; /*!< AHB1 Peripherals Reset Register 1 Address offset: 0x060 */ + __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x064 */ + __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x068 */ + uint32_t RESERVED4[2]; /*!< Reserved Address offset: 0x06C */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x074 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x078 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x07C */ + __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x080 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x084 */ + __IO uint32_t AHB1ENR1; /*!< AHB1 Peripherals Clock Enable Register 1 Address offset: 0x088 */ + __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x08C */ + __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x090 */ + __IO uint32_t AHB1ENR2; /*!< AHB1 Peripherals Clock Enable Register 2 Address offset: 0x094 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x098 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x09C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0x0A0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0x0A4 */ + __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0x0A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x0AC */ + __IO uint32_t AHB1SLPENR1; /*!< AHB1 Peripherals Clock Enable in Sleep Mode Register 1 Address offset: 0x0B0 */ + __IO uint32_t AHB2SLPENR1; /*!< AHB2 Peripherals Clock Enable in Sleep Mode Register 1 Address offset: 0x0B4 */ + __IO uint32_t AHB2SLPENR2; /*!< AHB2 Peripherals Clock Enable in Sleep Mode Register 2 Address offset: 0x0B8 */ + __IO uint32_t AHB1SLPENR2; /*!< AHB1 Peripherals Clock Enable in Sleep Mode Register 2 Address offset: 0x0BC */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x0C0 */ + __IO uint32_t APB1SLPENR1; /*!< APB1 Peripherals Clock Enable in Sleep Mode Register 1 Address offset: 0x0C4 */ + __IO uint32_t APB1SLPENR2; /*!< APB1 Peripherals Clock Enable in Sleep Mode Register 2 Address offset: 0x0C8 */ + __IO uint32_t APB2SLPENR; /*!< APB2 Peripherals Clock Enable in Sleep Mode Register Address offset: 0x0CC */ + __IO uint32_t APB3SLPENR; /*!< APB3 Peripherals Clock Enable in Sleep Mode Register Address offset: 0x0D0 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0x0D4 */ + __IO uint32_t AHB1STPENR1; /*!< AHB1 Peripherals Clock Enable in Stop Mode Register 1 Address offset: 0x0D8 */ + __IO uint32_t AHB2STPENR1; /*!< AHB2 Peripherals Clock Enable in Stop Mode Register 1 Address offset: 0x0DC */ + uint32_t RESERVED10[3]; /*!< Reserved Address offset: 0x0E0 */ + __IO uint32_t APB1STPENR1; /*!< APB1 Peripherals Clock Enable in Stop Mode Register 1 Address offset: 0x0EC */ + __IO uint32_t APB1STPENR2; /*!< APB1 Peripherals Clock Enable in Stop Mode Register 2 Address offset: 0x0F0 */ + __IO uint32_t APB2STPENR; /*!< APB2 Peripherals Clock Enable in Stop Mode Register Address offset: 0x0F4 */ + __IO uint32_t APB3STPENR; /*!< APB3 Peripherals Clock Enable in Stop Mode Register Address offset: 0x0F8 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0FC */ + __IO uint32_t CCIPR1; /*!< Peripherals Independent Clocks Configuration Register 1 Address offset: 0x100 */ + __IO uint32_t CCIPR2; /*!< Peripherals Independent Clocks Configuration Register 2 Address offset: 0x104 */ + __IO uint32_t CCIPR3; /*!< Peripherals Independent Clocks Configuration Register 3 Address offset: 0x108 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x10C */ + __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0x110 */ + __IO uint32_t CSR; /*!< Control & Status Register Address offset: 0x114 */ + uint32_t RESERVED13[6]; /*!< Reserved Address offset: 0x118 */ + __IO uint32_t SECCFGR; /*!< RCC Secure Configuration Register Address offset: 0x130 */ + __IO uint32_t PRIVCFGR; /*!< RCC Privilege Configuration Register Address offset: 0x134 */ +} RCC_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x60 */ + __IO uint32_t TAMPTSCR; /*!< RTC timestamp on tamper control register, Address offset: 0x64 */ + __IO uint32_t TSIDR; /*!< RTC timestamp status register, Address offset: 0x68 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED2; /*!< RESERVED2, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ +} SYSCFG_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + uint32_t RESERVED1[4]; /*!< Reserved, 0x10 -- 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x44 -- 0x50 */ + __IO uint32_t RPCFGR; /*!< TAMP resources protection configuration register, Address offset: 0x54 */ + uint32_t RESERVED3[42]; /*!< Reserved, 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Touch Sensing Controller (TSC) + */ +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, 0x34-0x4C */ +} TSC_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220]; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + __IO uint32_t RESERVED0[8]; /*!< Reserved, */ + __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IO uint32_t TXBD; /*!= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* ================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* ================================================================================================================== */ +/** @addtogroup STM32U3xx_Peripheral_peripheralAddr + * @{ + */ + +/*!< Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS 0x08000000UL /*!< FLASH non-secure base address */ +#define SYSTEM_FLASH_BASE_NS 0x0BF80000UL /*!< System FLASH non-secure base address */ +#define SRAM1_BASE_NS 0x20000000UL /*!< SRAM1 non-secure base address */ +#define SRAM2_BASE_NS 0x20040000UL /*!< SRAM2 non-secure base address */ + +#define PERIPH_BASE_NS 0x40000000UL /*!< Peripheral non-secure base address */ +#define EXTRAM_BASE_NS 0x90000000UL /*!< External RAM base address */ +#define EPPB_BASE 0xE0040000UL /*!< External Private Peripheral Bus */ + +/*!< OTP, Engineering bytes, Option bytes defines */ +#define FLASH_OTP_BASE (SYSTEM_FLASH_BASE_NS + 0x00020000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE 0x00000200U /*!< 512 bytes OTP (one-time programmable) */ +#define FLASH_ENGY_BASE (SYSTEM_FLASH_BASE_NS + 0x00020500UL) +#define PACKAGE_BASE (FLASH_ENGY_BASE) /*!< Package data register base address */ +#define UID_BASE (FLASH_ENGY_BASE + 0x00000200UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (FLASH_ENGY_BASE + 0x000002A0UL) /*!< Flash size data register base address */ +#define UID64_BASE (FLASH_ENGY_BASE + 0x00000500UL) /*!< 64-bit Unique device Identification */ + +/*!< Memory sizes */ +/* Internal Flash size */ +#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? 0x40000U : \ + ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? 0x40000U : \ + (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U))) + +/*!< Internal SRAMs size */ +#define SRAM1_SIZE 0x00004000UL /*!< SRAM1=16k */ +#define SRAM2_SIZE 0x00010000UL /*!< SRAM2=64k */ + +/*!< Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00040000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x00000000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x00000400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x00000800UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x00001000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x00001400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x00002C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x00003000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x00003800UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x00004800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x00004C00UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x00005400UL) +#define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x00005C00UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x00006000UL) +#define OPAMP1_BASE_NS (APB1PERIPH_BASE_NS + 0x00007000UL) +#define OPAMP2_BASE_NS (OPAMP1_BASE_NS + 0x0000010UL) +#define RTC_BASE_NS (APB1PERIPH_BASE_NS + 0x00007800UL) +#define TAMP_BASE_NS (APB1PERIPH_BASE_NS + 0x00007C00UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x00009400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0x0000A400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0x0000A500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0x0000AC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x00002C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x00003000UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x00003800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x00004000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x00004400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x00004800UL) +#define USB_DRD_BASE_NS (APB2PERIPH_BASE_NS + 0x00006000UL) +#define USB_DRD_PMAADDR_NS (APB2PERIPH_BASE_NS + 0x00006400UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x00000050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x000000D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x00000150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x000001D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x00000250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x000002D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x00000350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x000003D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x00000450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x000004D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x00000550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x000005D0UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x00002000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x00003000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x00004000UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x00006000UL) +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x00000040UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x00010400UL) +#define PWR_BASE_NS (AHB1PERIPH_BASE_NS + 0x00010800UL) +#define RCC_BASE_NS (AHB1PERIPH_BASE_NS + 0x00010C00UL) +#define EXTI_BASE_NS (AHB1PERIPH_BASE_NS + 0x00012000UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x00012400UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x00012C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x00013000UL) +#define ADF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x00014000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x00000080UL) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x00000400UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x00002400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x00002800UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x00004400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x00004800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x00004C00UL) +#define COMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x00005400UL) +#define COMP2_BASE_NS (COMP1_BASE_NS + 0x00000004UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000C00UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x00001C00UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008000UL) +#define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008400UL) +#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0800UL) +#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0x000AF000UL) +#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0x000B1400UL) + +#if defined(CPU_IN_SECURE_STATE) +/*!< Flash, Peripheral and internal SRAMs base addresses - secure */ +#define FLASH_BASE_S 0x0C000000UL /*!< FLASH secure base address */ +#define SYSTEM_FLASH_BASE_S 0x0FF80000UL /*!< System FLASH secure base address */ +#define SRAM1_BASE_S 0x30000000UL /*!< SRAM1 secure base address */ +#define SRAM2_BASE_S 0x30030000UL /*!< SRAM2 secure base address */ +#define PERIPH_BASE_S 0x50000000UL /*!< Peripheral secure base address */ + +/*!< Peripheral memory map - secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x00040000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) + +/*!< APB1 secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x00000000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x00000400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x00000800UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x00001000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x00001400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x00002C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x00003000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x00003800UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x00004800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x00004C00UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x00005400UL) +#define I3C1_BASE_S (APB1PERIPH_BASE_S + 0x00005C00UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x00006000UL) +#define OPAMP1_BASE_S (APB1PERIPH_BASE_S + 0x00007000UL) +#define OPAMP2_BASE_S (OPAMP1_BASE_S + 0x0000010UL) +#define RTC_BASE_S (APB1PERIPH_BASE_S + 0x00007800UL) +#define TAMP_BASE_S (APB1PERIPH_BASE_S + 0x00007C00UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x00009400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0x0000A400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0x0000A500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0x0000AC00UL) + +/*!< APB2 secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x00002C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x00003000UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x00003800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x00004000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x00004400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x00004800UL) +#define USB_DRD_BASE_S (APB2PERIPH_BASE_S + 0x00006000UL) +#define USB_DRD_PMAADDR_S (APB2PERIPH_BASE_S + 0x00006400UL) + +/*!< AHB1 secure peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x00000050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x000000D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x00000150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x000001D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x00000250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x000002D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x00000350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x000003D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x00000450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x000004D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x00000550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x000005D0UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x00002000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x00003000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x00004000UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x00006000UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x00000040UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x00010400UL) +#define PWR_BASE_S (AHB1PERIPH_BASE_S + 0x00010800UL) +#define RCC_BASE_S (AHB1PERIPH_BASE_S + 0x00010C00UL) +#define EXTI_BASE_S (AHB1PERIPH_BASE_S + 0x00012000UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x00012400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x00012800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x00012C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x00013000UL) +#define ADF1_BASE_S (AHB1PERIPH_BASE_S + 0x00014000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x00000080UL) + +/*!< APB3 secure peripherals */ +#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x00000400UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x00002400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x00002800UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x00004400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x00004800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x00004C00UL) +#define COMP1_BASE_S (APB3PERIPH_BASE_S + 0x00005400UL) +#define COMP2_BASE_S (COMP1_BASE_S + 0x00000004UL) + +/*!< AHB2 secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00000400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00000800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00000C00UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x00001C00UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x00008000UL) +#define DAC1_BASE_S (AHB2PERIPH_BASE_S + 0x00008400UL) +#define AES_BASE_S (AHB2PERIPH_BASE_S + 0x000A0000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0x000A0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0x000A0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0x000A0800UL) +#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0x000AF000UL) +#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0x000B1400UL) +#endif /* CPU_IN_SECURE_STATE */ + +/*!< External memories base addresses - Not aliased */ +#define OCTOSPI1_BASE EXTRAM_BASE_NS + +/*!< DBGMCU base addresses - Not aliased */ +#define DBGMCU_BASE (EPPB_BASE + 0x00004000UL) + +/*!< USB PMA SIZE */ +#define USB_DRD_PMA_SIZE (2048U) /*!< USB PMA Size 2Kbyte */ + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START 0x0BF99040UL +#define RSSLIB_SYS_FLASH_NS_PFUNC_END 0x0BF990FFUL + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR 0xF5F5F5F5UL +#define RSSLIB_SUCCESS 0xEAEAEAEAUL + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos 0UL +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos 0UL +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos 1UL +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) +#define RSSLIB_HDPEXT_CLOSE_BOUNDARY_OPEN 0xC9C9C9C9UL /* Access to HDPx extension area and HDPx area denied but HDPx_EXT (in FLASH_HDPEXTR) increment allowed at any time */ +#define RSSLIB_HDPEXT_CLOSE_BOUNDARY_LOCK 0xD6D6D6D6UL /* Access to HDPx extension area and HDPx area denied. Update of HDPx_EXT size is not possible anymore */ + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param VectorTableAddr pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + +/** + * @brief Prototype of RSSLIB Close and exit HDP extension Function + * @detail This function close the requested hdp extension area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpExtArea notifies which hdp extension area to close, can be a combination of + * hdp extension area 1 and hdp extension area 2 + * @param VectorTableAddr pointer on the vector table containing the reset handler the function + * jumps to. + * @param CloseBound notifies if the HDP extension area should be closed with + * HDPx_EXT increment allowed or not + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDPExt_TypeDef)( uint32_t HdpExtArea, uint32_t VectorTableAddr, uint32_t CloseBound ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ + __IM RSSLIB_S_CloseExitHDPExt_TypeDef CloseExitHDPExt; /*!< RSSLIB Bootloader Close and exit HDP extension Address offset: 0x2C */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/* + * Certificate address description + */ +#define CERT_CHIP_PACK1_ADDR (0x0BF9FE00U) +#define CERT_CHIP_PACK1_SIZE (0x200U) +#define CERT_CHIP_PACK2_ADDR (0x0BF9FC00U) +#define CERT_CHIP_PACK2_SIZE (0x200U) + +#define CERT_CHIP_PACK_ADDR (CERT_CHIP_PACK2_ADDR) +#define CERT_CHIP_PACK_SIZE (CERT_CHIP_PACK1_SIZE + CERT_CHIP_PACK2_SIZE) + +#define CERT_ST_DUA_USER_FU_PUB_KEY_OFFSET (12U) +#define CERT_ST_DUA_USER_FU_PUB_KEY_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_FU_PUB_KEY_OFFSET) +#define CERT_ST_DUA_USER_FU_SIGN_OFFSET (76U) +#define CERT_ST_DUA_USER_FU_SIGN_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_FU_SIGN_OFFSET) +#define CERT_ST_DUA_USER_FU_SERIAL_OFFSET (140U) +#define CERT_ST_DUA_USER_FU_SERIAL_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_FU_SERIAL_OFFSET) + +#define CERT_ST_DUA_USER_LU_PUB_KEY_OFFSET (162U) +#define CERT_ST_DUA_USER_LU_PUB_KEY_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_LU_PUB_KEY_OFFSET) +#define CERT_ST_DUA_USER_LU_SIGN_OFFSET (226U) +#define CERT_ST_DUA_USER_LU_SIGN_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_LU_SIGN_OFFSET) +#define CERT_ST_DUA_USER_LU_SERIAL_OFFSET (290U) +#define CERT_ST_DUA_USER_LU_SERIAL_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_LU_SERIAL_OFFSET) +/** @} */ /* End of group STM32U3xx_Peripheral_peripheralAddr */ + + +/* ================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================================================== */ +/** @addtogroup STM32U3xx_Peripheral_declaration + * @{ + */ +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) +#define AES_NS ((AES_TypeDef *) AES_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define I3C1_NS ((I3C_TypeDef *) I3C1_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) +#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define USB_DRD_FS_NS ((USB_DRD_TypeDef *) USB_DRD_BASE_NS) +#define USB_DRD_PMA_BUFF_NS ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) + +/*!< DBGMCU peripheral */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#if defined (CPU_IN_SECURE_STATE) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) +#define AES_S ((AES_TypeDef *) AES_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define I3C1_S ((I3C_TypeDef *) I3C1_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) +#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define USB_DRD_FS_S ((USB_DRD_TypeDef *) USB_DRD_BASE_S) +#define USB_DRD_PMA_BUFF_S ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S +#define AES AES_S +#define AES_BASE AES_BASE_S +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S +#define COMP2 COMP2_S +#define COMP2_BASE COMP2_BASE_S +#define COMP12_COMMON COMP12_COMMON_S +#define COMP12_COMMON_BASE COMP12_BASE_S +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S +#define I3C1 I3C1_S +#define I3C1_BASE I3C1_BASE_S +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S +#define OPAMP1 OPAMP1_S +#define OPAMP1_BASE OPAMP1_BASE_S +#define OPAMP2 OPAMP2_S +#define OPAMP2_BASE OPAMP2_BASE_S +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S +#define USB_DRD_FS USB_DRD_FS_S +#define USB_DRD_BASE USB_DRD_BASE_S +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_S +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_S +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#else /* CPU_IN_SECURE_STATE */ +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS +#define AES AES_NS +#define AES_BASE AES_BASE_NS +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS +#define COMP12_COMMON COMP12_COMMON_NS +#define COMP12_COMMON_BASE COMP12_BASE_NS +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS +#define I3C1 I3C1_NS +#define I3C1_BASE I3C1_BASE_NS +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS +#define OPAMP1 OPAMP1_NS +#define OPAMP1_BASE OPAMP1_BASE_NS +#define OPAMP2 OPAMP2_NS +#define OPAMP2_BASE OPAMP2_BASE_NS +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS +#define USB_DRD_FS USB_DRD_FS_NS +#define USB_DRD_BASE USB_DRD_BASE_NS +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_NS +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_NS +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS +#endif /* CPU_IN_SECURE_STATE */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 16000U /*!< LSI Maximum startup time in us : 4 cycles @ 250 Hz = 16 ms */ +/** + * @} + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ + +/* Specific device feature definitions */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0UL) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1UL) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2UL) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3UL) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4UL) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5UL) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6UL) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7UL) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8UL) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9UL) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10UL) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ +#define ADC_ISR_LDORDY_Pos (12UL) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC internal voltage regulator output ready flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0UL) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1UL) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2UL) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3UL) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4UL) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5UL) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6UL) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7UL) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8UL) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9UL) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10UL) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ +#define ADC_IER_LDORDYIE_Pos (12UL) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC internal voltage regulator interrupt*/ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0UL) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1UL) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2UL) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3UL) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4UL) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5UL) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28UL) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC internal voltage regulator */ +#define ADC_CR_DEEPPWD_Pos (29UL) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCAL_Pos (31UL) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register ******************/ +#define ADC_CFGR1_DMNGT_Pos (0UL) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC data management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2UL) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC_CFGR1_EXTSEL_Pos (5UL) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10UL) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12UL) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13UL) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_AUTDLY_Pos (14UL) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC low power auto wait */ + +#define ADC_CFGR1_DISCEN_Pos (16UL) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR1_DISCNUM_Pos (17UL) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20UL) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ + +#define ADC_CFGR1_JQM_Pos (21UL) +#define ADC_CFGR1_JQM_Msk (0x1UL << ADC_CFGR1_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_JQM ADC_CFGR1_JQM_Msk /*!< ADC group injected contexts queue mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22UL) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23UL) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR1_JAWD1EN_Pos (24UL) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR1_JAUTO_Pos (25UL) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26UL) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR1_JQDIS_Pos (31UL) +#define ADC_CFGR1_JQDIS_Msk (0x1UL << ADC_CFGR1_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR1_JQDIS ADC_CFGR1_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0UL) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1UL) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSS_Pos (5UL) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9UL) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10UL) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_BULB_Pos (13UL) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14UL) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15UL) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC sampling time control trigger mode */ + +#define ADC_CFGR2_OVSR_Pos (16UL) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_LFTRIG_Pos (27UL) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low-frequency trigge */ + +#define ADC_CFGR2_LSHIFT_Pos (28UL) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0UL) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3UL) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6UL) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9UL) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12UL) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15UL) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18UL) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21UL) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24UL) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27UL) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0UL) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3UL) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6UL) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9UL) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12UL) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15UL) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18UL) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21UL) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24UL) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27UL) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register *****************/ +#define ADC_PCSEL_PCSEL_Pos (0UL) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC channel preselection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0UL) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6UL) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12UL) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18UL) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24UL) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0UL) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6UL) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12UL) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18UL) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24UL) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0UL) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6UL) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12UL) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18UL) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24UL) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0UL) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6UL) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0UL) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_RDATA_0 (0x00000001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x00000002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x00000004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x00000008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x00000010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x00000020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x00000040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x00000080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x00000100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x00000200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x00000400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x00000800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x00001000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x00002000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x00004000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x00008000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_16 (0x00010000UL << ADC_DR_RDATA_Pos) /*!< 0x00010000 */ +#define ADC_DR_RDATA_17 (0x00020000UL << ADC_DR_RDATA_Pos) /*!< 0x00020000 */ +#define ADC_DR_RDATA_18 (0x00040000UL << ADC_DR_RDATA_Pos) /*!< 0x00040000 */ +#define ADC_DR_RDATA_19 (0x00080000UL << ADC_DR_RDATA_Pos) /*!< 0x00080000 */ +#define ADC_DR_RDATA_20 (0x00100000UL << ADC_DR_RDATA_Pos) /*!< 0x00100000 */ +#define ADC_DR_RDATA_21 (0x00200000UL << ADC_DR_RDATA_Pos) /*!< 0x00200000 */ +#define ADC_DR_RDATA_22 (0x00400000UL << ADC_DR_RDATA_Pos) /*!< 0x00400000 */ +#define ADC_DR_RDATA_23 (0x00800000UL << ADC_DR_RDATA_Pos) /*!< 0x00800000 */ +#define ADC_DR_RDATA_24 (0x01000000UL << ADC_DR_RDATA_Pos) /*!< 0x01000000 */ +#define ADC_DR_RDATA_25 (0x02000000UL << ADC_DR_RDATA_Pos) /*!< 0x02000000 */ +#define ADC_DR_RDATA_26 (0x04000000UL << ADC_DR_RDATA_Pos) /*!< 0x04000000 */ +#define ADC_DR_RDATA_27 (0x08000000UL << ADC_DR_RDATA_Pos) /*!< 0x08000000 */ +#define ADC_DR_RDATA_28 (0x10000000UL << ADC_DR_RDATA_Pos) /*!< 0x10000000 */ +#define ADC_DR_RDATA_29 (0x20000000UL << ADC_DR_RDATA_Pos) /*!< 0x20000000 */ +#define ADC_DR_RDATA_30 (0x40000000UL << ADC_DR_RDATA_Pos) /*!< 0x40000000 */ +#define ADC_DR_RDATA_31 (0x80000000UL << ADC_DR_RDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0UL) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2UL) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7UL) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9UL) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15UL) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21UL) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27UL) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR1 register ***************/ +#define ADC_OFCFGR1_POSOFF_Pos (24UL) +#define ADC_OFCFGR1_POSOFF_Msk (0x01UL << ADC_OFCFGR1_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR1_POSOFF ADC_OFCFGR1_POSOFF_Msk /*!< ADC offset instance 1 positive offset enable */ + +#define ADC_OFCFGR1_USAT_Pos (25UL) +#define ADC_OFCFGR1_USAT_Msk (0x01UL << ADC_OFCFGR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR1_USAT ADC_OFCFGR1_USAT_Msk /*!< ADC offset instance 1 unsigned saturation value */ + +#define ADC_OFCFGR1_SSAT_Pos (26UL) +#define ADC_OFCFGR1_SSAT_Msk (0x01UL << ADC_OFCFGR1_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR1_SSAT ADC_OFCFGR1_SSAT_Msk /*!< ADC offset instance 1 signed satuaration enable */ + +#define ADC_OFCFGR1_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR1_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR1_OFFSET_CH ADC_OFCFGR1_OFFSET_CH_Msk /*!< ADC offset instance 1 channel selection */ +#define ADC_OFCFGR1_OFFSET_CH_0 (0x01UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR1_OFFSET_CH_1 (0x02UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR1_OFFSET_CH_2 (0x03UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR1_OFFSET_CH_3 (0x04UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR1_OFFSET_CH_4 (0x05UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR2 register ***************/ +#define ADC_OFCFGR2_POSOFF_Pos (24UL) +#define ADC_OFCFGR2_POSOFF_Msk (0x01UL << ADC_OFCFGR2_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR2_POSOFF ADC_OFCFGR2_POSOFF_Msk /*!< ADC offset instance 2 positive offset enable */ + +#define ADC_OFCFGR2_USAT_Pos (25UL) +#define ADC_OFCFGR2_USAT_Msk (0x01UL << ADC_OFCFGR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR2_USAT ADC_OFCFGR2_USAT_Msk /*!< ADC offset instance 2 unsigned saturation value */ + +#define ADC_OFCFGR2_SSAT_Pos (26UL) +#define ADC_OFCFGR2_SSAT_Msk (0x01UL << ADC_OFCFGR2_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR2_SSAT ADC_OFCFGR2_SSAT_Msk /*!< ADC offset instance 2 signed satuaration enable */ + +#define ADC_OFCFGR2_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR2_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR2_OFFSET_CH ADC_OFCFGR2_OFFSET_CH_Msk /*!< ADC offset instance 2 channel selection */ +#define ADC_OFCFGR2_OFFSET_CH_0 (0x01UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR2_OFFSET_CH_1 (0x02UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR2_OFFSET_CH_2 (0x03UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR2_OFFSET_CH_3 (0x04UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR2_OFFSET_CH_4 (0x05UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR3 register ***************/ +#define ADC_OFCFGR3_POSOFF_Pos (24UL) +#define ADC_OFCFGR3_POSOFF_Msk (0x01UL << ADC_OFCFGR3_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR3_POSOFF ADC_OFCFGR3_POSOFF_Msk /*!< ADC offset instance 3 positive offset enable */ + +#define ADC_OFCFGR3_USAT_Pos (25UL) +#define ADC_OFCFGR3_USAT_Msk (0x01UL << ADC_OFCFGR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR3_USAT ADC_OFCFGR3_USAT_Msk /*!< ADC offset instance 3 unsigned saturation value */ + +#define ADC_OFCFGR3_SSAT_Pos (26UL) +#define ADC_OFCFGR3_SSAT_Msk (0x01UL << ADC_OFCFGR3_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR3_SSAT ADC_OFCFGR3_SSAT_Msk /*!< ADC offset instance 3 signed satuaration enable */ + +#define ADC_OFCFGR3_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR3_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR3_OFFSET_CH ADC_OFCFGR3_OFFSET_CH_Msk /*!< ADC offset instance 3 channel selection for the data offset */ +#define ADC_OFCFGR3_OFFSET_CH_0 (0x01UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR3_OFFSET_CH_1 (0x02UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR3_OFFSET_CH_2 (0x03UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR3_OFFSET_CH_3 (0x04UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR3_OFFSET_CH_4 (0x05UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR4 register ***************/ +#define ADC_OFCFGR4_POSOFF_Pos (24UL) +#define ADC_OFCFGR4_POSOFF_Msk (0x01UL << ADC_OFCFGR4_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR4_POSOFF ADC_OFCFGR4_POSOFF_Msk /*!< ADC offset instance 4 positive offset enable */ + +#define ADC_OFCFGR4_USAT_Pos (25UL) +#define ADC_OFCFGR4_USAT_Msk (0x01UL << ADC_OFCFGR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR4_USAT ADC_OFCFGR4_USAT_Msk /*!< ADC offset instance 4 unsigned saturation value */ + +#define ADC_OFCFGR4_SSAT_Pos (26UL) +#define ADC_OFCFGR4_SSAT_Msk (0x01UL << ADC_OFCFGR4_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR4_SSAT ADC_OFCFGR4_SSAT_Msk /*!< ADC offset instance 4 signed satuaration enable */ + +#define ADC_OFCFGR4_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR4_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR4_OFFSET_CH ADC_OFCFGR4_OFFSET_CH_Msk /*!< ADC offset instance 4 channel selection for the data offset */ +#define ADC_OFCFGR4_OFFSET_CH_0 (0x01UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR4_OFFSET_CH_1 (0x02UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR4_OFFSET_CH_2 (0x03UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR4_OFFSET_CH_3 (0x04UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR4_OFFSET_CH_4 (0x05UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET_Pos (0UL) +#define ADC_OFR1_OFFSET_Msk (0x03FFFFFUL << ADC_OFR1_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR1_OFFSET ADC_OFR1_OFFSET_Msk /*!< ADC offset instance 1 offset level */ +#define ADC_OFR1_OFFSET_0 (0x0000001UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET_1 (0x0000002UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET_2 (0x0000004UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET_3 (0x0000008UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET_4 (0x0000010UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET_5 (0x0000020UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET_6 (0x0000040UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET_7 (0x0000080UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET_8 (0x0000100UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET_9 (0x0000200UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET_10 (0x0000400UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET_11 (0x0000800UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET_12 (0x0001000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET_13 (0x0002000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET_14 (0x0004000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET_15 (0x0008000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET_16 (0x0010000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET_17 (0x0020000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET_18 (0x0040000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET_19 (0x0080000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET_20 (0x0100000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET_21 (0x0200000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET_Pos (0UL) +#define ADC_OFR2_OFFSET_Msk (0x03FFFFFUL << ADC_OFR2_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR2_OFFSET ADC_OFR2_OFFSET_Msk /*!< ADC offset instance 2 offset level */ +#define ADC_OFR2_OFFSET_0 (0x0000001UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET_1 (0x0000002UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET_2 (0x0000004UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET_3 (0x0000008UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET_4 (0x0000010UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET_5 (0x0000020UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET_6 (0x0000040UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET_7 (0x0000080UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET_8 (0x0000100UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET_9 (0x0000200UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET_10 (0x0000400UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET_11 (0x0000800UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET_12 (0x0001000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET_13 (0x0002000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET_14 (0x0004000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET_15 (0x0008000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET_16 (0x0010000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET_17 (0x0020000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET_18 (0x0040000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET_19 (0x0080000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET_20 (0x0100000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET_21 (0x0200000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET_Pos (0UL) +#define ADC_OFR3_OFFSET_Msk (0x03FFFFFUL << ADC_OFR3_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR3_OFFSET ADC_OFR3_OFFSET_Msk /*!< ADC offset instance 3 offset level */ +#define ADC_OFR3_OFFSET_0 (0x0000001UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET_1 (0x0000002UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET_2 (0x0000004UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET_3 (0x0000008UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET_4 (0x0000010UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET_5 (0x0000020UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET_6 (0x0000040UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET_7 (0x0000080UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET_8 (0x0000100UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET_9 (0x0000200UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET_10 (0x0000400UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET_11 (0x0000800UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET_12 (0x0001000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET_13 (0x0002000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET_14 (0x0004000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET_15 (0x0008000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET_16 (0x0010000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET_17 (0x0020000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET_18 (0x0040000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET_19 (0x0080000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET_20 (0x0100000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET_21 (0x0200000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET_Pos (0UL) +#define ADC_OFR4_OFFSET_Msk (0x03FFFFFUL << ADC_OFR4_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR4_OFFSET ADC_OFR4_OFFSET_Msk /*!< ADC offset instance 4 offset level */ +#define ADC_OFR4_OFFSET_0 (0x0000001UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET_1 (0x0000002UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET_2 (0x0000004UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET_3 (0x0000008UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET_4 (0x0000010UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET_5 (0x0000020UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET_6 (0x0000040UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET_7 (0x0000080UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET_8 (0x0000100UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET_9 (0x0000200UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET_10 (0x0000400UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET_11 (0x0000800UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET_12 (0x0001000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET_13 (0x0002000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET_14 (0x0004000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET_15 (0x0008000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET_16 (0x0010000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET_17 (0x0020000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET_18 (0x0040000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET_19 (0x0080000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET_20 (0x0100000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET_21 (0x0200000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_GCOMP register *****************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< Gain compensation coefficient */ +#define ADC_GCOMP_GCOMPCOEFF_0 (0x0001UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000001 */ +#define ADC_GCOMP_GCOMPCOEFF_1 (0x0002UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000002 */ +#define ADC_GCOMP_GCOMPCOEFF_2 (0x0004UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000004 */ +#define ADC_GCOMP_GCOMPCOEFF_3 (0x0008UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000008 */ +#define ADC_GCOMP_GCOMPCOEFF_4 (0x0010UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000010 */ +#define ADC_GCOMP_GCOMPCOEFF_5 (0x0020UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000020 */ +#define ADC_GCOMP_GCOMPCOEFF_6 (0x0040UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000040 */ +#define ADC_GCOMP_GCOMPCOEFF_7 (0x0080UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000080 */ +#define ADC_GCOMP_GCOMPCOEFF_8 (0x0100UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000100 */ +#define ADC_GCOMP_GCOMPCOEFF_9 (0x0200UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000200 */ +#define ADC_GCOMP_GCOMPCOEFF_10 (0x0400UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000400 */ +#define ADC_GCOMP_GCOMPCOEFF_11 (0x0800UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000800 */ +#define ADC_GCOMP_GCOMPCOEFF_12 (0x1000UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00001000 */ +#define ADC_GCOMP_GCOMPCOEFF_13 (0x2000UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00002000 */ + +#define ADC_GCOMP_GCOMP_Pos (31UL) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x80000000 */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< Gain compensation mode */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0UL) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0UL) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0UL) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0UL) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0UL) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0UL) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD1TR_LT register *************/ +#define ADC_AWD1LTR_LTR_Pos (0UL) +#define ADC_AWD1LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD1LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1LTR_LTR ADC_AWD1LTR_LTR_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1LTR_LTR_0 (0x000001UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1LTR_LTR_1 (0x000002UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1LTR_LTR_2 (0x000004UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1LTR_LTR_3 (0x000008UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1LTR_LTR_4 (0x000010UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1LTR_LTR_5 (0x000020UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1LTR_LTR_6 (0x000040UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1LTR_LTR_7 (0x000080UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1LTR_LTR_8 (0x000100UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1LTR_LTR_9 (0x000200UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1LTR_LTR_10 (0x000400UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1LTR_LTR_11 (0x000800UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1LTR_LTR_12 (0x001000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1LTR_LTR_13 (0x002000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1LTR_LTR_14 (0x004000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1LTR_LTR_15 (0x008000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1LTR_LTR_16 (0x010000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1LTR_LTR_17 (0x020000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1LTR_LTR_18 (0x040000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1LTR_LTR_19 (0x080000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1LTR_LTR_20 (0x100000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1LTR_LTR_21 (0x200000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1LTR_LTR_22 (0x400000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD1TR_HT register *******************/ +#define ADC_AWD1HTR_HTR_Pos (0UL) +#define ADC_AWD1HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD1HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1HTR_HTR ADC_AWD1HTR_HTR_Msk /*!< ADC analog watchdog 1 threshold high */ +#define ADC_AWD1HTR_HTR_0 (0x000001UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_HTR_1 (0x000002UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_HTR_2 (0x000004UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1HTR_HTR_3 (0x000008UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1HTR_HTR_4 (0x000010UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1HTR_HTR_5 (0x000020UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1HTR_HTR_6 (0x000040UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1HTR_HTR_7 (0x000080UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1HTR_HTR_8 (0x000100UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1HTR_HTR_9 (0x000200UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1HTR_HTR_10 (0x000400UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1HTR_HTR_11 (0x000800UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1HTR_HTR_12 (0x001000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1HTR_HTR_13 (0x002000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1HTR_HTR_14 (0x004000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1HTR_HTR_15 (0x008000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1HTR_HTR_16 (0x010000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1HTR_HTR_17 (0x020000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1HTR_HTR_18 (0x040000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1HTR_HTR_19 (0x080000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1HTR_HTR_20 (0x100000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1HTR_HTR_21 (0x200000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1HTR_HTR_22 (0x400000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00400000 */ + +#define ADC_AWD1HTR_AWDFILT_Pos (29UL) +#define ADC_AWD1HTR_AWDFILT_Msk (0x7UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000007 */ +#define ADC_AWD1HTR_AWDFILT ADC_AWD1HTR_AWDFILT_Msk /*!< ADC analog watchdog 1 filtering */ +#define ADC_AWD1HTR_AWDFILT_0 (0x000001UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_AWDFILT_1 (0x000002UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_AWDFILT_2 (0x000004UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000004 */ + +/******************** Bit definition for ADC_AWD2TR_LT register *******************/ +#define ADC_AWD2LTR_LTR_Pos (0UL) +#define ADC_AWD2LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD2LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2LTR_LTR ADC_AWD2LTR_LTR_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2LTR_LTR_0 (0x000001UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2LTR_LTR_1 (0x000002UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2LTR_LTR_2 (0x000004UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2LTR_LTR_3 (0x000008UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2LTR_LTR_4 (0x000010UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2LTR_LTR_5 (0x000020UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2LTR_LTR_6 (0x000040UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2LTR_LTR_7 (0x000080UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2LTR_LTR_8 (0x000100UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2LTR_LTR_9 (0x000200UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2LTR_LTR_10 (0x000400UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2LTR_LTR_11 (0x000800UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2LTR_LTR_12 (0x001000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2LTR_LTR_13 (0x002000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2LTR_LTR_14 (0x004000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2LTR_LTR_15 (0x008000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2LTR_LTR_16 (0x010000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2LTR_LTR_17 (0x020000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2LTR_LTR_18 (0x040000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2LTR_LTR_19 (0x080000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2LTR_LTR_20 (0x100000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2LTR_LTR_21 (0x200000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2LTR_LTR_22 (0x400000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD2TR_HT register *******************/ +#define ADC_AWD2HTR_HTR_Pos (0UL) +#define ADC_AWD2HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD2HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2HTR_HTR ADC_AWD2HTR_HTR_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2HTR_HTR_0 (0x000001UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2HTR_HTR_1 (0x000002UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2HTR_HTR_2 (0x000004UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2HTR_HTR_3 (0x000008UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2HTR_HTR_4 (0x000010UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2HTR_HTR_5 (0x000020UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2HTR_HTR_6 (0x000040UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2HTR_HTR_7 (0x000080UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2HTR_HTR_8 (0x000100UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2HTR_HTR_9 (0x000200UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2HTR_HTR_10 (0x000400UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2HTR_HTR_11 (0x000800UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2HTR_HTR_12 (0x001000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2HTR_HTR_13 (0x002000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2HTR_HTR_14 (0x004000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2HTR_HTR_15 (0x008000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2HTR_HTR_16 (0x010000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2HTR_HTR_17 (0x020000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2HTR_HTR_18 (0x040000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2HTR_HTR_19 (0x080000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2HTR_HTR_20 (0x100000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2HTR_HTR_21 (0x200000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2HTR_HTR_22 (0x400000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD3TR_LT register *******************/ +#define ADC_AWD3LTR_LTR_Pos (0UL) +#define ADC_AWD3LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD3LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3LTR_LTR ADC_AWD3LTR_LTR_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3LTR_LTR_0 (0x000001UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3LTR_LTR_1 (0x000002UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3LTR_LTR_2 (0x000004UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3LTR_LTR_3 (0x000008UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3LTR_LTR_4 (0x000010UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3LTR_LTR_5 (0x000020UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3LTR_LTR_6 (0x000040UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3LTR_LTR_7 (0x000080UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3LTR_LTR_8 (0x000100UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3LTR_LTR_9 (0x000200UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3LTR_LTR_10 (0x000400UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3LTR_LTR_11 (0x000800UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3LTR_LTR_12 (0x001000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3LTR_LTR_13 (0x002000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3LTR_LTR_14 (0x004000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3LTR_LTR_15 (0x008000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3LTR_LTR_16 (0x010000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3LTR_LTR_17 (0x020000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3LTR_LTR_18 (0x040000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3LTR_LTR_19 (0x080000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3LTR_LTR_20 (0x100000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3LTR_LTR_21 (0x200000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3LTR_LTR_22 (0x400000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD3TR_HT register *******************/ +#define ADC_AWD3HTR_HTR_Pos (0UL) +#define ADC_AWD3HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD3HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3HTR_HTR ADC_AWD3HTR_HTR_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3HTR_HTR_0 (0x000001UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3HTR_HTR_1 (0x000002UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3HTR_HTR_2 (0x000004UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3HTR_HTR_3 (0x000008UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3HTR_HTR_4 (0x000010UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3HTR_HTR_5 (0x000020UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3HTR_HTR_6 (0x000040UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3HTR_HTR_7 (0x000080UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3HTR_HTR_8 (0x000100UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3HTR_HTR_9 (0x000200UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3HTR_HTR_10 (0x000400UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3HTR_HTR_11 (0x000800UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3HTR_HTR_12 (0x001000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3HTR_HTR_13 (0x002000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3HTR_HTR_14 (0x004000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3HTR_HTR_15 (0x008000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3HTR_HTR_16 (0x010000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3HTR_HTR_17 (0x020000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3HTR_HTR_18 (0x040000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3HTR_HTR_19 (0x080000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3HTR_HTR_20 (0x100000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3HTR_HTR_21 (0x200000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3HTR_HTR_22 (0x400000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ + +#define ADC_CALFACT_CALFACT_Pos (0UL) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_7 (0x80UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT_CALFACT_8 (0x100UL<< ADC_CALFACT_CALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_CALFACT_9 (0x200UL<< ADC_CALFACT_CALFACT_Pos) /*!< 0x00000200 */ + + +/******************** Bit definition for ADC_OR option register ***************/ +#define ADC_OR_VDDCOREEN_Pos (0UL) +#define ADC_OR_VDDCOREEN_Msk (0x1UL << ADC_OR_VDDCOREEN_Pos) /*!< 0x00000004 */ +#define ADC_OR_VDDCOREEN ADC_OR_VDDCOREEN_Msk /*!< ADC internal path to VDDCORE */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0UL) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1UL) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2UL) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3UL) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4UL) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5UL) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6UL) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7UL) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8UL) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9UL) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10UL) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ +#define ADC_CSR_LDORDY_MST_Pos (12UL) +#define ADC_CSR_LDORDY_MST_Msk (0x1UL << ADC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADC_CSR_LDORDY_MST ADC_CSR_LDORDY_MST_Msk /*!< ADC multimode master internal voltage regulator output ready flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16UL) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17UL) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18UL) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19UL) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20UL) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21UL) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22UL) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23UL) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24UL) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25UL) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26UL) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ +#define ADC_CSR_LDORDY_SLV_Pos (28UL) +#define ADC_CSR_LDORDY_SLV_Msk (0x1UL << ADC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CSR_LDORDY_SLV ADC_CSR_LDORDY_SLV_Msk /*!< ADC multimode slave internal voltage regulator output ready flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0UL) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8UL) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DAMDF_Pos (14UL) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< ADC multimode data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_PRESC_Pos (18UL) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22UL) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ + +#define ADC_CCR_TSEN_Pos (23UL) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to Temperature sensor voltage enable */ + +#define ADC_CCR_VBATEN_Pos (24UL) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0UL) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16UL) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0UL) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< ADC multimode master or slave (alternated) group regular conversion data */ + +/******************************************************************************/ +/* */ +/* Advanced Encryption Standard (AES) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AES_CR register *********************/ +#define AES_CR_EN_Pos (0UL) +#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ +#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ +#define AES_CR_DATATYPE_Pos (1UL) +#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ +#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ +#define AES_CR_MODE_Pos (3UL) +#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ +#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ +#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ +#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ +#define AES_CR_CHMOD_Pos (5UL) +#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ +#define AES_CR_DMAINEN_Pos (11UL) +#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define AES_CR_DMAOUTEN_Pos (12UL) +#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ +#define AES_CR_GCMPH_Pos (13UL) +#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ +#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ +#define AES_CR_KEYSIZE_Pos (18UL) +#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ +#define AES_CR_KEYPROT_Pos (19UL) +#define AES_CR_KEYPROT_Msk (0x1UL << AES_CR_KEYPROT_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYPROT AES_CR_KEYPROT_Msk /*!< Key protection */ +#define AES_CR_NPBLB_Pos (20UL) +#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */ +#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ +#define AES_CR_KMOD_Pos (24UL) +#define AES_CR_KMOD_Msk (0x3UL << AES_CR_KMOD_Pos) /*!< 0x03000000 */ +#define AES_CR_KMOD AES_CR_KMOD_Msk /*!< Key mode selection */ +#define AES_CR_KMOD_0 (0x1UL << AES_CR_KMOD_Pos) /*!< 0x01000000 */ +#define AES_CR_KMOD_1 (0x2UL << AES_CR_KMOD_Pos) /*!< 0x02000000 */ +#define AES_CR_KSHAREID_Pos (26UL) +#define AES_CR_KSHAREID_Msk (0x3UL << AES_CR_KSHAREID_Pos) /*!< 0x0C000000 */ +#define AES_CR_KSHAREID AES_CR_KSHAREID_Msk /*!< Key Shared ID */ +#define AES_CR_KEYSEL_Pos (28UL) +#define AES_CR_KEYSEL_Msk (0x7UL << AES_CR_KEYSEL_Pos) /*!< 0x70000000 */ +#define AES_CR_KEYSEL AES_CR_KEYSEL_Msk /*!< Key Selection */ +#define AES_CR_KEYSEL_0 (0x1UL << AES_CR_KEYSEL_Pos) /*!< 0x10000000 */ +#define AES_CR_KEYSEL_1 (0x2UL << AES_CR_KEYSEL_Pos) /*!< 0x20000000 */ +#define AES_CR_KEYSEL_2 (0x4UL << AES_CR_KEYSEL_Pos) /*!< 0x40000000 */ +#define AES_CR_IPRST_Pos (31UL) +#define AES_CR_IPRST_Msk (0x1UL << AES_CR_IPRST_Pos) /*!< 0x80000000 */ +#define AES_CR_IPRST AES_CR_IPRST_Msk /*!< AES IP software reset */ + +/******************* Bit definition for AES_SR register *********************/ +#define AES_SR_CCF_Pos (0UL) +#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ +#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define AES_SR_RDERR_Pos (1UL) +#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ +#define AES_SR_WRERR_Pos (2UL) +#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ +#define AES_SR_BUSY_Pos (3UL) +#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ +#define AES_SR_KEYVALID_Pos (7UL) +#define AES_SR_KEYVALID_Msk (0x1UL << AES_SR_KEYVALID_Pos) /*!< 0x00000080 */ +#define AES_SR_KEYVALID AES_SR_KEYVALID_Msk /*!< KEYVALID Flag */ + +/******************* Bit definition for AES_DINR register *******************/ +#define AES_DINR_Pos (0UL) +#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ + +/******************* Bit definition for AES_DOUTR register ******************/ +#define AES_DOUTR_Pos (0UL) +#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ + +/******************* Bit definition for AES_KEYR0 register ******************/ +#define AES_KEYR0_Pos (0UL) +#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ + +/******************* Bit definition for AES_KEYR1 register ******************/ +#define AES_KEYR1_Pos (0UL) +#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ + +/******************* Bit definition for AES_KEYR2 register ******************/ +#define AES_KEYR2_Pos (0UL) +#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ + +/******************* Bit definition for AES_KEYR3 register ******************/ +#define AES_KEYR3_Pos (0UL) +#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ + +/******************* Bit definition for AES_KEYR4 register ******************/ +#define AES_KEYR4_Pos (0UL) +#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ + +/******************* Bit definition for AES_KEYR5 register ******************/ +#define AES_KEYR5_Pos (0UL) +#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ + +/******************* Bit definition for AES_KEYR6 register ******************/ +#define AES_KEYR6_Pos (0UL) +#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ + +/******************* Bit definition for AES_KEYR7 register ******************/ +#define AES_KEYR7_Pos (0UL) +#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ + +/******************* Bit definition for AES_IVR0 register ******************/ +#define AES_IVR0_Pos (0UL) +#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ + +/******************* Bit definition for AES_IVR1 register ******************/ +#define AES_IVR1_Pos (0UL) +#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ + +/******************* Bit definition for AES_IVR2 register ******************/ +#define AES_IVR2_Pos (0UL) +#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ + +/******************* Bit definition for AES_IVR3 register ******************/ +#define AES_IVR3_Pos (0UL) +#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ + +/******************* Bit definition for AES_SUSP0R register ******************/ +#define AES_SUSP0R_Pos (0UL) +#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ + +/******************* Bit definition for AES_SUSP1R register ******************/ +#define AES_SUSP1R_Pos (0UL) +#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ + +/******************* Bit definition for AES_SUSP2R register ******************/ +#define AES_SUSP2R_Pos (0UL) +#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ + +/******************* Bit definition for AES_SUSP3R register ******************/ +#define AES_SUSP3R_Pos (0UL) +#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ + +/******************* Bit definition for AES_SUSP4R register ******************/ +#define AES_SUSP4R_Pos (0UL) +#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ + +/******************* Bit definition for AES_SUSP5R register ******************/ +#define AES_SUSP5R_Pos (0UL) +#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for AES_SUSP6R register ******************/ +#define AES_SUSP6R_Pos (0UL) +#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ + +/******************* Bit definition for AES_SUSP7R register ******************/ +#define AES_SUSP7R_Pos (0UL) +#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ + +/******************* Bit definition for AES_IER register ******************/ +#define AES_IER_CCFIE_Pos (0UL) +#define AES_IER_CCFIE_Msk (0x1UL << AES_IER_CCFIE_Pos) /*!< 0x00000001 */ +#define AES_IER_CCFIE AES_IER_CCFIE_Msk /*!< Computation complete flag interrupt enable */ +#define AES_IER_RWEIE_Pos (1UL) +#define AES_IER_RWEIE_Msk (0x1UL << AES_IER_RWEIE_Pos) /*!< 0x00000002 */ +#define AES_IER_RWEIE AES_IER_RWEIE_Msk /*!< Read or write error Interrupt Enable */ +#define AES_IER_KEIE_Pos (2UL) +#define AES_IER_KEIE_Msk (0x1UL << AES_IER_KEIE_Pos) /*!< 0x00000004 */ +#define AES_IER_KEIE AES_IER_KEIE_Msk /*!< Key error interrupt enable */ +#define AES_IER_RNGEIE_Pos (3UL) +#define AES_IER_RNGEIE_Msk (0x1UL << AES_IER_RNGEIE_Pos) /*!< 0x00000008 */ +#define AES_IER_RNGEIE AES_IER_RNGEIE_Msk /*!< Rng error interrupt enable */ + +/******************* Bit definition for AES_ISR register ******************/ +#define AES_ISR_CCF_Pos (0UL) +#define AES_ISR_CCF_Msk (0x1UL << AES_ISR_CCF_Pos) /*!< 0x00000001 */ +#define AES_ISR_CCF AES_ISR_CCF_Msk /*!< Computation complete flag */ +#define AES_ISR_RWEIF_Pos (1UL) +#define AES_ISR_RWEIF_Msk (0x1UL << AES_ISR_RWEIF_Pos) /*!< 0x00000002 */ +#define AES_ISR_RWEIF AES_ISR_RWEIF_Msk /*!< Read or write error Interrupt flag */ +#define AES_ISR_KEIF_Pos (2UL) +#define AES_ISR_KEIF_Msk (0x1UL << AES_ISR_KEIF_Pos) /*!< 0x00000004 */ +#define AES_ISR_KEIF AES_ISR_KEIF_Msk /*!< Key error interrupt flag */ +#define AES_ISR_RNGEIF_Pos (3UL) +#define AES_ISR_RNGEIF_Msk (0x1UL << AES_ISR_RNGEIF_Pos) /*!< 0x00000008 */ +#define AES_ISR_RNGEIF AES_ISR_RNGEIF_Msk /*!< Rng error interrupt flag */ + +/******************* Bit definition for AES_ICR register ******************/ +#define AES_ICR_CCF_Pos (0UL) +#define AES_ICR_CCF_Msk (0x1UL << AES_ICR_CCF_Pos) /*!< 0x00000001 */ +#define AES_ICR_CCF AES_ICR_CCF_Msk /*!< Computation complete flag clear */ +#define AES_ICR_RWEIF_Pos (1UL) +#define AES_ICR_RWEIF_Msk (0x1UL << AES_ICR_RWEIF_Pos) /*!< 0x00000002 */ +#define AES_ICR_RWEIF AES_ICR_RWEIF_Msk /*!< Read or write error Interrupt flag clear */ +#define AES_ICR_KEIF_Pos (2UL) +#define AES_ICR_KEIF_Msk (0x1UL << AES_ICR_KEIF_Pos) /*!< 0x00000004 */ +#define AES_ICR_KEIF AES_ICR_KEIF_Msk /*!< Key error interrupt flag clear */ +#define AES_ICR_RNGEIF_Pos (3UL) +#define AES_ICR_RNGEIF_Msk (0x1UL << AES_ICR_RNGEIF_Pos) /*!< 0x00000008 */ +#define AES_ICR_RNGEIF AES_ICR_RNGEIF_Msk /*!< Rng error interrupt flag clear */ + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0UL) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0UL) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0UL) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3UL) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5UL) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7UL) +#define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ +#define CRC_CR_RTYPE_IN_Pos (9UL) +#define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ +#define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< RTYPE_IN Reverse Type Input bit */ +#define CRC_CR_RTYPE_OUT_Pos (10UL) +#define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ +#define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< RTYPE_OUT Reverse Type Output bit */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0UL) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0UL) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0UL) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1UL) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2UL) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3UL) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5UL) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6UL) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7UL) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8UL) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0UL) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16UL) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24UL) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28UL) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31UL) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0UL) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1UL) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2UL) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3UL) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8UL) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9UL) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10UL) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15UL) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16UL) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0UL) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1UL) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2UL) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3UL) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ +/*!< ****************** Bit definition for COMPx_CSR register ********************/ +#define COMP_CSR_EN_Pos (0UL) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< COMPx enable bit */ +#define COMP_CSR_INMSEL_Pos (4UL) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00070000 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< COMPx input minus selection bit */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00010000 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00020000 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00040000 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00080000 */ +#define COMP_CSR_INPSEL_Pos (8UL) +#define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00100000 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< COMPx input plus selection bit */ +#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) +#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) +#define COMP_CSR_WINMODE_Pos (11UL) +#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000010 */ +#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< COMPx Windows mode selection bit */ +#define COMP_CSR_WINOUT_Pos (14UL) +#define COMP_CSR_WINOUT_Msk (0x1UL << COMP_CSR_WINOUT_Pos) /*!< 0x00000008 */ +#define COMP_CSR_WINOUT COMP_CSR_WINOUT_Msk /*!< COMPx polarity selection bit */ +#define COMP_CSR_POLARITY_Pos (15UL) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00000008 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< COMPx polarity selection bit */ +#define COMP_CSR_HYST_Pos (16UL) +#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00000300 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< COMPx hysteresis selection bits */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00000100 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00000200 */ +#define COMP_CSR_PWRMODE_Pos (18UL) +#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00003000 */ +#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< COMPx Power Mode of the comparator */ +#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00001000 */ +#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00002000 */ +#define COMP_CSR_BLANKSEL_Pos (20UL) +#define COMP_CSR_BLANKSEL_Msk (0x1FUL << COMP_CSR_BLANKSEL_Pos) /*!< 0x0F000000 */ +#define COMP_CSR_BLANKSEL COMP_CSR_BLANKSEL_Msk /*!< COMPx blanking source selection bits */ +#define COMP_CSR_BLANKSEL_0 (0x1UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ +#define COMP_CSR_BLANKSEL_1 (0x2UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x02000000 */ +#define COMP_CSR_BLANKSEL_2 (0x4UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x04000000 */ +#define COMP_CSR_BLANKSEL_3 (0x8UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x08000000 */ +#define COMP_CSR_BLANKSEL_4 (0x10UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ +#define COMP2_CSR_BLANKSEL_2 COMP_CSR_BLANKSEL_2 /*!< COMP2 blanking source selection bit 2 */ +#define COMP_CSR_VALUE_Pos (30UL) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x00000001 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< COMPx enable bit */ +#define COMP_CSR_LOCK_Pos (31UL) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< COMPx Lock Bit */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0UL) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14UL) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16UL) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30UL) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0UL) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4UL) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7UL) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8UL) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12UL) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15UL) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16UL) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20UL) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22UL) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23UL) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24UL) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28UL) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30UL) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31UL) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0UL) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24UL) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31UL) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0UL) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4UL) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7UL) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8UL) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12UL) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15UL) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16UL) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20UL) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22UL) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23UL) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24UL) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28UL) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30UL) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31UL) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0UL) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0UL) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1UL) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2UL) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3UL) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4UL) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5UL) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6UL) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0UL) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1UL) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2UL) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3UL) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4UL) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5UL) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6UL) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0UL) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1UL) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2UL) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3UL) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4UL) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5UL) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6UL) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0UL) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1UL) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2UL) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3UL) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4UL) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5UL) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6UL) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_TAMPTSCR register ******************/ +#define RTC_TAMPTSCR_TAMP1TS_Pos (0UL) +#define RTC_TAMPTSCR_TAMP1TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP1TS_Pos) /*!< 0x00000001 */ +#define RTC_TAMPTSCR_TAMP1TS RTC_TAMPTSCR_TAMP1TS_Msk +#define RTC_TAMPTSCR_TAMP2TS_Pos (1UL) +#define RTC_TAMPTSCR_TAMP2TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP2TS_Pos) /*!< 0x00000002 */ +#define RTC_TAMPTSCR_TAMP2TS RTC_TAMPTSCR_TAMP2TS_Msk +#define RTC_TAMPTSCR_TAMP3TS_Pos (2UL) +#define RTC_TAMPTSCR_TAMP3TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP3TS_Pos) /*!< 0x00000004 */ +#define RTC_TAMPTSCR_TAMP3TS RTC_TAMPTSCR_TAMP3TS_Msk +#define RTC_TAMPTSCR_TAMP4TS_Pos (3UL) +#define RTC_TAMPTSCR_TAMP4TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP4TS_Pos) /*!< 0x00000008 */ +#define RTC_TAMPTSCR_TAMP4TS RTC_TAMPTSCR_TAMP4TS_Msk +#define RTC_TAMPTSCR_TAMP5TS_Pos (4UL) +#define RTC_TAMPTSCR_TAMP5TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP5TS_Pos) /*!< 0x00000010 */ +#define RTC_TAMPTSCR_TAMP5TS RTC_TAMPTSCR_TAMP5TS_Msk +#define RTC_TAMPTSCR_ITAMPTS_Pos (16UL) +#define RTC_TAMPTSCR_ITAMPTS_Msk (0x1UL << RTC_TAMPTSCR_ITAMPTS_Pos) /*!< 0x00010000 */ +#define RTC_TAMPTSCR_ITAMPTS RTC_TAMPTSCR_ITAMPTS_Msk + +/******************** Bits definition for RTC_TSIDR register ******************/ +#define RTC_TSIDR_TSID_Pos (0UL) +#define RTC_TSIDR_TSID_Msk (0x3FUL << RTC_TSIDR_TSID_Pos) /*!< 0x0000003F */ +#define RTC_TSIDR_TSID RTC_TSIDR_TSID_Msk +#define RTC_TSIDR_TSID_0 (0x1UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000001 */ +#define RTC_TSIDR_TSID_1 (0x2UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000002 */ +#define RTC_TSIDR_TSID_2 (0x4UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000004 */ +#define RTC_TSIDR_TSID_3 (0x8UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000008 */ +#define RTC_TSIDR_TSID_4 (0x10UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000010 */ +#define RTC_TSIDR_TSID_5 (0x20UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000020 */ + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0UL) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0UL) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_SPE_Pos (0UL) +#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */ +#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*! 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + /** * @brief Power Control */ @@ -1300,7 +1317,7 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; #define FLASH_BASE_NS 0x08000000UL /*!< FLASH non-secure base address */ #define SYSTEM_FLASH_BASE_NS 0x0BF80000UL /*!< System FLASH non-secure base address */ #define SRAM1_BASE_NS 0x20000000UL /*!< SRAM1 non-secure base address */ -#define SRAM2_BASE_NS 0x20030000UL /*!< SRAM2 non-secure base address */ +#define SRAM2_BASE_NS 0x20020000UL /*!< SRAM2 non-secure base address */ #define PERIPH_BASE_NS 0x40000000UL /*!< Peripheral non-secure base address */ #define EXTRAM_BASE_NS 0x90000000UL /*!< External RAM base address */ @@ -1402,7 +1419,7 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; #define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x00004C00UL) #define COMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x00005400UL) #define COMP2_BASE_NS (COMP1_BASE_NS + 0x00000004UL) -#define LCD_BASE_NS (APB3PERIPH_BASE_NS + 0x00008000UL) +#define LCD_BASE_NS (APB3PERIPH_BASE_NS + 0x00008000UL) /*!< AHB2 Non secure peripherals */ #define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000000UL) @@ -1410,7 +1427,6 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; #define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000800UL) #define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000C00UL) #define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x00001000UL) -#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x00001800UL) #define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x00001C00UL) #define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008000UL) #define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008100UL) @@ -1419,6 +1435,8 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; #define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0400UL) #define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0710UL) #define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0800UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A2400UL) #define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0x000AF000UL) #define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0x000B1400UL) @@ -1427,7 +1445,7 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; #define FLASH_BASE_S 0x0C000000UL /*!< FLASH secure base address */ #define SYSTEM_FLASH_BASE_S 0x0FF80000UL /*!< System FLASH secure base address */ #define SRAM1_BASE_S 0x30000000UL /*!< SRAM1 secure base address */ -#define SRAM2_BASE_S 0x30030000UL /*!< SRAM2 secure base address */ +#define SRAM2_BASE_S 0x30020000UL /*!< SRAM2 secure base address */ #define PERIPH_BASE_S 0x50000000UL /*!< Peripheral secure base address */ /*!< Peripheral memory map - secure */ @@ -1516,7 +1534,6 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; #define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00000800UL) #define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00000C00UL) #define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x00001000UL) -#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x00001800UL) #define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x00001C00UL) #define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x00008000UL) #define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x00008100UL) @@ -1525,6 +1542,8 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; #define HASH_BASE_S (AHB2PERIPH_BASE_S + 0x000A0400UL) #define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0x000A0710UL) #define RNG_BASE_S (AHB2PERIPH_BASE_S + 0x000A0800UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0x000A2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0x000A2400UL) #define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0x000AF000UL) #define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0x000B1400UL) #endif /* CPU_IN_SECURE_STATE */ @@ -1538,7 +1557,6 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; /*!< USB PMA SIZE */ #define USB_DRD_PMA_SIZE (2048U) /*!< USB PMA Size 2Kbyte */ -#if defined (CPU_IN_SECURE_STATE) /*!< Root Secure Service Library */ /************ RSSLIB SAU system Flash region definition constants *************/ #define RSSLIB_SYS_FLASH_NS_PFUNC_START 0x0BF99040UL @@ -1553,11 +1571,11 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; #define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) /*!< HDP Area constant definition */ -#define RSSLIB_HDP_AREA_Pos 0U +#define RSSLIB_HDP_AREA_Pos 0UL #define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) -#define RSSLIB_HDP_AREA1_Pos 0U +#define RSSLIB_HDP_AREA1_Pos 0UL #define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) -#define RSSLIB_HDP_AREA2_Pos 1U +#define RSSLIB_HDP_AREA2_Pos 1UL #define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) #define RSSLIB_HDPEXT_CLOSE_BOUNDARY_OPEN 0xC9C9C9C9UL /* Access to HDPx extension area and HDPx area denied but HDPx_EXT (in FLASH_HDPEXTR) increment allowed at any time */ #define RSSLIB_HDPEXT_CLOSE_BOUNDARY_LOCK 0xD6D6D6D6UL /* Access to HDPx extension area and HDPx area denied. Update of HDPx_EXT size is not possible anymore */ @@ -1617,7 +1635,6 @@ typedef struct NSC_pFuncTypeDef NSC; S_pFuncTypeDef S; }RSSLIB_pFunc_TypeDef; -#endif /* CPU_IN_SECURE_STATE */ /* * Certificate address description @@ -1682,7 +1699,6 @@ typedef struct #define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) #define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) #define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) -#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) #define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) #define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) #define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) @@ -1704,6 +1720,7 @@ typedef struct #define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) #define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) #define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) #define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) #define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) #define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) @@ -1768,7 +1785,6 @@ typedef struct #define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) #define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) #define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) -#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) #define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) #define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) #define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) @@ -1791,6 +1807,7 @@ typedef struct #define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) #define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) #define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) #define PWR_S ((PWR_TypeDef *) PWR_BASE_S) #define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) #define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) @@ -1888,8 +1905,6 @@ typedef struct #define GPIOD_BASE GPIOD_BASE_S #define GPIOE GPIOE_S #define GPIOE_BASE GPIOE_BASE_S -#define GPIOG GPIOG_S -#define GPIOG_BASE GPIOG_BASE_S #define GPIOH GPIOH_S #define GPIOH_BASE GPIOH_BASE_S #define GTZC_MPCBB1 GTZC_MPCBB1_S @@ -1914,6 +1929,8 @@ typedef struct #define ICACHE_BASE ICACHE_BASE_S #define IWDG IWDG_S #define IWDG_BASE IWDG_BASE_S +#define LCD LCD_S +#define LCD_BASE LCD_BASE_S #define LPTIM1 LPTIM1_S #define LPTIM1_BASE LPTIM1_BASE_S #define LPTIM2 LPTIM2_S @@ -1932,6 +1949,9 @@ typedef struct #define OPAMP2_BASE OPAMP2_BASE_S #define OPAMP12_COMMON OPAMP12_COMMON_S #define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S #define PWR PWR_S #define PWR_BASE PWR_BASE_S #define RAMCFG_SRAM1 RAMCFG_SRAM1_S @@ -2059,8 +2079,6 @@ typedef struct #define GPIOD_BASE GPIOD_BASE_NS #define GPIOE GPIOE_NS #define GPIOE_BASE GPIOE_BASE_NS -#define GPIOG GPIOG_NS -#define GPIOG_BASE GPIOG_BASE_NS #define GPIOH GPIOH_NS #define GPIOH_BASE GPIOH_BASE_NS #define GTZC_MPCBB1 GTZC_MPCBB1_NS @@ -2083,6 +2101,8 @@ typedef struct #define ICACHE_BASE ICACHE_BASE_NS #define IWDG IWDG_NS #define IWDG_BASE IWDG_BASE_NS +#define LCD LCD_NS +#define LCD_BASE LCD_BASE_NS #define LPTIM1 LPTIM1_NS #define LPTIM1_BASE LPTIM1_BASE_NS #define LPTIM2 LPTIM2_NS @@ -2101,6 +2121,9 @@ typedef struct #define OPAMP2_BASE OPAMP2_BASE_NS #define OPAMP12_COMMON OPAMP12_COMMON_NS #define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS #define PWR PWR_NS #define PWR_BASE PWR_BASE_NS #define RAMCFG_SRAM1 RAMCFG_SRAM1_NS @@ -2188,124 +2211,124 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register *******************/ -#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Pos (0UL) #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ -#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Pos (1UL) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ -#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Pos (2UL) #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ -#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Pos (3UL) #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ -#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Pos (4UL) #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ -#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Pos (5UL) #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ -#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Pos (6UL) #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ -#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Pos (7UL) #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ -#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Pos (8UL) #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ -#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Pos (9UL) #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ -#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Pos (10UL) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ -#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Pos (12UL) #define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ #define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC internal voltage regulator output ready flag */ /******************** Bit definition for ADC_IER register *******************/ -#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Pos (0UL) #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ -#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Pos (1UL) #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ -#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Pos (2UL) #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ -#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Pos (3UL) #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ -#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Pos (4UL) #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ -#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Pos (5UL) #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ -#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Pos (6UL) #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ -#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Pos (7UL) #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ -#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Pos (8UL) #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ -#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Pos (9UL) #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ -#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Pos (10UL) #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ -#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Pos (12UL) #define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ #define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC internal voltage regulator interrupt*/ /******************** Bit definition for ADC_CR register ********************/ -#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Pos (0UL) #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ -#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Pos (1UL) #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ -#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Pos (2UL) #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ -#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Pos (3UL) #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ -#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Pos (4UL) #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ -#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Pos (5UL) #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ -#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Pos (28UL) #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC internal voltage regulator */ -#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Pos (29UL) #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ -#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Pos (31UL) #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR1 register ******************/ -#define ADC_CFGR1_DMNGT_Pos (0U) +#define ADC_CFGR1_DMNGT_Pos (0UL) #define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ #define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC data management configuration */ #define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ #define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ -#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Pos (2UL) #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ #define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ #define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ -#define ADC_CFGR1_EXTSEL_Pos (5U) +#define ADC_CFGR1_EXTSEL_Pos (5UL) #define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ #define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ @@ -2314,55 +2337,55 @@ typedef struct #define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ -#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Pos (10UL) #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ -#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Pos (12UL) #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ -#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Pos (13UL) #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ -#define ADC_CFGR1_AUTDLY_Pos (14U) +#define ADC_CFGR1_AUTDLY_Pos (14UL) #define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC low power auto wait */ -#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Pos (16UL) #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ -#define ADC_CFGR1_DISCNUM_Pos (17U) +#define ADC_CFGR1_DISCNUM_Pos (17UL) #define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ #define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ #define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ #define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ -#define ADC_CFGR1_JDISCEN_Pos (20U) +#define ADC_CFGR1_JDISCEN_Pos (20UL) #define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ -#define ADC_CFGR1_JQM_Pos (21U) +#define ADC_CFGR1_JQM_Pos (21UL) #define ADC_CFGR1_JQM_Msk (0x1UL << ADC_CFGR1_JQM_Pos) /*!< 0x00200000 */ #define ADC_CFGR1_JQM ADC_CFGR1_JQM_Msk /*!< ADC group injected contexts queue mode */ -#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Pos (22UL) #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ -#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Pos (23UL) #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ -#define ADC_CFGR1_JAWD1EN_Pos (24U) +#define ADC_CFGR1_JAWD1EN_Pos (24UL) #define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ -#define ADC_CFGR1_JAUTO_Pos (25U) +#define ADC_CFGR1_JAUTO_Pos (25UL) #define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ -#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Pos (26UL) #define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ #define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ @@ -2371,19 +2394,19 @@ typedef struct #define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ #define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ -#define ADC_CFGR1_JQDIS_Pos (31U) +#define ADC_CFGR1_JQDIS_Pos (31UL) #define ADC_CFGR1_JQDIS_Msk (0x1UL << ADC_CFGR1_JQDIS_Pos) /*!< 0x80000000 */ #define ADC_CFGR1_JQDIS ADC_CFGR1_JQDIS_Msk /*!< ADC group injected contexts queue disable */ /******************** Bit definition for ADC_CFGR2 register *****************/ -#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Pos (0UL) #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ -#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Pos (1UL) #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ -#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Pos (5UL) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ @@ -2391,26 +2414,26 @@ typedef struct #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ -#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Pos (9UL) #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ -#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Pos (10UL) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ -#define ADC_CFGR2_BULB_Pos (13U) +#define ADC_CFGR2_BULB_Pos (13UL) #define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ #define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC bulb sampling mode */ -#define ADC_CFGR2_SWTRIG_Pos (14U) +#define ADC_CFGR2_SWTRIG_Pos (14UL) #define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC software trigger bit for sampling time control trigger mode */ -#define ADC_CFGR2_SMPTRIG_Pos (15U) +#define ADC_CFGR2_SMPTRIG_Pos (15UL) #define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ #define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC sampling time control trigger mode */ -#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Pos (16UL) #define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ #define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ @@ -2424,11 +2447,11 @@ typedef struct #define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ #define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ -#define ADC_CFGR2_LFTRIG_Pos (27U) +#define ADC_CFGR2_LFTRIG_Pos (27UL) #define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ #define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low-frequency trigge */ -#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Pos (28UL) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ #define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC left shift factor */ #define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ @@ -2437,70 +2460,70 @@ typedef struct #define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_SMPR1 register *****************/ -#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Pos (0UL) #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ -#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Pos (3UL) #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ -#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Pos (6UL) #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ -#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Pos (9UL) #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ -#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Pos (12UL) #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ -#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Pos (15UL) #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ -#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Pos (18UL) #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ -#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Pos (21UL) #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ -#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Pos (24UL) #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ -#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Pos (27UL) #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ @@ -2508,70 +2531,70 @@ typedef struct #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ /******************** Bit definition for ADC_SMPR2 register *****************/ -#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Pos (0UL) #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ -#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Pos (3UL) #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ -#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Pos (6UL) #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ -#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Pos (9UL) #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ -#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Pos (12UL) #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ -#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Pos (15UL) #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ -#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Pos (18UL) #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ -#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Pos (21UL) #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ -#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Pos (24UL) #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ -#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Pos (27UL) #define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ #define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ #define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ @@ -2579,7 +2602,7 @@ typedef struct #define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ /******************** Bit definition for ADC_PCSEL register *****************/ -#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Pos (0UL) #define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ #define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC channel preselection */ #define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ @@ -2603,7 +2626,7 @@ typedef struct #define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_SQR1 register ******************/ -#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Pos (0UL) #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ @@ -2611,7 +2634,7 @@ typedef struct #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ -#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Pos (6UL) #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ @@ -2620,7 +2643,7 @@ typedef struct #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ -#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Pos (12UL) #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ @@ -2629,7 +2652,7 @@ typedef struct #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ -#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Pos (18UL) #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ @@ -2638,7 +2661,7 @@ typedef struct #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ #define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ -#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Pos (24UL) #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ @@ -2648,7 +2671,7 @@ typedef struct #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ******************/ -#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Pos (0UL) #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ @@ -2657,7 +2680,7 @@ typedef struct #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ -#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Pos (6UL) #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ @@ -2666,7 +2689,7 @@ typedef struct #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ -#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Pos (12UL) #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ @@ -2675,7 +2698,7 @@ typedef struct #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ -#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Pos (18UL) #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ @@ -2684,7 +2707,7 @@ typedef struct #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ -#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Pos (24UL) #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ @@ -2694,7 +2717,7 @@ typedef struct #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ******************/ -#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Pos (0UL) #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ @@ -2703,7 +2726,7 @@ typedef struct #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ -#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Pos (6UL) #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ @@ -2712,7 +2735,7 @@ typedef struct #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ -#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Pos (12UL) #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ @@ -2721,7 +2744,7 @@ typedef struct #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ -#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Pos (18UL) #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ @@ -2730,7 +2753,7 @@ typedef struct #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ -#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Pos (24UL) #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ @@ -2740,7 +2763,7 @@ typedef struct #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ******************/ -#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Pos (0UL) #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ @@ -2749,7 +2772,7 @@ typedef struct #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ -#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Pos (6UL) #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ @@ -2759,7 +2782,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Pos (0UL) #define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ #define ADC_DR_RDATA_0 (0x00000001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ @@ -2796,13 +2819,13 @@ typedef struct #define ADC_DR_RDATA_31 (0x80000000UL << ADC_DR_RDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JSQR register ******************/ -#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Pos (0UL) #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ -#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Pos (2UL) #define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ #define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ @@ -2811,13 +2834,13 @@ typedef struct #define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ -#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Pos (7UL) #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ -#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Pos (9UL) #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ @@ -2826,7 +2849,7 @@ typedef struct #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ -#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Pos (15UL) #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ @@ -2835,7 +2858,7 @@ typedef struct #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ -#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Pos (21UL) #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ @@ -2844,7 +2867,7 @@ typedef struct #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ -#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Pos (27UL) #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ @@ -2854,19 +2877,19 @@ typedef struct #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFCFGR1 register ***************/ -#define ADC_OFCFGR1_POSOFF_Pos (24U) +#define ADC_OFCFGR1_POSOFF_Pos (24UL) #define ADC_OFCFGR1_POSOFF_Msk (0x01UL << ADC_OFCFGR1_POSOFF_Pos) /*!< 0x01000000 */ #define ADC_OFCFGR1_POSOFF ADC_OFCFGR1_POSOFF_Msk /*!< ADC offset instance 1 positive offset enable */ -#define ADC_OFCFGR1_USAT_Pos (25U) +#define ADC_OFCFGR1_USAT_Pos (25UL) #define ADC_OFCFGR1_USAT_Msk (0x01UL << ADC_OFCFGR1_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFCFGR1_USAT ADC_OFCFGR1_USAT_Msk /*!< ADC offset instance 1 unsigned saturation value */ -#define ADC_OFCFGR1_SSAT_Pos (26U) +#define ADC_OFCFGR1_SSAT_Pos (26UL) #define ADC_OFCFGR1_SSAT_Msk (0x01UL << ADC_OFCFGR1_SSAT_Pos) /*!< 0x04000000 */ #define ADC_OFCFGR1_SSAT ADC_OFCFGR1_SSAT_Msk /*!< ADC offset instance 1 signed satuaration enable */ -#define ADC_OFCFGR1_OFFSET_CH_Pos (27U) +#define ADC_OFCFGR1_OFFSET_CH_Pos (27UL) #define ADC_OFCFGR1_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0xF8000000 */ #define ADC_OFCFGR1_OFFSET_CH ADC_OFCFGR1_OFFSET_CH_Msk /*!< ADC offset instance 1 channel selection */ #define ADC_OFCFGR1_OFFSET_CH_0 (0x01UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x08000000 */ @@ -2876,19 +2899,19 @@ typedef struct #define ADC_OFCFGR1_OFFSET_CH_4 (0x05UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFCFGR2 register ***************/ -#define ADC_OFCFGR2_POSOFF_Pos (24U) +#define ADC_OFCFGR2_POSOFF_Pos (24UL) #define ADC_OFCFGR2_POSOFF_Msk (0x01UL << ADC_OFCFGR2_POSOFF_Pos) /*!< 0x01000000 */ #define ADC_OFCFGR2_POSOFF ADC_OFCFGR2_POSOFF_Msk /*!< ADC offset instance 2 positive offset enable */ -#define ADC_OFCFGR2_USAT_Pos (25U) +#define ADC_OFCFGR2_USAT_Pos (25UL) #define ADC_OFCFGR2_USAT_Msk (0x01UL << ADC_OFCFGR2_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFCFGR2_USAT ADC_OFCFGR2_USAT_Msk /*!< ADC offset instance 2 unsigned saturation value */ -#define ADC_OFCFGR2_SSAT_Pos (26U) +#define ADC_OFCFGR2_SSAT_Pos (26UL) #define ADC_OFCFGR2_SSAT_Msk (0x01UL << ADC_OFCFGR2_SSAT_Pos) /*!< 0x04000000 */ #define ADC_OFCFGR2_SSAT ADC_OFCFGR2_SSAT_Msk /*!< ADC offset instance 2 signed satuaration enable */ -#define ADC_OFCFGR2_OFFSET_CH_Pos (27U) +#define ADC_OFCFGR2_OFFSET_CH_Pos (27UL) #define ADC_OFCFGR2_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0xF8000000 */ #define ADC_OFCFGR2_OFFSET_CH ADC_OFCFGR2_OFFSET_CH_Msk /*!< ADC offset instance 2 channel selection */ #define ADC_OFCFGR2_OFFSET_CH_0 (0x01UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x08000000 */ @@ -2898,19 +2921,19 @@ typedef struct #define ADC_OFCFGR2_OFFSET_CH_4 (0x05UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFCFGR3 register ***************/ -#define ADC_OFCFGR3_POSOFF_Pos (24U) +#define ADC_OFCFGR3_POSOFF_Pos (24UL) #define ADC_OFCFGR3_POSOFF_Msk (0x01UL << ADC_OFCFGR3_POSOFF_Pos) /*!< 0x01000000 */ #define ADC_OFCFGR3_POSOFF ADC_OFCFGR3_POSOFF_Msk /*!< ADC offset instance 3 positive offset enable */ -#define ADC_OFCFGR3_USAT_Pos (25U) +#define ADC_OFCFGR3_USAT_Pos (25UL) #define ADC_OFCFGR3_USAT_Msk (0x01UL << ADC_OFCFGR3_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFCFGR3_USAT ADC_OFCFGR3_USAT_Msk /*!< ADC offset instance 3 unsigned saturation value */ -#define ADC_OFCFGR3_SSAT_Pos (26U) +#define ADC_OFCFGR3_SSAT_Pos (26UL) #define ADC_OFCFGR3_SSAT_Msk (0x01UL << ADC_OFCFGR3_SSAT_Pos) /*!< 0x04000000 */ #define ADC_OFCFGR3_SSAT ADC_OFCFGR3_SSAT_Msk /*!< ADC offset instance 3 signed satuaration enable */ -#define ADC_OFCFGR3_OFFSET_CH_Pos (27U) +#define ADC_OFCFGR3_OFFSET_CH_Pos (27UL) #define ADC_OFCFGR3_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0xF8000000 */ #define ADC_OFCFGR3_OFFSET_CH ADC_OFCFGR3_OFFSET_CH_Msk /*!< ADC offset instance 3 channel selection for the data offset */ #define ADC_OFCFGR3_OFFSET_CH_0 (0x01UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x08000000 */ @@ -2920,19 +2943,19 @@ typedef struct #define ADC_OFCFGR3_OFFSET_CH_4 (0x05UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFCFGR4 register ***************/ -#define ADC_OFCFGR4_POSOFF_Pos (24U) +#define ADC_OFCFGR4_POSOFF_Pos (24UL) #define ADC_OFCFGR4_POSOFF_Msk (0x01UL << ADC_OFCFGR4_POSOFF_Pos) /*!< 0x01000000 */ #define ADC_OFCFGR4_POSOFF ADC_OFCFGR4_POSOFF_Msk /*!< ADC offset instance 4 positive offset enable */ -#define ADC_OFCFGR4_USAT_Pos (25U) +#define ADC_OFCFGR4_USAT_Pos (25UL) #define ADC_OFCFGR4_USAT_Msk (0x01UL << ADC_OFCFGR4_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFCFGR4_USAT ADC_OFCFGR4_USAT_Msk /*!< ADC offset instance 4 unsigned saturation value */ -#define ADC_OFCFGR4_SSAT_Pos (26U) +#define ADC_OFCFGR4_SSAT_Pos (26UL) #define ADC_OFCFGR4_SSAT_Msk (0x01UL << ADC_OFCFGR4_SSAT_Pos) /*!< 0x04000000 */ #define ADC_OFCFGR4_SSAT ADC_OFCFGR4_SSAT_Msk /*!< ADC offset instance 4 signed satuaration enable */ -#define ADC_OFCFGR4_OFFSET_CH_Pos (27U) +#define ADC_OFCFGR4_OFFSET_CH_Pos (27UL) #define ADC_OFCFGR4_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0xF8000000 */ #define ADC_OFCFGR4_OFFSET_CH ADC_OFCFGR4_OFFSET_CH_Msk /*!< ADC offset instance 4 channel selection for the data offset */ #define ADC_OFCFGR4_OFFSET_CH_0 (0x01UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x08000000 */ @@ -2942,7 +2965,7 @@ typedef struct #define ADC_OFCFGR4_OFFSET_CH_4 (0x05UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFR1 register ******************/ -#define ADC_OFR1_OFFSET_Pos (0U) +#define ADC_OFR1_OFFSET_Pos (0UL) #define ADC_OFR1_OFFSET_Msk (0x03FFFFFUL << ADC_OFR1_OFFSET_Pos) /*!< 0x003FFFFF */ #define ADC_OFR1_OFFSET ADC_OFR1_OFFSET_Msk /*!< ADC offset instance 1 offset level */ #define ADC_OFR1_OFFSET_0 (0x0000001UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000001 */ @@ -2969,7 +2992,7 @@ typedef struct #define ADC_OFR1_OFFSET_21 (0x0200000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00200000 */ /******************** Bit definition for ADC_OFR2 register ******************/ -#define ADC_OFR2_OFFSET_Pos (0U) +#define ADC_OFR2_OFFSET_Pos (0UL) #define ADC_OFR2_OFFSET_Msk (0x03FFFFFUL << ADC_OFR2_OFFSET_Pos) /*!< 0x003FFFFF */ #define ADC_OFR2_OFFSET ADC_OFR2_OFFSET_Msk /*!< ADC offset instance 2 offset level */ #define ADC_OFR2_OFFSET_0 (0x0000001UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000001 */ @@ -2996,7 +3019,7 @@ typedef struct #define ADC_OFR2_OFFSET_21 (0x0200000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00200000 */ /******************** Bit definition for ADC_OFR3 register ******************/ -#define ADC_OFR3_OFFSET_Pos (0U) +#define ADC_OFR3_OFFSET_Pos (0UL) #define ADC_OFR3_OFFSET_Msk (0x03FFFFFUL << ADC_OFR3_OFFSET_Pos) /*!< 0x003FFFFF */ #define ADC_OFR3_OFFSET ADC_OFR3_OFFSET_Msk /*!< ADC offset instance 3 offset level */ #define ADC_OFR3_OFFSET_0 (0x0000001UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000001 */ @@ -3023,7 +3046,7 @@ typedef struct #define ADC_OFR3_OFFSET_21 (0x0200000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00200000 */ /******************** Bit definition for ADC_OFR4 register ******************/ -#define ADC_OFR4_OFFSET_Pos (0U) +#define ADC_OFR4_OFFSET_Pos (0UL) #define ADC_OFR4_OFFSET_Msk (0x03FFFFFUL << ADC_OFR4_OFFSET_Pos) /*!< 0x003FFFFF */ #define ADC_OFR4_OFFSET ADC_OFR4_OFFSET_Msk /*!< ADC offset instance 4 offset level */ #define ADC_OFR4_OFFSET_0 (0x0000001UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000001 */ @@ -3050,7 +3073,7 @@ typedef struct #define ADC_OFR4_OFFSET_21 (0x0200000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00200000 */ /******************** Bit definition for ADC_GCOMP register *****************/ -#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) #define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ #define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< Gain compensation coefficient */ #define ADC_GCOMP_GCOMPCOEFF_0 (0x0001UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000001 */ @@ -3068,12 +3091,12 @@ typedef struct #define ADC_GCOMP_GCOMPCOEFF_12 (0x1000UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00001000 */ #define ADC_GCOMP_GCOMPCOEFF_13 (0x2000UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00002000 */ -#define ADC_GCOMP_GCOMP_Pos (31U) +#define ADC_GCOMP_GCOMP_Pos (31UL) #define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x80000000 */ #define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< Gain compensation mode */ /******************** Bit definition for ADC_JDR1 register ******************/ -#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Pos (0UL) #define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ #define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ @@ -3110,7 +3133,7 @@ typedef struct #define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JDR2 register ********************/ -#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Pos (0UL) #define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ #define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ @@ -3147,7 +3170,7 @@ typedef struct #define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JDR3 register ********************/ -#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Pos (0UL) #define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ #define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ @@ -3184,7 +3207,7 @@ typedef struct #define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JDR4 register ********************/ -#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Pos (0UL) #define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ #define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ @@ -3221,7 +3244,7 @@ typedef struct #define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_AWD2CR register ****************/ -#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Pos (0UL) #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ @@ -3245,7 +3268,7 @@ typedef struct #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ -#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Pos (0UL) #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ @@ -3269,7 +3292,7 @@ typedef struct #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_AWD1TR_LT register *************/ -#define ADC_AWD1LTR_LTR_Pos (0U) +#define ADC_AWD1LTR_LTR_Pos (0UL) #define ADC_AWD1LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD1LTR_LTR_Pos) /*!< 0x007FFFFF */ #define ADC_AWD1LTR_LTR ADC_AWD1LTR_LTR_Msk /*!< ADC analog watchdog 1 threshold low */ #define ADC_AWD1LTR_LTR_0 (0x000001UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000001 */ @@ -3297,7 +3320,7 @@ typedef struct #define ADC_AWD1LTR_LTR_22 (0x400000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00400000 */ /******************** Bit definition for ADC_AWD1TR_HT register *******************/ -#define ADC_AWD1HTR_HTR_Pos (0U) +#define ADC_AWD1HTR_HTR_Pos (0UL) #define ADC_AWD1HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD1HTR_HTR_Pos) /*!< 0x007FFFFF */ #define ADC_AWD1HTR_HTR ADC_AWD1HTR_HTR_Msk /*!< ADC analog watchdog 1 threshold high */ #define ADC_AWD1HTR_HTR_0 (0x000001UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000001 */ @@ -3324,7 +3347,7 @@ typedef struct #define ADC_AWD1HTR_HTR_21 (0x200000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00200000 */ #define ADC_AWD1HTR_HTR_22 (0x400000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00400000 */ -#define ADC_AWD1HTR_AWDFILT_Pos (29U) +#define ADC_AWD1HTR_AWDFILT_Pos (29UL) #define ADC_AWD1HTR_AWDFILT_Msk (0x7UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000007 */ #define ADC_AWD1HTR_AWDFILT ADC_AWD1HTR_AWDFILT_Msk /*!< ADC analog watchdog 1 filtering */ #define ADC_AWD1HTR_AWDFILT_0 (0x000001UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000001 */ @@ -3332,7 +3355,7 @@ typedef struct #define ADC_AWD1HTR_AWDFILT_2 (0x000004UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000004 */ /******************** Bit definition for ADC_AWD2TR_LT register *******************/ -#define ADC_AWD2LTR_LTR_Pos (0U) +#define ADC_AWD2LTR_LTR_Pos (0UL) #define ADC_AWD2LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD2LTR_LTR_Pos) /*!< 0x007FFFFF */ #define ADC_AWD2LTR_LTR ADC_AWD2LTR_LTR_Msk /*!< ADC analog watchdog 2 threshold low */ #define ADC_AWD2LTR_LTR_0 (0x000001UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000001 */ @@ -3360,7 +3383,7 @@ typedef struct #define ADC_AWD2LTR_LTR_22 (0x400000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00400000 */ /******************** Bit definition for ADC_AWD2TR_HT register *******************/ -#define ADC_AWD2HTR_HTR_Pos (0U) +#define ADC_AWD2HTR_HTR_Pos (0UL) #define ADC_AWD2HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD2HTR_HTR_Pos) /*!< 0x007FFFFF */ #define ADC_AWD2HTR_HTR ADC_AWD2HTR_HTR_Msk /*!< ADC analog watchdog 2 threshold high */ #define ADC_AWD2HTR_HTR_0 (0x000001UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000001 */ @@ -3388,7 +3411,7 @@ typedef struct #define ADC_AWD2HTR_HTR_22 (0x400000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00400000 */ /******************** Bit definition for ADC_AWD3TR_LT register *******************/ -#define ADC_AWD3LTR_LTR_Pos (0U) +#define ADC_AWD3LTR_LTR_Pos (0UL) #define ADC_AWD3LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD3LTR_LTR_Pos) /*!< 0x007FFFFF */ #define ADC_AWD3LTR_LTR ADC_AWD3LTR_LTR_Msk /*!< ADC analog watchdog 3 threshold low */ #define ADC_AWD3LTR_LTR_0 (0x000001UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000001 */ @@ -3416,7 +3439,7 @@ typedef struct #define ADC_AWD3LTR_LTR_22 (0x400000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00400000 */ /******************** Bit definition for ADC_AWD3TR_HT register *******************/ -#define ADC_AWD3HTR_HTR_Pos (0U) +#define ADC_AWD3HTR_HTR_Pos (0UL) #define ADC_AWD3HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD3HTR_HTR_Pos) /*!< 0x007FFFFF */ #define ADC_AWD3HTR_HTR ADC_AWD3HTR_HTR_Msk /*!< ADC analog watchdog 3 threshold high */ #define ADC_AWD3HTR_HTR_0 (0x000001UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000001 */ @@ -3443,34 +3466,9 @@ typedef struct #define ADC_AWD3HTR_HTR_21 (0x200000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00200000 */ #define ADC_AWD3HTR_HTR_22 (0x400000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00400000 */ -/******************** Bit definition for ADC_DIFSEL register ****************/ -#define ADC_DIFSEL_DIFSEL_Pos (0U) -#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ -#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode selection */ -#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ -#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ -#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ -#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ -#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ -#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ -#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ -#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ -#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ -#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ -#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ -#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ -#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ -#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ -#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ -#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ -#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ -#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ -#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ -#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ - /******************** Bit definition for ADC_CALFACT register ***************/ -#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Pos (0UL) #define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ #define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ #define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ @@ -3486,88 +3484,88 @@ typedef struct /******************** Bit definition for ADC_OR option register ***************/ -#define ADC_OR_VDDCOREEN_Pos (0U) +#define ADC_OR_VDDCOREEN_Pos (0UL) #define ADC_OR_VDDCOREEN_Msk (0x1UL << ADC_OR_VDDCOREEN_Pos) /*!< 0x00000004 */ #define ADC_OR_VDDCOREEN ADC_OR_VDDCOREEN_Msk /*!< ADC internal path to VDDCORE */ /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register *******************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Pos (0UL) #define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ -#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Pos (1UL) #define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ -#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Pos (2UL) #define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ -#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Pos (3UL) #define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ -#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Pos (4UL) #define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ -#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Pos (5UL) #define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ -#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Pos (6UL) #define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ -#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Pos (7UL) #define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ -#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Pos (8UL) #define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ -#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Pos (9UL) #define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ -#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Pos (10UL) #define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ -#define ADC_CSR_LDORDY_MST_Pos (12U) +#define ADC_CSR_LDORDY_MST_Pos (12UL) #define ADC_CSR_LDORDY_MST_Msk (0x1UL << ADC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ #define ADC_CSR_LDORDY_MST ADC_CSR_LDORDY_MST_Msk /*!< ADC multimode master internal voltage regulator output ready flag */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Pos (16UL) #define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Pos (17UL) #define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ -#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Pos (18UL) #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ -#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Pos (19UL) #define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ -#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Pos (20UL) #define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ -#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Pos (21UL) #define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ -#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Pos (22UL) #define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ -#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Pos (23UL) #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ -#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Pos (24UL) #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ -#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Pos (25UL) #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Pos (26UL) #define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ -#define ADC_CSR_LDORDY_SLV_Pos (28U) +#define ADC_CSR_LDORDY_SLV_Pos (28UL) #define ADC_CSR_LDORDY_SLV_Msk (0x1UL << ADC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ #define ADC_CSR_LDORDY_SLV ADC_CSR_LDORDY_SLV_Msk /*!< ADC multimode slave internal voltage regulator output ready flag */ /******************** Bit definition for ADC_CCR register *******************/ -#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Pos (0UL) #define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ #define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ @@ -3576,7 +3574,7 @@ typedef struct #define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ #define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ -#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Pos (8UL) #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ @@ -3584,13 +3582,13 @@ typedef struct #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ -#define ADC_CCR_DAMDF_Pos (14U) +#define ADC_CCR_DAMDF_Pos (14UL) #define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ #define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< ADC multimode data format */ #define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ #define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ -#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Pos (18UL) #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler */ #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ @@ -3598,29 +3596,29 @@ typedef struct #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ -#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Pos (22UL) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ -#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Pos (23UL) #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to Temperature sensor voltage enable */ -#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Pos (24UL) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ /******************** Bit definition for ADC_CDR register *******************/ -#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Pos (0UL) #define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ -#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Pos (16UL) #define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ /******************** Bit definition for ADC_CDR2 register ******************/ -#define ADC_CDR2_RDATA_ALT_Pos (0U) +#define ADC_CDR2_RDATA_ALT_Pos (0UL) #define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ #define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< ADC multimode master or slave (alternated) group regular conversion data */ @@ -3630,48 +3628,48 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Pos (0UL) #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Pos (0UL) #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ /******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Pos (0UL) #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ -#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Pos (3UL) #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ -#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Pos (5UL) #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ -#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Pos (7UL) #define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ #define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ #define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ -#define CRC_CR_RTYPE_IN_Pos (9U) +#define CRC_CR_RTYPE_IN_Pos (9UL) #define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ #define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< RTYPE_IN Reverse Type Input bit */ -#define CRC_CR_RTYPE_OUT_Pos (10U) +#define CRC_CR_RTYPE_OUT_Pos (10UL) #define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ #define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< RTYPE_OUT Reverse Type Output bit */ /******************* Bit definition for CRC_INIT register *******************/ -#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Pos (0UL) #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ /******************* Bit definition for CRC_POL register ********************/ -#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Pos (0UL) #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ @@ -3680,93 +3678,93 @@ typedef struct /* CRS Clock Recovery System */ /******************************************************************************/ /******************* Bit definition for CRS_CR register *********************/ -#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Pos (0UL) #define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ -#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Pos (1UL) #define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ -#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Pos (2UL) #define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ -#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Pos (3UL) #define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ -#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Pos (5UL) #define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ -#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Pos (6UL) #define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ -#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Pos (7UL) #define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ -#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Pos (8UL) #define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ -#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Pos (0UL) #define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ -#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Pos (16UL) #define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ -#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Pos (24UL) #define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ #define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ #define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ #define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ -#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Pos (28UL) #define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ #define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ #define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ -#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Pos (31UL) #define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ /******************* Bit definition for CRS_ISR register *********************/ -#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Pos (0UL) #define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ -#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Pos (1UL) #define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ -#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Pos (2UL) #define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ -#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Pos (3UL) #define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ -#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Pos (8UL) #define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ -#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Pos (9UL) #define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ -#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Pos (10UL) #define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ -#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Pos (15UL) #define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ -#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Pos (16UL) #define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ /******************* Bit definition for CRS_ICR register *********************/ -#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Pos (0UL) #define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ -#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Pos (1UL) #define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ -#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Pos (2UL) #define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ -#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Pos (3UL) #define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ @@ -3776,41 +3774,41 @@ typedef struct /* */ /******************************************************************************/ /*!< ****************** Bit definition for COMPx_CSR register ********************/ -#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Pos (0UL) #define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ #define COMP_CSR_EN COMP_CSR_EN_Msk /*!< COMPx enable bit */ -#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Pos (4UL) #define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00070000 */ #define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< COMPx input minus selection bit */ #define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00010000 */ #define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00020000 */ #define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00040000 */ #define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00080000 */ -#define COMP_CSR_INPSEL_Pos (8U) +#define COMP_CSR_INPSEL_Pos (8UL) #define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00100000 */ #define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< COMPx input plus selection bit */ #define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) #define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) -#define COMP_CSR_WINMODE_Pos (11U) +#define COMP_CSR_WINMODE_Pos (11UL) #define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000010 */ #define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< COMPx Windows mode selection bit */ -#define COMP_CSR_WINOUT_Pos (14U) +#define COMP_CSR_WINOUT_Pos (14UL) #define COMP_CSR_WINOUT_Msk (0x1UL << COMP_CSR_WINOUT_Pos) /*!< 0x00000008 */ #define COMP_CSR_WINOUT COMP_CSR_WINOUT_Msk /*!< COMPx polarity selection bit */ -#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Pos (15UL) #define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00000008 */ #define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< COMPx polarity selection bit */ -#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Pos (16UL) #define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00000300 */ #define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< COMPx hysteresis selection bits */ #define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00000100 */ #define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00000200 */ -#define COMP_CSR_PWRMODE_Pos (18U) +#define COMP_CSR_PWRMODE_Pos (18UL) #define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00003000 */ #define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< COMPx Power Mode of the comparator */ #define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00001000 */ #define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00002000 */ -#define COMP_CSR_BLANKSEL_Pos (20U) +#define COMP_CSR_BLANKSEL_Pos (20UL) #define COMP_CSR_BLANKSEL_Msk (0x1FUL << COMP_CSR_BLANKSEL_Pos) /*!< 0x0F000000 */ #define COMP_CSR_BLANKSEL COMP_CSR_BLANKSEL_Msk /*!< COMPx blanking source selection bits */ #define COMP_CSR_BLANKSEL_0 (0x1UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ @@ -3818,10 +3816,11 @@ typedef struct #define COMP_CSR_BLANKSEL_2 (0x4UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x04000000 */ #define COMP_CSR_BLANKSEL_3 (0x8UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x08000000 */ #define COMP_CSR_BLANKSEL_4 (0x10UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ -#define COMP_CSR_VALUE_Pos (30U) +#define COMP2_CSR_BLANKSEL_2 COMP_CSR_BLANKSEL_2 /*!< COMP2 blanking source selection bit 2 */ +#define COMP_CSR_VALUE_Pos (30UL) #define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x00000001 */ #define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< COMPx enable bit */ -#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Pos (31UL) #define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ #define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< COMPx Lock Bit */ @@ -3833,277 +3832,277 @@ typedef struct #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ /******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Pos (0UL) #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -14319,85 +13646,85 @@ typedef struct #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -14406,124 +13733,124 @@ typedef struct #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Pos (5UL) #define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_TAMPTSCR register ******************/ -#define RTC_TAMPTSCR_TAMP1TS_Pos (0U) +#define RTC_TAMPTSCR_TAMP1TS_Pos (0UL) #define RTC_TAMPTSCR_TAMP1TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP1TS_Pos) /*!< 0x00000001 */ #define RTC_TAMPTSCR_TAMP1TS RTC_TAMPTSCR_TAMP1TS_Msk -#define RTC_TAMPTSCR_TAMP2TS_Pos (1U) +#define RTC_TAMPTSCR_TAMP2TS_Pos (1UL) #define RTC_TAMPTSCR_TAMP2TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP2TS_Pos) /*!< 0x00000002 */ #define RTC_TAMPTSCR_TAMP2TS RTC_TAMPTSCR_TAMP2TS_Msk -#define RTC_TAMPTSCR_TAMP3TS_Pos (2U) +#define RTC_TAMPTSCR_TAMP3TS_Pos (2UL) #define RTC_TAMPTSCR_TAMP3TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP3TS_Pos) /*!< 0x00000004 */ #define RTC_TAMPTSCR_TAMP3TS RTC_TAMPTSCR_TAMP3TS_Msk -#define RTC_TAMPTSCR_TAMP4TS_Pos (3U) +#define RTC_TAMPTSCR_TAMP4TS_Pos (3UL) #define RTC_TAMPTSCR_TAMP4TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP4TS_Pos) /*!< 0x00000008 */ #define RTC_TAMPTSCR_TAMP4TS RTC_TAMPTSCR_TAMP4TS_Msk -#define RTC_TAMPTSCR_TAMP5TS_Pos (4U) +#define RTC_TAMPTSCR_TAMP5TS_Pos (4UL) #define RTC_TAMPTSCR_TAMP5TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP5TS_Pos) /*!< 0x00000010 */ #define RTC_TAMPTSCR_TAMP5TS RTC_TAMPTSCR_TAMP5TS_Msk -#define RTC_TAMPTSCR_ITAMPTS_Pos (16U) +#define RTC_TAMPTSCR_ITAMPTS_Pos (16UL) #define RTC_TAMPTSCR_ITAMPTS_Msk (0x1UL << RTC_TAMPTSCR_ITAMPTS_Pos) /*!< 0x00010000 */ #define RTC_TAMPTSCR_ITAMPTS RTC_TAMPTSCR_ITAMPTS_Msk /******************** Bits definition for RTC_TSIDR register ******************/ -#define RTC_TSIDR_TSID_Pos (0U) +#define RTC_TSIDR_TSID_Pos (0UL) #define RTC_TSIDR_TSID_Msk (0x3FUL << RTC_TSIDR_TSID_Pos) /*!< 0x0000003F */ #define RTC_TSIDR_TSID RTC_TSIDR_TSID_Msk #define RTC_TSIDR_TSID_0 (0x1UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000001 */ @@ -14534,12 +13861,12 @@ typedef struct #define RTC_TSIDR_TSID_5 (0x20UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000020 */ /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -14549,49 +13876,49 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for SAI_xCR1 register *******************/ -#define SAI_xCR1_MODE_Pos (0U) +#define SAI_xCR1_MODE_Pos (0UL) #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + /******************************************************************************/ /* */ /* VREFBUF */ /* */ /******************************************************************************/ /******************* Bit definition for VREFBUF_CSR register ****************/ -#define VREFBUF_CSR_ENVR_Pos (0U) +#define VREFBUF_CSR_ENVR_Pos (0UL) #define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ #define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -14775,85 +14059,85 @@ typedef struct #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -14862,124 +14146,124 @@ typedef struct #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Pos (5UL) #define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_TAMPTSCR register ******************/ -#define RTC_TAMPTSCR_TAMP1TS_Pos (0U) +#define RTC_TAMPTSCR_TAMP1TS_Pos (0UL) #define RTC_TAMPTSCR_TAMP1TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP1TS_Pos) /*!< 0x00000001 */ #define RTC_TAMPTSCR_TAMP1TS RTC_TAMPTSCR_TAMP1TS_Msk -#define RTC_TAMPTSCR_TAMP2TS_Pos (1U) +#define RTC_TAMPTSCR_TAMP2TS_Pos (1UL) #define RTC_TAMPTSCR_TAMP2TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP2TS_Pos) /*!< 0x00000002 */ #define RTC_TAMPTSCR_TAMP2TS RTC_TAMPTSCR_TAMP2TS_Msk -#define RTC_TAMPTSCR_TAMP3TS_Pos (2U) +#define RTC_TAMPTSCR_TAMP3TS_Pos (2UL) #define RTC_TAMPTSCR_TAMP3TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP3TS_Pos) /*!< 0x00000004 */ #define RTC_TAMPTSCR_TAMP3TS RTC_TAMPTSCR_TAMP3TS_Msk -#define RTC_TAMPTSCR_TAMP4TS_Pos (3U) +#define RTC_TAMPTSCR_TAMP4TS_Pos (3UL) #define RTC_TAMPTSCR_TAMP4TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP4TS_Pos) /*!< 0x00000008 */ #define RTC_TAMPTSCR_TAMP4TS RTC_TAMPTSCR_TAMP4TS_Msk -#define RTC_TAMPTSCR_TAMP5TS_Pos (4U) +#define RTC_TAMPTSCR_TAMP5TS_Pos (4UL) #define RTC_TAMPTSCR_TAMP5TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP5TS_Pos) /*!< 0x00000010 */ #define RTC_TAMPTSCR_TAMP5TS RTC_TAMPTSCR_TAMP5TS_Msk -#define RTC_TAMPTSCR_ITAMPTS_Pos (16U) +#define RTC_TAMPTSCR_ITAMPTS_Pos (16UL) #define RTC_TAMPTSCR_ITAMPTS_Msk (0x1UL << RTC_TAMPTSCR_ITAMPTS_Pos) /*!< 0x00010000 */ #define RTC_TAMPTSCR_ITAMPTS RTC_TAMPTSCR_ITAMPTS_Msk /******************** Bits definition for RTC_TSIDR register ******************/ -#define RTC_TSIDR_TSID_Pos (0U) +#define RTC_TSIDR_TSID_Pos (0UL) #define RTC_TSIDR_TSID_Msk (0x3FUL << RTC_TSIDR_TSID_Pos) /*!< 0x0000003F */ #define RTC_TSIDR_TSID RTC_TSIDR_TSID_Msk #define RTC_TSIDR_TSID_0 (0x1UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000001 */ @@ -14990,12 +14274,12 @@ typedef struct #define RTC_TSIDR_TSID_5 (0x20UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000020 */ /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -15005,49 +14289,49 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for SAI_xCR1 register *******************/ -#define SAI_xCR1_MODE_Pos (0U) +#define SAI_xCR1_MODE_Pos (0UL) #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*! 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + /** * @brief Power Control */ @@ -1488,6 +1513,8 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; #define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0400UL) #define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0710UL) #define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0800UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A2400UL) #define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A8000UL) #define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A8400UL) #define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0x000AF000UL) @@ -1605,6 +1632,8 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; #define HASH_BASE_S (AHB2PERIPH_BASE_S + 0x000A0400UL) #define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0x000A0710UL) #define RNG_BASE_S (AHB2PERIPH_BASE_S + 0x000A0800UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0x000A2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0x000A2400UL) #define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0x000A8000UL) #define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0x000A8400UL) #define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0x000AF000UL) @@ -1620,7 +1649,6 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; /*!< USB PMA SIZE */ #define USB_DRD_PMA_SIZE (2048U) /*!< USB PMA Size 2Kbyte */ -#if defined (CPU_IN_SECURE_STATE) /*!< Root Secure Service Library */ /************ RSSLIB SAU system Flash region definition constants *************/ #define RSSLIB_SYS_FLASH_NS_PFUNC_START 0x0BF99040UL @@ -1635,11 +1663,11 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; #define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) /*!< HDP Area constant definition */ -#define RSSLIB_HDP_AREA_Pos 0U +#define RSSLIB_HDP_AREA_Pos 0UL #define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) -#define RSSLIB_HDP_AREA1_Pos 0U +#define RSSLIB_HDP_AREA1_Pos 0UL #define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) -#define RSSLIB_HDP_AREA2_Pos 1U +#define RSSLIB_HDP_AREA2_Pos 1UL #define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) #define RSSLIB_HDPEXT_CLOSE_BOUNDARY_OPEN 0xC9C9C9C9UL /* Access to HDPx extension area and HDPx area denied but HDPx_EXT (in FLASH_HDPEXTR) increment allowed at any time */ #define RSSLIB_HDPEXT_CLOSE_BOUNDARY_LOCK 0xD6D6D6D6UL /* Access to HDPx extension area and HDPx area denied. Update of HDPx_EXT size is not possible anymore */ @@ -1699,7 +1727,6 @@ typedef struct NSC_pFuncTypeDef NSC; S_pFuncTypeDef S; }RSSLIB_pFunc_TypeDef; -#endif /* CPU_IN_SECURE_STATE */ /* * Certificate address description @@ -1792,6 +1819,7 @@ typedef struct #define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) #define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) #define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) #define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) #define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) #define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) @@ -1889,6 +1917,7 @@ typedef struct #define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) #define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) #define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) #define PWR_S ((PWR_TypeDef *) PWR_BASE_S) #define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) #define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) @@ -2048,6 +2077,9 @@ typedef struct #define OPAMP2_BASE OPAMP2_BASE_S #define OPAMP12_COMMON OPAMP12_COMMON_S #define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S #define PWR PWR_S #define PWR_BASE PWR_BASE_S #define RAMCFG_SRAM1 RAMCFG_SRAM1_S @@ -2239,6 +2271,9 @@ typedef struct #define OPAMP2_BASE OPAMP2_BASE_NS #define OPAMP12_COMMON OPAMP12_COMMON_NS #define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS #define PWR PWR_NS #define PWR_BASE PWR_BASE_NS #define RAMCFG_SRAM1 RAMCFG_SRAM1_NS @@ -2334,124 +2369,124 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register *******************/ -#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Pos (0UL) #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ -#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Pos (1UL) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ -#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Pos (2UL) #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ -#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Pos (3UL) #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ -#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Pos (4UL) #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ -#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Pos (5UL) #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ -#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Pos (6UL) #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ -#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Pos (7UL) #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ -#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Pos (8UL) #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ -#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Pos (9UL) #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ -#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Pos (10UL) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ -#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Pos (12UL) #define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ #define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC internal voltage regulator output ready flag */ /******************** Bit definition for ADC_IER register *******************/ -#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Pos (0UL) #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ -#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Pos (1UL) #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ -#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Pos (2UL) #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ -#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Pos (3UL) #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ -#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Pos (4UL) #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ -#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Pos (5UL) #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ -#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Pos (6UL) #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ -#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Pos (7UL) #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ -#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Pos (8UL) #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ -#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Pos (9UL) #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ -#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Pos (10UL) #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ -#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Pos (12UL) #define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ #define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC internal voltage regulator interrupt*/ /******************** Bit definition for ADC_CR register ********************/ -#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Pos (0UL) #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ -#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Pos (1UL) #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ -#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Pos (2UL) #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ -#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Pos (3UL) #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ -#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Pos (4UL) #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ -#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Pos (5UL) #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ -#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Pos (28UL) #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC internal voltage regulator */ -#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Pos (29UL) #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ -#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Pos (31UL) #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR1 register ******************/ -#define ADC_CFGR1_DMNGT_Pos (0U) +#define ADC_CFGR1_DMNGT_Pos (0UL) #define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ #define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC data management configuration */ #define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ #define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ -#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Pos (2UL) #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ #define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ #define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ -#define ADC_CFGR1_EXTSEL_Pos (5U) +#define ADC_CFGR1_EXTSEL_Pos (5UL) #define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ #define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ @@ -2460,55 +2495,55 @@ typedef struct #define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ -#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Pos (10UL) #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ -#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Pos (12UL) #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ -#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Pos (13UL) #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ -#define ADC_CFGR1_AUTDLY_Pos (14U) +#define ADC_CFGR1_AUTDLY_Pos (14UL) #define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC low power auto wait */ -#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Pos (16UL) #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ -#define ADC_CFGR1_DISCNUM_Pos (17U) +#define ADC_CFGR1_DISCNUM_Pos (17UL) #define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ #define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ #define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ #define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ -#define ADC_CFGR1_JDISCEN_Pos (20U) +#define ADC_CFGR1_JDISCEN_Pos (20UL) #define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ -#define ADC_CFGR1_JQM_Pos (21U) +#define ADC_CFGR1_JQM_Pos (21UL) #define ADC_CFGR1_JQM_Msk (0x1UL << ADC_CFGR1_JQM_Pos) /*!< 0x00200000 */ #define ADC_CFGR1_JQM ADC_CFGR1_JQM_Msk /*!< ADC group injected contexts queue mode */ -#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Pos (22UL) #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ -#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Pos (23UL) #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ -#define ADC_CFGR1_JAWD1EN_Pos (24U) +#define ADC_CFGR1_JAWD1EN_Pos (24UL) #define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ -#define ADC_CFGR1_JAUTO_Pos (25U) +#define ADC_CFGR1_JAUTO_Pos (25UL) #define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ -#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Pos (26UL) #define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ #define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ @@ -2517,19 +2552,19 @@ typedef struct #define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ #define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ -#define ADC_CFGR1_JQDIS_Pos (31U) +#define ADC_CFGR1_JQDIS_Pos (31UL) #define ADC_CFGR1_JQDIS_Msk (0x1UL << ADC_CFGR1_JQDIS_Pos) /*!< 0x80000000 */ #define ADC_CFGR1_JQDIS ADC_CFGR1_JQDIS_Msk /*!< ADC group injected contexts queue disable */ /******************** Bit definition for ADC_CFGR2 register *****************/ -#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Pos (0UL) #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ -#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Pos (1UL) #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ -#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Pos (5UL) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ @@ -2537,26 +2572,26 @@ typedef struct #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ -#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Pos (9UL) #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ -#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Pos (10UL) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ -#define ADC_CFGR2_BULB_Pos (13U) +#define ADC_CFGR2_BULB_Pos (13UL) #define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ #define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC bulb sampling mode */ -#define ADC_CFGR2_SWTRIG_Pos (14U) +#define ADC_CFGR2_SWTRIG_Pos (14UL) #define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC software trigger bit for sampling time control trigger mode */ -#define ADC_CFGR2_SMPTRIG_Pos (15U) +#define ADC_CFGR2_SMPTRIG_Pos (15UL) #define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ #define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC sampling time control trigger mode */ -#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Pos (16UL) #define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ #define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ @@ -2570,11 +2605,11 @@ typedef struct #define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ #define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ -#define ADC_CFGR2_LFTRIG_Pos (27U) +#define ADC_CFGR2_LFTRIG_Pos (27UL) #define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ #define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low-frequency trigge */ -#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Pos (28UL) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ #define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC left shift factor */ #define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ @@ -2583,70 +2618,70 @@ typedef struct #define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_SMPR1 register *****************/ -#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Pos (0UL) #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ -#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Pos (3UL) #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ -#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Pos (6UL) #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ -#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Pos (9UL) #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ -#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Pos (12UL) #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ -#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Pos (15UL) #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ -#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Pos (18UL) #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ -#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Pos (21UL) #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ -#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Pos (24UL) #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ -#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Pos (27UL) #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ @@ -2654,70 +2689,70 @@ typedef struct #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ /******************** Bit definition for ADC_SMPR2 register *****************/ -#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Pos (0UL) #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ -#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Pos (3UL) #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ -#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Pos (6UL) #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ -#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Pos (9UL) #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ -#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Pos (12UL) #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ -#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Pos (15UL) #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ -#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Pos (18UL) #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ -#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Pos (21UL) #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ -#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Pos (24UL) #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ -#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Pos (27UL) #define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ #define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ #define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ @@ -2725,7 +2760,7 @@ typedef struct #define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ /******************** Bit definition for ADC_PCSEL register *****************/ -#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Pos (0UL) #define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ #define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC channel preselection */ #define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ @@ -2749,7 +2784,7 @@ typedef struct #define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_SQR1 register ******************/ -#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Pos (0UL) #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ @@ -2757,7 +2792,7 @@ typedef struct #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ -#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Pos (6UL) #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ @@ -2766,7 +2801,7 @@ typedef struct #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ -#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Pos (12UL) #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ @@ -2775,7 +2810,7 @@ typedef struct #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ -#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Pos (18UL) #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ @@ -2784,7 +2819,7 @@ typedef struct #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ #define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ -#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Pos (24UL) #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ @@ -2794,7 +2829,7 @@ typedef struct #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ******************/ -#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Pos (0UL) #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ @@ -2803,7 +2838,7 @@ typedef struct #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ -#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Pos (6UL) #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ @@ -2812,7 +2847,7 @@ typedef struct #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ -#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Pos (12UL) #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ @@ -2821,7 +2856,7 @@ typedef struct #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ -#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Pos (18UL) #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ @@ -2830,7 +2865,7 @@ typedef struct #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ -#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Pos (24UL) #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ @@ -2840,7 +2875,7 @@ typedef struct #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ******************/ -#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Pos (0UL) #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ @@ -2849,7 +2884,7 @@ typedef struct #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ -#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Pos (6UL) #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ @@ -2858,7 +2893,7 @@ typedef struct #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ -#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Pos (12UL) #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ @@ -2867,7 +2902,7 @@ typedef struct #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ -#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Pos (18UL) #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ @@ -2876,7 +2911,7 @@ typedef struct #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ -#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Pos (24UL) #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ @@ -2886,7 +2921,7 @@ typedef struct #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ******************/ -#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Pos (0UL) #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ @@ -2895,7 +2930,7 @@ typedef struct #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ -#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Pos (6UL) #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ @@ -2905,7 +2940,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Pos (0UL) #define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ #define ADC_DR_RDATA_0 (0x00000001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ @@ -2942,13 +2977,13 @@ typedef struct #define ADC_DR_RDATA_31 (0x80000000UL << ADC_DR_RDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JSQR register ******************/ -#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Pos (0UL) #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ -#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Pos (2UL) #define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ #define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ @@ -2957,13 +2992,13 @@ typedef struct #define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ -#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Pos (7UL) #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ -#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Pos (9UL) #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ @@ -2972,7 +3007,7 @@ typedef struct #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ -#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Pos (15UL) #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ @@ -2981,7 +3016,7 @@ typedef struct #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ -#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Pos (21UL) #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ @@ -2990,7 +3025,7 @@ typedef struct #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ -#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Pos (27UL) #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ @@ -3000,19 +3035,19 @@ typedef struct #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFCFGR1 register ***************/ -#define ADC_OFCFGR1_POSOFF_Pos (24U) +#define ADC_OFCFGR1_POSOFF_Pos (24UL) #define ADC_OFCFGR1_POSOFF_Msk (0x01UL << ADC_OFCFGR1_POSOFF_Pos) /*!< 0x01000000 */ #define ADC_OFCFGR1_POSOFF ADC_OFCFGR1_POSOFF_Msk /*!< ADC offset instance 1 positive offset enable */ -#define ADC_OFCFGR1_USAT_Pos (25U) +#define ADC_OFCFGR1_USAT_Pos (25UL) #define ADC_OFCFGR1_USAT_Msk (0x01UL << ADC_OFCFGR1_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFCFGR1_USAT ADC_OFCFGR1_USAT_Msk /*!< ADC offset instance 1 unsigned saturation value */ -#define ADC_OFCFGR1_SSAT_Pos (26U) +#define ADC_OFCFGR1_SSAT_Pos (26UL) #define ADC_OFCFGR1_SSAT_Msk (0x01UL << ADC_OFCFGR1_SSAT_Pos) /*!< 0x04000000 */ #define ADC_OFCFGR1_SSAT ADC_OFCFGR1_SSAT_Msk /*!< ADC offset instance 1 signed satuaration enable */ -#define ADC_OFCFGR1_OFFSET_CH_Pos (27U) +#define ADC_OFCFGR1_OFFSET_CH_Pos (27UL) #define ADC_OFCFGR1_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0xF8000000 */ #define ADC_OFCFGR1_OFFSET_CH ADC_OFCFGR1_OFFSET_CH_Msk /*!< ADC offset instance 1 channel selection */ #define ADC_OFCFGR1_OFFSET_CH_0 (0x01UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x08000000 */ @@ -3022,19 +3057,19 @@ typedef struct #define ADC_OFCFGR1_OFFSET_CH_4 (0x05UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFCFGR2 register ***************/ -#define ADC_OFCFGR2_POSOFF_Pos (24U) +#define ADC_OFCFGR2_POSOFF_Pos (24UL) #define ADC_OFCFGR2_POSOFF_Msk (0x01UL << ADC_OFCFGR2_POSOFF_Pos) /*!< 0x01000000 */ #define ADC_OFCFGR2_POSOFF ADC_OFCFGR2_POSOFF_Msk /*!< ADC offset instance 2 positive offset enable */ -#define ADC_OFCFGR2_USAT_Pos (25U) +#define ADC_OFCFGR2_USAT_Pos (25UL) #define ADC_OFCFGR2_USAT_Msk (0x01UL << ADC_OFCFGR2_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFCFGR2_USAT ADC_OFCFGR2_USAT_Msk /*!< ADC offset instance 2 unsigned saturation value */ -#define ADC_OFCFGR2_SSAT_Pos (26U) +#define ADC_OFCFGR2_SSAT_Pos (26UL) #define ADC_OFCFGR2_SSAT_Msk (0x01UL << ADC_OFCFGR2_SSAT_Pos) /*!< 0x04000000 */ #define ADC_OFCFGR2_SSAT ADC_OFCFGR2_SSAT_Msk /*!< ADC offset instance 2 signed satuaration enable */ -#define ADC_OFCFGR2_OFFSET_CH_Pos (27U) +#define ADC_OFCFGR2_OFFSET_CH_Pos (27UL) #define ADC_OFCFGR2_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0xF8000000 */ #define ADC_OFCFGR2_OFFSET_CH ADC_OFCFGR2_OFFSET_CH_Msk /*!< ADC offset instance 2 channel selection */ #define ADC_OFCFGR2_OFFSET_CH_0 (0x01UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x08000000 */ @@ -3044,19 +3079,19 @@ typedef struct #define ADC_OFCFGR2_OFFSET_CH_4 (0x05UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFCFGR3 register ***************/ -#define ADC_OFCFGR3_POSOFF_Pos (24U) +#define ADC_OFCFGR3_POSOFF_Pos (24UL) #define ADC_OFCFGR3_POSOFF_Msk (0x01UL << ADC_OFCFGR3_POSOFF_Pos) /*!< 0x01000000 */ #define ADC_OFCFGR3_POSOFF ADC_OFCFGR3_POSOFF_Msk /*!< ADC offset instance 3 positive offset enable */ -#define ADC_OFCFGR3_USAT_Pos (25U) +#define ADC_OFCFGR3_USAT_Pos (25UL) #define ADC_OFCFGR3_USAT_Msk (0x01UL << ADC_OFCFGR3_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFCFGR3_USAT ADC_OFCFGR3_USAT_Msk /*!< ADC offset instance 3 unsigned saturation value */ -#define ADC_OFCFGR3_SSAT_Pos (26U) +#define ADC_OFCFGR3_SSAT_Pos (26UL) #define ADC_OFCFGR3_SSAT_Msk (0x01UL << ADC_OFCFGR3_SSAT_Pos) /*!< 0x04000000 */ #define ADC_OFCFGR3_SSAT ADC_OFCFGR3_SSAT_Msk /*!< ADC offset instance 3 signed satuaration enable */ -#define ADC_OFCFGR3_OFFSET_CH_Pos (27U) +#define ADC_OFCFGR3_OFFSET_CH_Pos (27UL) #define ADC_OFCFGR3_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0xF8000000 */ #define ADC_OFCFGR3_OFFSET_CH ADC_OFCFGR3_OFFSET_CH_Msk /*!< ADC offset instance 3 channel selection for the data offset */ #define ADC_OFCFGR3_OFFSET_CH_0 (0x01UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x08000000 */ @@ -3066,19 +3101,19 @@ typedef struct #define ADC_OFCFGR3_OFFSET_CH_4 (0x05UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFCFGR4 register ***************/ -#define ADC_OFCFGR4_POSOFF_Pos (24U) +#define ADC_OFCFGR4_POSOFF_Pos (24UL) #define ADC_OFCFGR4_POSOFF_Msk (0x01UL << ADC_OFCFGR4_POSOFF_Pos) /*!< 0x01000000 */ #define ADC_OFCFGR4_POSOFF ADC_OFCFGR4_POSOFF_Msk /*!< ADC offset instance 4 positive offset enable */ -#define ADC_OFCFGR4_USAT_Pos (25U) +#define ADC_OFCFGR4_USAT_Pos (25UL) #define ADC_OFCFGR4_USAT_Msk (0x01UL << ADC_OFCFGR4_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFCFGR4_USAT ADC_OFCFGR4_USAT_Msk /*!< ADC offset instance 4 unsigned saturation value */ -#define ADC_OFCFGR4_SSAT_Pos (26U) +#define ADC_OFCFGR4_SSAT_Pos (26UL) #define ADC_OFCFGR4_SSAT_Msk (0x01UL << ADC_OFCFGR4_SSAT_Pos) /*!< 0x04000000 */ #define ADC_OFCFGR4_SSAT ADC_OFCFGR4_SSAT_Msk /*!< ADC offset instance 4 signed satuaration enable */ -#define ADC_OFCFGR4_OFFSET_CH_Pos (27U) +#define ADC_OFCFGR4_OFFSET_CH_Pos (27UL) #define ADC_OFCFGR4_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0xF8000000 */ #define ADC_OFCFGR4_OFFSET_CH ADC_OFCFGR4_OFFSET_CH_Msk /*!< ADC offset instance 4 channel selection for the data offset */ #define ADC_OFCFGR4_OFFSET_CH_0 (0x01UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x08000000 */ @@ -3088,7 +3123,7 @@ typedef struct #define ADC_OFCFGR4_OFFSET_CH_4 (0x05UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFR1 register ******************/ -#define ADC_OFR1_OFFSET_Pos (0U) +#define ADC_OFR1_OFFSET_Pos (0UL) #define ADC_OFR1_OFFSET_Msk (0x03FFFFFUL << ADC_OFR1_OFFSET_Pos) /*!< 0x003FFFFF */ #define ADC_OFR1_OFFSET ADC_OFR1_OFFSET_Msk /*!< ADC offset instance 1 offset level */ #define ADC_OFR1_OFFSET_0 (0x0000001UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000001 */ @@ -3115,7 +3150,7 @@ typedef struct #define ADC_OFR1_OFFSET_21 (0x0200000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00200000 */ /******************** Bit definition for ADC_OFR2 register ******************/ -#define ADC_OFR2_OFFSET_Pos (0U) +#define ADC_OFR2_OFFSET_Pos (0UL) #define ADC_OFR2_OFFSET_Msk (0x03FFFFFUL << ADC_OFR2_OFFSET_Pos) /*!< 0x003FFFFF */ #define ADC_OFR2_OFFSET ADC_OFR2_OFFSET_Msk /*!< ADC offset instance 2 offset level */ #define ADC_OFR2_OFFSET_0 (0x0000001UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000001 */ @@ -3142,7 +3177,7 @@ typedef struct #define ADC_OFR2_OFFSET_21 (0x0200000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00200000 */ /******************** Bit definition for ADC_OFR3 register ******************/ -#define ADC_OFR3_OFFSET_Pos (0U) +#define ADC_OFR3_OFFSET_Pos (0UL) #define ADC_OFR3_OFFSET_Msk (0x03FFFFFUL << ADC_OFR3_OFFSET_Pos) /*!< 0x003FFFFF */ #define ADC_OFR3_OFFSET ADC_OFR3_OFFSET_Msk /*!< ADC offset instance 3 offset level */ #define ADC_OFR3_OFFSET_0 (0x0000001UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000001 */ @@ -3169,7 +3204,7 @@ typedef struct #define ADC_OFR3_OFFSET_21 (0x0200000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00200000 */ /******************** Bit definition for ADC_OFR4 register ******************/ -#define ADC_OFR4_OFFSET_Pos (0U) +#define ADC_OFR4_OFFSET_Pos (0UL) #define ADC_OFR4_OFFSET_Msk (0x03FFFFFUL << ADC_OFR4_OFFSET_Pos) /*!< 0x003FFFFF */ #define ADC_OFR4_OFFSET ADC_OFR4_OFFSET_Msk /*!< ADC offset instance 4 offset level */ #define ADC_OFR4_OFFSET_0 (0x0000001UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000001 */ @@ -3196,7 +3231,7 @@ typedef struct #define ADC_OFR4_OFFSET_21 (0x0200000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00200000 */ /******************** Bit definition for ADC_GCOMP register *****************/ -#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) #define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ #define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< Gain compensation coefficient */ #define ADC_GCOMP_GCOMPCOEFF_0 (0x0001UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000001 */ @@ -3214,12 +3249,12 @@ typedef struct #define ADC_GCOMP_GCOMPCOEFF_12 (0x1000UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00001000 */ #define ADC_GCOMP_GCOMPCOEFF_13 (0x2000UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00002000 */ -#define ADC_GCOMP_GCOMP_Pos (31U) +#define ADC_GCOMP_GCOMP_Pos (31UL) #define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x80000000 */ #define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< Gain compensation mode */ /******************** Bit definition for ADC_JDR1 register ******************/ -#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Pos (0UL) #define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ #define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ @@ -3256,7 +3291,7 @@ typedef struct #define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JDR2 register ********************/ -#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Pos (0UL) #define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ #define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ @@ -3293,7 +3328,7 @@ typedef struct #define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JDR3 register ********************/ -#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Pos (0UL) #define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ #define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ @@ -3330,7 +3365,7 @@ typedef struct #define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JDR4 register ********************/ -#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Pos (0UL) #define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ #define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ @@ -3367,7 +3402,7 @@ typedef struct #define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_AWD2CR register ****************/ -#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Pos (0UL) #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ @@ -3391,7 +3426,7 @@ typedef struct #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ -#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Pos (0UL) #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ @@ -3415,7 +3450,7 @@ typedef struct #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_AWD1TR_LT register *************/ -#define ADC_AWD1LTR_LTR_Pos (0U) +#define ADC_AWD1LTR_LTR_Pos (0UL) #define ADC_AWD1LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD1LTR_LTR_Pos) /*!< 0x007FFFFF */ #define ADC_AWD1LTR_LTR ADC_AWD1LTR_LTR_Msk /*!< ADC analog watchdog 1 threshold low */ #define ADC_AWD1LTR_LTR_0 (0x000001UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000001 */ @@ -3443,7 +3478,7 @@ typedef struct #define ADC_AWD1LTR_LTR_22 (0x400000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00400000 */ /******************** Bit definition for ADC_AWD1TR_HT register *******************/ -#define ADC_AWD1HTR_HTR_Pos (0U) +#define ADC_AWD1HTR_HTR_Pos (0UL) #define ADC_AWD1HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD1HTR_HTR_Pos) /*!< 0x007FFFFF */ #define ADC_AWD1HTR_HTR ADC_AWD1HTR_HTR_Msk /*!< ADC analog watchdog 1 threshold high */ #define ADC_AWD1HTR_HTR_0 (0x000001UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000001 */ @@ -3470,7 +3505,7 @@ typedef struct #define ADC_AWD1HTR_HTR_21 (0x200000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00200000 */ #define ADC_AWD1HTR_HTR_22 (0x400000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00400000 */ -#define ADC_AWD1HTR_AWDFILT_Pos (29U) +#define ADC_AWD1HTR_AWDFILT_Pos (29UL) #define ADC_AWD1HTR_AWDFILT_Msk (0x7UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000007 */ #define ADC_AWD1HTR_AWDFILT ADC_AWD1HTR_AWDFILT_Msk /*!< ADC analog watchdog 1 filtering */ #define ADC_AWD1HTR_AWDFILT_0 (0x000001UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000001 */ @@ -3478,7 +3513,7 @@ typedef struct #define ADC_AWD1HTR_AWDFILT_2 (0x000004UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000004 */ /******************** Bit definition for ADC_AWD2TR_LT register *******************/ -#define ADC_AWD2LTR_LTR_Pos (0U) +#define ADC_AWD2LTR_LTR_Pos (0UL) #define ADC_AWD2LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD2LTR_LTR_Pos) /*!< 0x007FFFFF */ #define ADC_AWD2LTR_LTR ADC_AWD2LTR_LTR_Msk /*!< ADC analog watchdog 2 threshold low */ #define ADC_AWD2LTR_LTR_0 (0x000001UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000001 */ @@ -3506,7 +3541,7 @@ typedef struct #define ADC_AWD2LTR_LTR_22 (0x400000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00400000 */ /******************** Bit definition for ADC_AWD2TR_HT register *******************/ -#define ADC_AWD2HTR_HTR_Pos (0U) +#define ADC_AWD2HTR_HTR_Pos (0UL) #define ADC_AWD2HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD2HTR_HTR_Pos) /*!< 0x007FFFFF */ #define ADC_AWD2HTR_HTR ADC_AWD2HTR_HTR_Msk /*!< ADC analog watchdog 2 threshold high */ #define ADC_AWD2HTR_HTR_0 (0x000001UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000001 */ @@ -3534,7 +3569,7 @@ typedef struct #define ADC_AWD2HTR_HTR_22 (0x400000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00400000 */ /******************** Bit definition for ADC_AWD3TR_LT register *******************/ -#define ADC_AWD3LTR_LTR_Pos (0U) +#define ADC_AWD3LTR_LTR_Pos (0UL) #define ADC_AWD3LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD3LTR_LTR_Pos) /*!< 0x007FFFFF */ #define ADC_AWD3LTR_LTR ADC_AWD3LTR_LTR_Msk /*!< ADC analog watchdog 3 threshold low */ #define ADC_AWD3LTR_LTR_0 (0x000001UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000001 */ @@ -3562,7 +3597,7 @@ typedef struct #define ADC_AWD3LTR_LTR_22 (0x400000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00400000 */ /******************** Bit definition for ADC_AWD3TR_HT register *******************/ -#define ADC_AWD3HTR_HTR_Pos (0U) +#define ADC_AWD3HTR_HTR_Pos (0UL) #define ADC_AWD3HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD3HTR_HTR_Pos) /*!< 0x007FFFFF */ #define ADC_AWD3HTR_HTR ADC_AWD3HTR_HTR_Msk /*!< ADC analog watchdog 3 threshold high */ #define ADC_AWD3HTR_HTR_0 (0x000001UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000001 */ @@ -3589,34 +3624,9 @@ typedef struct #define ADC_AWD3HTR_HTR_21 (0x200000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00200000 */ #define ADC_AWD3HTR_HTR_22 (0x400000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00400000 */ -/******************** Bit definition for ADC_DIFSEL register ****************/ -#define ADC_DIFSEL_DIFSEL_Pos (0U) -#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ -#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode selection */ -#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ -#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ -#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ -#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ -#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ -#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ -#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ -#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ -#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ -#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ -#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ -#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ -#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ -#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ -#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ -#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ -#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ -#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ -#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ -#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ - /******************** Bit definition for ADC_CALFACT register ***************/ -#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Pos (0UL) #define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ #define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ #define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ @@ -3632,88 +3642,88 @@ typedef struct /******************** Bit definition for ADC_OR option register ***************/ -#define ADC_OR_VDDCOREEN_Pos (0U) +#define ADC_OR_VDDCOREEN_Pos (0UL) #define ADC_OR_VDDCOREEN_Msk (0x1UL << ADC_OR_VDDCOREEN_Pos) /*!< 0x00000004 */ #define ADC_OR_VDDCOREEN ADC_OR_VDDCOREEN_Msk /*!< ADC internal path to VDDCORE */ /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register *******************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Pos (0UL) #define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ -#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Pos (1UL) #define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ -#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Pos (2UL) #define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ -#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Pos (3UL) #define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ -#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Pos (4UL) #define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ -#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Pos (5UL) #define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ -#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Pos (6UL) #define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ -#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Pos (7UL) #define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ -#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Pos (8UL) #define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ -#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Pos (9UL) #define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ -#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Pos (10UL) #define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ -#define ADC_CSR_LDORDY_MST_Pos (12U) +#define ADC_CSR_LDORDY_MST_Pos (12UL) #define ADC_CSR_LDORDY_MST_Msk (0x1UL << ADC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ #define ADC_CSR_LDORDY_MST ADC_CSR_LDORDY_MST_Msk /*!< ADC multimode master internal voltage regulator output ready flag */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Pos (16UL) #define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Pos (17UL) #define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ -#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Pos (18UL) #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ -#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Pos (19UL) #define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ -#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Pos (20UL) #define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ -#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Pos (21UL) #define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ -#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Pos (22UL) #define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ -#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Pos (23UL) #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ -#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Pos (24UL) #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ -#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Pos (25UL) #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Pos (26UL) #define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ -#define ADC_CSR_LDORDY_SLV_Pos (28U) +#define ADC_CSR_LDORDY_SLV_Pos (28UL) #define ADC_CSR_LDORDY_SLV_Msk (0x1UL << ADC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ #define ADC_CSR_LDORDY_SLV ADC_CSR_LDORDY_SLV_Msk /*!< ADC multimode slave internal voltage regulator output ready flag */ /******************** Bit definition for ADC_CCR register *******************/ -#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Pos (0UL) #define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ #define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ @@ -3722,7 +3732,7 @@ typedef struct #define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ #define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ -#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Pos (8UL) #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ @@ -3730,13 +3740,13 @@ typedef struct #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ -#define ADC_CCR_DAMDF_Pos (14U) +#define ADC_CCR_DAMDF_Pos (14UL) #define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ #define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< ADC multimode data format */ #define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ #define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ -#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Pos (18UL) #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler */ #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ @@ -3744,29 +3754,29 @@ typedef struct #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ -#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Pos (22UL) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ -#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Pos (23UL) #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to Temperature sensor voltage enable */ -#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Pos (24UL) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ /******************** Bit definition for ADC_CDR register *******************/ -#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Pos (0UL) #define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ -#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Pos (16UL) #define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ /******************** Bit definition for ADC_CDR2 register ******************/ -#define ADC_CDR2_RDATA_ALT_Pos (0U) +#define ADC_CDR2_RDATA_ALT_Pos (0UL) #define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ #define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< ADC multimode master or slave (alternated) group regular conversion data */ @@ -3776,48 +3786,48 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Pos (0UL) #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Pos (0UL) #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ /******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Pos (0UL) #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ -#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Pos (3UL) #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ -#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Pos (5UL) #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ -#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Pos (7UL) #define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ #define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ #define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ -#define CRC_CR_RTYPE_IN_Pos (9U) +#define CRC_CR_RTYPE_IN_Pos (9UL) #define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ #define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< RTYPE_IN Reverse Type Input bit */ -#define CRC_CR_RTYPE_OUT_Pos (10U) +#define CRC_CR_RTYPE_OUT_Pos (10UL) #define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ #define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< RTYPE_OUT Reverse Type Output bit */ /******************* Bit definition for CRC_INIT register *******************/ -#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Pos (0UL) #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ /******************* Bit definition for CRC_POL register ********************/ -#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Pos (0UL) #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ @@ -3826,93 +3836,93 @@ typedef struct /* CRS Clock Recovery System */ /******************************************************************************/ /******************* Bit definition for CRS_CR register *********************/ -#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Pos (0UL) #define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ -#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Pos (1UL) #define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ -#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Pos (2UL) #define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ -#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Pos (3UL) #define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ -#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Pos (5UL) #define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ -#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Pos (6UL) #define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ -#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Pos (7UL) #define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ -#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Pos (8UL) #define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ -#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Pos (0UL) #define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ -#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Pos (16UL) #define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ -#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Pos (24UL) #define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ #define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ #define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ #define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ -#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Pos (28UL) #define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ #define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ #define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ -#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Pos (31UL) #define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ /******************* Bit definition for CRS_ISR register *********************/ -#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Pos (0UL) #define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ -#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Pos (1UL) #define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ -#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Pos (2UL) #define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ -#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Pos (3UL) #define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ -#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Pos (8UL) #define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ -#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Pos (9UL) #define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ -#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Pos (10UL) #define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ -#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Pos (15UL) #define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ -#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Pos (16UL) #define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ /******************* Bit definition for CRS_ICR register *********************/ -#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Pos (0UL) #define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ -#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Pos (1UL) #define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ -#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Pos (2UL) #define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ -#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Pos (3UL) #define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ @@ -3922,41 +3932,41 @@ typedef struct /* */ /******************************************************************************/ /*!< ****************** Bit definition for COMPx_CSR register ********************/ -#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Pos (0UL) #define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ #define COMP_CSR_EN COMP_CSR_EN_Msk /*!< COMPx enable bit */ -#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Pos (4UL) #define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00070000 */ #define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< COMPx input minus selection bit */ #define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00010000 */ #define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00020000 */ #define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00040000 */ #define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00080000 */ -#define COMP_CSR_INPSEL_Pos (8U) +#define COMP_CSR_INPSEL_Pos (8UL) #define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00100000 */ #define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< COMPx input plus selection bit */ #define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) #define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) -#define COMP_CSR_WINMODE_Pos (11U) +#define COMP_CSR_WINMODE_Pos (11UL) #define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000010 */ #define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< COMPx Windows mode selection bit */ -#define COMP_CSR_WINOUT_Pos (14U) +#define COMP_CSR_WINOUT_Pos (14UL) #define COMP_CSR_WINOUT_Msk (0x1UL << COMP_CSR_WINOUT_Pos) /*!< 0x00000008 */ #define COMP_CSR_WINOUT COMP_CSR_WINOUT_Msk /*!< COMPx polarity selection bit */ -#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Pos (15UL) #define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00000008 */ #define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< COMPx polarity selection bit */ -#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Pos (16UL) #define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00000300 */ #define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< COMPx hysteresis selection bits */ #define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00000100 */ #define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00000200 */ -#define COMP_CSR_PWRMODE_Pos (18U) +#define COMP_CSR_PWRMODE_Pos (18UL) #define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00003000 */ #define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< COMPx Power Mode of the comparator */ #define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00001000 */ #define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00002000 */ -#define COMP_CSR_BLANKSEL_Pos (20U) +#define COMP_CSR_BLANKSEL_Pos (20UL) #define COMP_CSR_BLANKSEL_Msk (0x1FUL << COMP_CSR_BLANKSEL_Pos) /*!< 0x0F000000 */ #define COMP_CSR_BLANKSEL COMP_CSR_BLANKSEL_Msk /*!< COMPx blanking source selection bits */ #define COMP_CSR_BLANKSEL_0 (0x1UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ @@ -3964,10 +3974,11 @@ typedef struct #define COMP_CSR_BLANKSEL_2 (0x4UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x04000000 */ #define COMP_CSR_BLANKSEL_3 (0x8UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x08000000 */ #define COMP_CSR_BLANKSEL_4 (0x10UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ -#define COMP_CSR_VALUE_Pos (30U) +#define COMP2_CSR_BLANKSEL_2 COMP_CSR_BLANKSEL_2 /*!< COMP2 blanking source selection bit 2 */ +#define COMP_CSR_VALUE_Pos (30UL) #define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x00000001 */ #define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< COMPx enable bit */ -#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Pos (31UL) #define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ #define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< COMPx Lock Bit */ @@ -3979,277 +3990,277 @@ typedef struct #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ /******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Pos (0UL) #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -15221,85 +15334,85 @@ typedef struct #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -15308,124 +15421,124 @@ typedef struct #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Pos (5UL) #define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_TAMPTSCR register ******************/ -#define RTC_TAMPTSCR_TAMP1TS_Pos (0U) +#define RTC_TAMPTSCR_TAMP1TS_Pos (0UL) #define RTC_TAMPTSCR_TAMP1TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP1TS_Pos) /*!< 0x00000001 */ #define RTC_TAMPTSCR_TAMP1TS RTC_TAMPTSCR_TAMP1TS_Msk -#define RTC_TAMPTSCR_TAMP2TS_Pos (1U) +#define RTC_TAMPTSCR_TAMP2TS_Pos (1UL) #define RTC_TAMPTSCR_TAMP2TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP2TS_Pos) /*!< 0x00000002 */ #define RTC_TAMPTSCR_TAMP2TS RTC_TAMPTSCR_TAMP2TS_Msk -#define RTC_TAMPTSCR_TAMP3TS_Pos (2U) +#define RTC_TAMPTSCR_TAMP3TS_Pos (2UL) #define RTC_TAMPTSCR_TAMP3TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP3TS_Pos) /*!< 0x00000004 */ #define RTC_TAMPTSCR_TAMP3TS RTC_TAMPTSCR_TAMP3TS_Msk -#define RTC_TAMPTSCR_TAMP4TS_Pos (3U) +#define RTC_TAMPTSCR_TAMP4TS_Pos (3UL) #define RTC_TAMPTSCR_TAMP4TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP4TS_Pos) /*!< 0x00000008 */ #define RTC_TAMPTSCR_TAMP4TS RTC_TAMPTSCR_TAMP4TS_Msk -#define RTC_TAMPTSCR_TAMP5TS_Pos (4U) +#define RTC_TAMPTSCR_TAMP5TS_Pos (4UL) #define RTC_TAMPTSCR_TAMP5TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP5TS_Pos) /*!< 0x00000010 */ #define RTC_TAMPTSCR_TAMP5TS RTC_TAMPTSCR_TAMP5TS_Msk -#define RTC_TAMPTSCR_ITAMPTS_Pos (16U) +#define RTC_TAMPTSCR_ITAMPTS_Pos (16UL) #define RTC_TAMPTSCR_ITAMPTS_Msk (0x1UL << RTC_TAMPTSCR_ITAMPTS_Pos) /*!< 0x00010000 */ #define RTC_TAMPTSCR_ITAMPTS RTC_TAMPTSCR_ITAMPTS_Msk /******************** Bits definition for RTC_TSIDR register ******************/ -#define RTC_TSIDR_TSID_Pos (0U) +#define RTC_TSIDR_TSID_Pos (0UL) #define RTC_TSIDR_TSID_Msk (0x3FUL << RTC_TSIDR_TSID_Pos) /*!< 0x0000003F */ #define RTC_TSIDR_TSID RTC_TSIDR_TSID_Msk #define RTC_TSIDR_TSID_0 (0x1UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000001 */ @@ -15436,12 +15549,12 @@ typedef struct #define RTC_TSIDR_TSID_5 (0x20UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000020 */ /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -15451,49 +15564,49 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for SAI_xCR1 register *******************/ -#define SAI_xCR1_MODE_Pos (0U) +#define SAI_xCR1_MODE_Pos (0UL) #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + /******************************************************************************/ /* */ /* VREFBUF */ /* */ /******************************************************************************/ /******************* Bit definition for VREFBUF_CSR register ****************/ -#define VREFBUF_CSR_ENVR_Pos (0U) +#define VREFBUF_CSR_ENVR_Pos (0UL) #define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ #define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -15677,85 +15747,85 @@ typedef struct #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -15764,124 +15834,124 @@ typedef struct #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Pos (5UL) #define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_TAMPTSCR register ******************/ -#define RTC_TAMPTSCR_TAMP1TS_Pos (0U) +#define RTC_TAMPTSCR_TAMP1TS_Pos (0UL) #define RTC_TAMPTSCR_TAMP1TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP1TS_Pos) /*!< 0x00000001 */ #define RTC_TAMPTSCR_TAMP1TS RTC_TAMPTSCR_TAMP1TS_Msk -#define RTC_TAMPTSCR_TAMP2TS_Pos (1U) +#define RTC_TAMPTSCR_TAMP2TS_Pos (1UL) #define RTC_TAMPTSCR_TAMP2TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP2TS_Pos) /*!< 0x00000002 */ #define RTC_TAMPTSCR_TAMP2TS RTC_TAMPTSCR_TAMP2TS_Msk -#define RTC_TAMPTSCR_TAMP3TS_Pos (2U) +#define RTC_TAMPTSCR_TAMP3TS_Pos (2UL) #define RTC_TAMPTSCR_TAMP3TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP3TS_Pos) /*!< 0x00000004 */ #define RTC_TAMPTSCR_TAMP3TS RTC_TAMPTSCR_TAMP3TS_Msk -#define RTC_TAMPTSCR_TAMP4TS_Pos (3U) +#define RTC_TAMPTSCR_TAMP4TS_Pos (3UL) #define RTC_TAMPTSCR_TAMP4TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP4TS_Pos) /*!< 0x00000008 */ #define RTC_TAMPTSCR_TAMP4TS RTC_TAMPTSCR_TAMP4TS_Msk -#define RTC_TAMPTSCR_TAMP5TS_Pos (4U) +#define RTC_TAMPTSCR_TAMP5TS_Pos (4UL) #define RTC_TAMPTSCR_TAMP5TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP5TS_Pos) /*!< 0x00000010 */ #define RTC_TAMPTSCR_TAMP5TS RTC_TAMPTSCR_TAMP5TS_Msk -#define RTC_TAMPTSCR_ITAMPTS_Pos (16U) +#define RTC_TAMPTSCR_ITAMPTS_Pos (16UL) #define RTC_TAMPTSCR_ITAMPTS_Msk (0x1UL << RTC_TAMPTSCR_ITAMPTS_Pos) /*!< 0x00010000 */ #define RTC_TAMPTSCR_ITAMPTS RTC_TAMPTSCR_ITAMPTS_Msk /******************** Bits definition for RTC_TSIDR register ******************/ -#define RTC_TSIDR_TSID_Pos (0U) +#define RTC_TSIDR_TSID_Pos (0UL) #define RTC_TSIDR_TSID_Msk (0x3FUL << RTC_TSIDR_TSID_Pos) /*!< 0x0000003F */ #define RTC_TSIDR_TSID RTC_TSIDR_TSID_Msk #define RTC_TSIDR_TSID_0 (0x1UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000001 */ @@ -15892,12 +15962,12 @@ typedef struct #define RTC_TSIDR_TSID_5 (0x20UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000020 */ /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -15907,49 +15977,49 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for SAI_xCR1 register *******************/ -#define SAI_xCR1_MODE_Pos (0U) +#define SAI_xCR1_MODE_Pos (0UL) #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p4 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32u3xx.h" /*!< STM32U3xx System */ + + +/* ================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================================================== */ +/** @addtogroup STM32U3xx_peripherals + * @{ + */ + +/** + * @brief ADC Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC channel preselection register, Address offset: 0x1C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + __IO uint32_t OFCFGR1; /*!< ADC offset configuration register 1, Address offset: 0x50 */ + __IO uint32_t OFCFGR2; /*!< ADC offset configuration register 2, Address offset: 0x54 */ + __IO uint32_t OFCFGR3; /*!< ADC offset configuration register 3, Address offset: 0x58 */ + __IO uint32_t OFCFGR4; /*!< ADC offset configuration register 4, Address offset: 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ + uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x90 */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + __IO uint32_t AWD1LTR; /*!< ADC analog watchdog 1 low threshold register, Address offset: 0xA8 */ + __IO uint32_t AWD1HTR; /*!< ADC analog watchdog 1 high threshold register, Address offset: 0xAC */ + __IO uint32_t AWD2LTR; /*!< ADC analog watchdog 2 low threshold register, Address offset: 0xB0 */ + __IO uint32_t AWD2HTR; /*!< ADC analog watchdog 2 high threshold register, Address offset: 0xB4 */ + __IO uint32_t AWD3LTR; /*!< ADC analog watchdog 3 low threshold register, Address offset: 0xB8 */ + __IO uint32_t AWD3HTR; /*!< ADC analog watchdog 3 high threshold register, Address offset: 0xBC */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xC4 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0xC8 */ + __IO uint32_t OR; /*!< ADC option register, Address offset: 0xD0 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for dual mode 32-bit, Address offset: 0x310 */ +} ADC_Common_TypeDef; + + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control/status register , Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1LFZR; /*!< Debug MCU APB1L freeze register, Address offset: 0x08 */ + __IO uint32_t APB1HFZR; /*!< Debug MCU APB1H freeze register, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x18 - 0x20 */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2[54]; /*!< Reserved, 0x24 - 0xFC */ + __IO uint32_t SR; /*!< Debug MCU status register, Address offset: 0xFC */ + __IO uint32_t DGB_AUTH_HOST; /*!< Debug MCU debug host authentication register, Address offset: 0x100 */ + __IO uint32_t DGB_AUTH_DEVICE; /*!< Debug MCU debug device authentication register, Address offset: 0x104 */ + uint32_t RESERVED3[946]; /*!< Reserved, 0x108 - 0xFD0 */ + __IO uint32_t PIDR4; /*!< Debug MCU CoreSight peripheral identity register 4, Address offset: 0xFD0 */ + __IO uint32_t PIDR0; /*!< Debug MCU CoreSight peripheral identity register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU CoreSight peripheral identity register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU CoreSight peripheral identity register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU CoreSight peripheral identity register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU CoreSight component identity register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU CoreSight component identity register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU CoreSight component identity register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU CoreSight component identity register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @ brief Delay Block + */ +typedef struct +{ + __IO uint32_t CR; /*!< Delay Block Control Register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< Delay Block Configuration Register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128]; /*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58]; /*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t PDKEY1R; /*!< FLASH bank 1 power-down key register, Address offset: 0x18 */ + __IO uint32_t PDKEY2R; /*!< FLASH bank 2 power-down key register, Address offset: 0x1C */ + __IO uint32_t SR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t CR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCCR; /*!< FLASH ECC correction register, Address offset: 0x30 */ + __IO uint32_t ECCDR; /*!< FLASH ECC detection register, Address offset: 0x34 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x38 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t BOOT0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t BOOT1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SBOOT0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ + __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ + __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ + __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ + __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ + __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x70-0x7C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ + __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0x84 */ + __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0x88 */ + __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0x8C */ + uint32_t RESERVED5[4]; /*!< Reserved, Address offset: 0x90-0x9C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ + __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0xA4 */ + __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0xA8 */ + __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0xAC */ + uint32_t RESERVED6[4]; /*!< Reserved, Address offset: 0xB0-0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + __IO uint32_t SECHDPEXTR; /*!< FLASH HDP extension register, Address offset: 0xC8 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0xCC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ + __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xD4 */ + __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xD8 */ + __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xDC */ + uint32_t RESERVED8[4]; /*!< Reserved, Address offset: 0xE0-0xEC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ + __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0xF4 */ + __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0xF8 */ + __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0xFC */ + uint32_t RESERVED9[4]; /*!< Reserved, Address offset: 0x100-0x10C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x110 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x114 */ + __IO uint32_t OEM1KEYR3; /*!< FLASH OEM1 key register 3, Address offset: 0x118 */ + __IO uint32_t OEM1KEYR4; /*!< FLASH OEM1 key register 4, Address offset: 0x11C */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x120 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x124 */ + __IO uint32_t OEM2KEYR3; /*!< FLASH OEM2 key register 3, Address offset: 0x128 */ + __IO uint32_t OEM2KEYR4; /*!< FLASH OEM2 key register 4, Address offset: 0x12C */ + __IO uint32_t OEMKEYSR; /*!< FLASH OEM key status register, Address offset: 0x130 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[12]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x12C */ + uint32_t RESERVED3[52]; /*!< Reserved3, Address offset: 0x130-0x200 */ + __IO uint32_t PRIVCFGR[12]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x22C */ +} GTZC_MPCBB_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ +} GTZC_TZSC_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + __IO uint32_t SHA3CFGR; /*!< HASH SHA-3 configuration register, Address offset: 0x28 */ + uint32_t RESERVED[51]; /*!< Reserved, 0x2C-0xF4 */ + __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[50]; /*!< HASH digest registers, Address offset: 0x310-0x3D4 */ +} HASH_DIGEST_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; /*!< I2C Autonomous mode control register, Address offset: 0x2C */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + __IO uint32_t MISR; /*!< I3C Masked Interrupt Status register, Address offset: 0x5C */ + __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief LCD + */ +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief MDF/ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED0[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t TRGISELR; /*!< MDF Trigger Input Selection Register, Address offset: 0x20 */ +} MDF_TypeDef; + +/** + * @brief MDF/ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x94-0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + uint32_t RESERVED1[1]; /*!< Reserved, 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED3[10]; /*!< Reserved, 0xC8-0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t BDCR; /*!< Power backup domain control register, Address offset: 0x24 */ + __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ + __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ + __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ + __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ + __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ + __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ + __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ + __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ + __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ + __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ + __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */ + __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ + __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ + __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ + uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x90 -> 0xAC */ + __IO uint32_t I3CPUCR1; /*!< Power I3C pull-up control register 1, Address offset: 0xB0 */ + __IO uint32_t I3CPUCR2; /*!< Power I3C pull-up control register 2, Address offset: 0xB4 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt status register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t PEAR; /*!< Parity error address register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt clear register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< Write protection register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< Write protection register 2, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t PARKEYR; /*!< Parity key register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< Erase key register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC Clock Control Register Address offset: 0x000 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x004 */ + __IO uint32_t ICSCR1; /*!< RCC Internal Clock Sources Calibration Register 1 Address offset: 0x008 */ + __IO uint32_t ICSCR2; /*!< RCC Internal Clock Sources Calibration Register 2 Address offset: 0x00C */ + __IO uint32_t ICSCR3; /*!< RCC Internal Clock Sources Calibration Register 3 Address offset: 0x010 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x014 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x018 */ + __IO uint32_t CFGR1; /*!< RCC Clock Configuration Register 1 Address offset: 0x01C */ + __IO uint32_t CFGR2; /*!< RCC Clock Configuration Register 2 Address offset: 0x020 */ + __IO uint32_t CFGR3; /*!< RCC Clock Configuration Register 3 Address offset: 0x024 */ + __IO uint32_t CFGR4; /*!< RCC Clock Configuration Register 4 Address offset: 0x028 */ + uint32_t RESERVED2[9]; /*!< Reserved Address offset: 0x02C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x050 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x054 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x058 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x05C */ + __IO uint32_t AHB1RSTR1; /*!< AHB1 Peripherals Reset Register 1 Address offset: 0x060 */ + __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x064 */ + __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x068 */ + uint32_t RESERVED4[2]; /*!< Reserved Address offset: 0x06C */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x074 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x078 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x07C */ + __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x080 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x084 */ + __IO uint32_t AHB1ENR1; /*!< AHB1 Peripherals Clock Enable Register 1 Address offset: 0x088 */ + __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x08C */ + __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x090 */ + __IO uint32_t AHB1ENR2; /*!< AHB1 Peripherals Clock Enable Register 2 Address offset: 0x094 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x098 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x09C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0x0A0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0x0A4 */ + __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0x0A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x0AC */ + __IO uint32_t AHB1SLPENR1; /*!< AHB1 Peripherals Clock Enable in Sleep Mode Register 1 Address offset: 0x0B0 */ + __IO uint32_t AHB2SLPENR1; /*!< AHB2 Peripherals Clock Enable in Sleep Mode Register 1 Address offset: 0x0B4 */ + __IO uint32_t AHB2SLPENR2; /*!< AHB2 Peripherals Clock Enable in Sleep Mode Register 2 Address offset: 0x0B8 */ + __IO uint32_t AHB1SLPENR2; /*!< AHB1 Peripherals Clock Enable in Sleep Mode Register 2 Address offset: 0x0BC */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x0C0 */ + __IO uint32_t APB1SLPENR1; /*!< APB1 Peripherals Clock Enable in Sleep Mode Register 1 Address offset: 0x0C4 */ + __IO uint32_t APB1SLPENR2; /*!< APB1 Peripherals Clock Enable in Sleep Mode Register 2 Address offset: 0x0C8 */ + __IO uint32_t APB2SLPENR; /*!< APB2 Peripherals Clock Enable in Sleep Mode Register Address offset: 0x0CC */ + __IO uint32_t APB3SLPENR; /*!< APB3 Peripherals Clock Enable in Sleep Mode Register Address offset: 0x0D0 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0x0D4 */ + __IO uint32_t AHB1STPENR1; /*!< AHB1 Peripherals Clock Enable in Stop Mode Register 1 Address offset: 0x0D8 */ + __IO uint32_t AHB2STPENR1; /*!< AHB2 Peripherals Clock Enable in Stop Mode Register 1 Address offset: 0x0DC */ + uint32_t RESERVED10[3]; /*!< Reserved Address offset: 0x0E0 */ + __IO uint32_t APB1STPENR1; /*!< APB1 Peripherals Clock Enable in Stop Mode Register 1 Address offset: 0x0EC */ + __IO uint32_t APB1STPENR2; /*!< APB1 Peripherals Clock Enable in Stop Mode Register 2 Address offset: 0x0F0 */ + __IO uint32_t APB2STPENR; /*!< APB2 Peripherals Clock Enable in Stop Mode Register Address offset: 0x0F4 */ + __IO uint32_t APB3STPENR; /*!< APB3 Peripherals Clock Enable in Stop Mode Register Address offset: 0x0F8 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0FC */ + __IO uint32_t CCIPR1; /*!< Peripherals Independent Clocks Configuration Register 1 Address offset: 0x100 */ + __IO uint32_t CCIPR2; /*!< Peripherals Independent Clocks Configuration Register 2 Address offset: 0x104 */ + __IO uint32_t CCIPR3; /*!< Peripherals Independent Clocks Configuration Register 3 Address offset: 0x108 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x10C */ + __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0x110 */ + __IO uint32_t CSR; /*!< Control & Status Register Address offset: 0x114 */ + uint32_t RESERVED13[6]; /*!< Reserved Address offset: 0x118 */ + __IO uint32_t SECCFGR; /*!< RCC Secure Configuration Register Address offset: 0x130 */ + __IO uint32_t PRIVCFGR; /*!< RCC Privilege Configuration Register Address offset: 0x134 */ +} RCC_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x60 */ + __IO uint32_t TAMPTSCR; /*!< RTC timestamp on tamper control register, Address offset: 0x64 */ + __IO uint32_t TSIDR; /*!< RTC timestamp status register, Address offset: 0x68 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + uint32_t RESERVED[17]; /*!< Reserved, Address offset: 0x00 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED2; /*!< RESERVED2, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ +} SYSCFG_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + uint32_t RESERVED1[4]; /*!< Reserved, 0x10 -- 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x44 -- 0x50 */ + __IO uint32_t RPCFGR; /*!< TAMP resources protection configuration register, Address offset: 0x54 */ + uint32_t RESERVED3[42]; /*!< Reserved, 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Touch Sensing Controller (TSC) + */ +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, 0x34-0x4C */ +} TSC_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220]; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + __IO uint32_t RESERVED0[8]; /*!< Reserved, */ + __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IO uint32_t TXBD; /*!= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* ================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* ================================================================================================================== */ +/** @addtogroup STM32U3xx_Peripheral_peripheralAddr + * @{ + */ + +/*!< Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS 0x08000000UL /*!< FLASH non-secure base address */ +#define SYSTEM_FLASH_BASE_NS 0x0BF80000UL /*!< System FLASH non-secure base address */ +#define SRAM1_BASE_NS 0x20000000UL /*!< SRAM1 non-secure base address */ +#define SRAM2_BASE_NS 0x20018000UL /*!< SRAM2 non-secure base address */ +#define SRAM3_BASE_NS 0x20028000UL /*!< SRAM3 non-secure base address */ +#define SRAM4_BASE_NS 0x20068000UL /*!< SRAM4 non-secure base address */ + +#define PERIPH_BASE_NS 0x40000000UL /*!< Peripheral non-secure base address */ +#define EXTRAM_BASE_NS 0x90000000UL /*!< External RAM base address */ +#define EPPB_BASE 0xE0040000UL /*!< External Private Peripheral Bus */ + +/*!< OTP, Engineering bytes, Option bytes defines */ +#define FLASH_OTP_BASE (SYSTEM_FLASH_BASE_NS + 0x00020000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE 0x00000200U /*!< 512 bytes OTP (one-time programmable) */ +#define FLASH_ENGY_BASE (SYSTEM_FLASH_BASE_NS + 0x00020500UL) +#define PACKAGE_BASE (FLASH_ENGY_BASE) /*!< Package data register base address */ +#define UID_BASE (FLASH_ENGY_BASE + 0x00000200UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (FLASH_ENGY_BASE + 0x000002A0UL) /*!< Flash size data register base address */ +#define UID64_BASE (FLASH_ENGY_BASE + 0x00000500UL) /*!< 64-bit Unique device Identification */ + +/*!< Memory sizes */ +/* Internal Flash size */ +#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? 0x180000U : \ + ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? 0x180000U : \ + (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U))) + +/*!< Internal SRAMs size */ +#define SRAM1_SIZE 0x00018000UL /*!< SRAM1=96k */ +#define SRAM2_SIZE 0x00010000UL /*!< SRAM2=64k */ +#define SRAM3_SIZE 0x00040000UL /*!< SRAM3=256k */ +#define SRAM4_SIZE 0x00010000UL /*!< SRAM4=64k */ + +/*!< Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00040000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x00000000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x00000400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x00000800UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x00001000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x00001400UL) +#define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x00002000UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x00002C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x00003000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x00003800UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x00004400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x00004800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x00004C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x00005000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x00005400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x00005800UL) +#define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x00005C00UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x00006000UL) +#define OPAMP1_BASE_NS (APB1PERIPH_BASE_NS + 0x00007000UL) +#define OPAMP2_BASE_NS (OPAMP1_BASE_NS + 0x0000010UL) +#define VREFBUF_BASE_NS (APB1PERIPH_BASE_NS + 0x00007400UL) +#define RTC_BASE_NS (APB1PERIPH_BASE_NS + 0x00007800UL) +#define TAMP_BASE_NS (APB1PERIPH_BASE_NS + 0x00007C00UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x00009400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0x0000A400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0x0000A500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0x0000AC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x00002C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x00003000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x00003400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x00003800UL) +#define TIM12_BASE_NS (APB2PERIPH_BASE_NS + 0x00003C00UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x00004000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x00004400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x00004800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x00005400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x0000004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x0000024UL) +#define USB_DRD_BASE_NS (APB2PERIPH_BASE_NS + 0x00006000UL) +#define USB_DRD_PMAADDR_NS (APB2PERIPH_BASE_NS + 0x00006400UL) +#define I3C2_BASE_NS (APB2PERIPH_BASE_NS + 0x00006C00UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x00000050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x000000D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x00000150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x000001D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x00000250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x000002D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x00000350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x000003D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x00000450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x000004D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x00000550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x000005D0UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x00002000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x00003000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x00004000UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x00006000UL) +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x00000040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x00000080UL) +#define HSP1_BASE_NS (AHB1PERIPH_BASE_NS + 0x0000C000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x00010400UL) +#define PWR_BASE_NS (AHB1PERIPH_BASE_NS + 0x00010800UL) +#define RCC_BASE_NS (AHB1PERIPH_BASE_NS + 0x00010C00UL) +#define EXTI_BASE_NS (AHB1PERIPH_BASE_NS + 0x00012000UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x00012400UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x00012C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x00013000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x00013400UL) +#define GTZC_MPCBB4_BASE_NS (AHB1PERIPH_BASE_NS + 0x00013800UL) +#define ADF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x00014000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x00000080UL) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x00000400UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x00002400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x00002800UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x00004400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x00004800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x00004C00UL) +#define COMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x00005400UL) +#define COMP2_BASE_NS (COMP1_BASE_NS + 0x00000004UL) +#define LCD_BASE_NS (APB3PERIPH_BASE_NS + 0x00008000UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x00001000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x00001400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x00001800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x00001C00UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008300UL) +#define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008400UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0800UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A2400UL) +#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A8000UL) +#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A8400UL) +#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0x000AF000UL) +#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0x000B1400UL) + +#if defined(CPU_IN_SECURE_STATE) +/*!< Flash, Peripheral and internal SRAMs base addresses - secure */ +#define FLASH_BASE_S 0x0C000000UL /*!< FLASH secure base address */ +#define SYSTEM_FLASH_BASE_S 0x0FF80000UL /*!< System FLASH secure base address */ +#define SRAM1_BASE_S 0x30000000UL /*!< SRAM1 secure base address */ +#define SRAM2_BASE_S 0x30018000UL /*!< SRAM2 secure base address */ +#define SRAM3_BASE_S 0x30028000UL /*!< SRAM3 secure base address */ +#define SRAM4_BASE_S 0x30068000UL /*!< SRAM4 secure base address */ +#define PERIPH_BASE_S 0x50000000UL /*!< Peripheral secure base address */ + +/*!< Peripheral memory map - secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x00040000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) + +/*!< APB1 secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x00000000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x00000400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x00000800UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x00001000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x00001400UL) +#define SPI3_BASE_S (APB1PERIPH_BASE_S + 0x00002000UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x00002C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x00003000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x00003800UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x00004400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x00004800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x00004C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x00005000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x00005400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x00005800UL) +#define I3C1_BASE_S (APB1PERIPH_BASE_S + 0x00005C00UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x00006000UL) +#define OPAMP1_BASE_S (APB1PERIPH_BASE_S + 0x00007000UL) +#define OPAMP2_BASE_S (OPAMP1_BASE_S + 0x0000010UL) +#define VREFBUF_BASE_S (APB1PERIPH_BASE_S + 0x00007400UL) +#define RTC_BASE_S (APB1PERIPH_BASE_S + 0x00007800UL) +#define TAMP_BASE_S (APB1PERIPH_BASE_S + 0x00007C00UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x00009400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0x0000A400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0x0000A500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0x0000AC00UL) + +/*!< APB2 secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x00002C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x00003000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x00003400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x00003800UL) +#define TIM12_BASE_S (APB2PERIPH_BASE_S + 0x00003C00UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x00004000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x00004400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x00004800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x00005400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x0000004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x0000024UL) +#define USB_DRD_BASE_S (APB2PERIPH_BASE_S + 0x00006000UL) +#define USB_DRD_PMAADDR_S (APB2PERIPH_BASE_S + 0x00006400UL) +#define I3C2_BASE_S (APB2PERIPH_BASE_S + 0x00006C00UL) + +/*!< AHB1 secure peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x00000050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x000000D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x00000150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x000001D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x00000250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x000002D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x00000350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x000003D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x00000450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x000004D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x00000550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x000005D0UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x00002000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x00003000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x00004000UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x00006000UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x00000040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x00000080UL) +#define HSP1_BASE_S (AHB1PERIPH_BASE_S + 0x0000C000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x00010400UL) +#define PWR_BASE_S (AHB1PERIPH_BASE_S + 0x00010800UL) +#define RCC_BASE_S (AHB1PERIPH_BASE_S + 0x00010C00UL) +#define EXTI_BASE_S (AHB1PERIPH_BASE_S + 0x00012000UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x00012400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x00012800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x00012C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x00013000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x00013400UL) +#define GTZC_MPCBB4_BASE_S (AHB1PERIPH_BASE_S + 0x00013800UL) +#define ADF1_BASE_S (AHB1PERIPH_BASE_S + 0x00014000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x00000080UL) + +/*!< APB3 secure peripherals */ +#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x00000400UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x00002400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x00002800UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x00004400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x00004800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x00004C00UL) +#define COMP1_BASE_S (APB3PERIPH_BASE_S + 0x00005400UL) +#define COMP2_BASE_S (COMP1_BASE_S + 0x00000004UL) +#define LCD_BASE_S (APB3PERIPH_BASE_S + 0x00008000UL) + +/*!< AHB2 secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00000400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00000800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00000C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x00001000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x00001400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x00001800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x00001C00UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x00008000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x00008100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x00008300UL) +#define DAC1_BASE_S (AHB2PERIPH_BASE_S + 0x00008400UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0x000A0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0x000A0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0x000A0800UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0x000A2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0x000A2400UL) +#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0x000A8000UL) +#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0x000A8400UL) +#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0x000AF000UL) +#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0x000B1400UL) +#endif /* CPU_IN_SECURE_STATE */ + +/*!< External memories base addresses - Not aliased */ +#define OCTOSPI1_BASE EXTRAM_BASE_NS + +/*!< DBGMCU base addresses - Not aliased */ +#define DBGMCU_BASE (EPPB_BASE + 0x00004000UL) + +/*!< USB PMA SIZE */ +#define USB_DRD_PMA_SIZE (2048U) /*!< USB PMA Size 2Kbyte */ + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START 0x0BF99040UL +#define RSSLIB_SYS_FLASH_NS_PFUNC_END 0x0BF990FFUL + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR 0xF5F5F5F5UL +#define RSSLIB_SUCCESS 0xEAEAEAEAUL + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos 0UL +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos 0UL +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos 1UL +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) +#define RSSLIB_HDPEXT_CLOSE_BOUNDARY_OPEN 0xC9C9C9C9UL /* Access to HDPx extension area and HDPx area denied but HDPx_EXT (in FLASH_HDPEXTR) increment allowed at any time */ +#define RSSLIB_HDPEXT_CLOSE_BOUNDARY_LOCK 0xD6D6D6D6UL /* Access to HDPx extension area and HDPx area denied. Update of HDPx_EXT size is not possible anymore */ + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param VectorTableAddr pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + +/** + * @brief Prototype of RSSLIB Close and exit HDP extension Function + * @detail This function close the requested hdp extension area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpExtArea notifies which hdp extension area to close, can be a combination of + * hdp extension area 1 and hdp extension area 2 + * @param VectorTableAddr pointer on the vector table containing the reset handler the function + * jumps to. + * @param CloseBound notifies if the HDP extension area should be closed with + * HDPx_EXT increment allowed or not + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDPExt_TypeDef)( uint32_t HdpExtArea, uint32_t VectorTableAddr, uint32_t CloseBound ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ + __IM RSSLIB_S_CloseExitHDPExt_TypeDef CloseExitHDPExt; /*!< RSSLIB Bootloader Close and exit HDP extension Address offset: 0x2C */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/* + * Certificate address description + */ +#define CERT_CHIP_PACK1_ADDR (0x0BF9FE00U) +#define CERT_CHIP_PACK1_SIZE (0x200U) +#define CERT_CHIP_PACK2_ADDR (0x0BF9FC00U) +#define CERT_CHIP_PACK2_SIZE (0x200U) + +#define CERT_CHIP_PACK_ADDR (CERT_CHIP_PACK2_ADDR) +#define CERT_CHIP_PACK_SIZE (CERT_CHIP_PACK1_SIZE + CERT_CHIP_PACK2_SIZE) + +#define CERT_ST_DUA_USER_FU_PUB_KEY_OFFSET (12U) +#define CERT_ST_DUA_USER_FU_PUB_KEY_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_FU_PUB_KEY_OFFSET) +#define CERT_ST_DUA_USER_FU_SIGN_OFFSET (76U) +#define CERT_ST_DUA_USER_FU_SIGN_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_FU_SIGN_OFFSET) +#define CERT_ST_DUA_USER_FU_SERIAL_OFFSET (140U) +#define CERT_ST_DUA_USER_FU_SERIAL_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_FU_SERIAL_OFFSET) + +#define CERT_ST_DUA_USER_LU_PUB_KEY_OFFSET (162U) +#define CERT_ST_DUA_USER_LU_PUB_KEY_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_LU_PUB_KEY_OFFSET) +#define CERT_ST_DUA_USER_LU_SIGN_OFFSET (226U) +#define CERT_ST_DUA_USER_LU_SIGN_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_LU_SIGN_OFFSET) +#define CERT_ST_DUA_USER_LU_SERIAL_OFFSET (290U) +#define CERT_ST_DUA_USER_LU_SERIAL_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_LU_SERIAL_OFFSET) +/** @} */ /* End of group STM32U3xx_Peripheral_peripheralAddr */ + + +/* ================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================================================== */ +/** @addtogroup STM32U3xx_Peripheral_declaration + * @{ + */ +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define I3C1_NS ((I3C_TypeDef *) I3C1_BASE_NS) +#define I3C2_NS ((I3C_TypeDef *) I3C2_BASE_NS) +#define HSP1_NS ((HSP_TypeDef *) HSP1_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define LCD_NS ((LCD_TypeDef *) LCD_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) +#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define TIM12_NS ((TIM_TypeDef *) TIM12_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define USB_DRD_FS_NS ((USB_DRD_TypeDef *) USB_DRD_BASE_NS) +#define USB_DRD_PMA_BUFF_NS ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) + +/*!< DBGMCU peripheral */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#if defined (CPU_IN_SECURE_STATE) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define I3C1_S ((I3C_TypeDef *) I3C1_BASE_S) +#define I3C2_S ((I3C_TypeDef *) I3C2_BASE_S) +#define HSP1_S ((HSP_TypeDef *) HSP1_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define LCD_S ((LCD_TypeDef *) LCD_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) +#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define TIM12_S ((TIM_TypeDef *) TIM12_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define USB_DRD_FS_S ((USB_DRD_TypeDef *) USB_DRD_BASE_S) +#define USB_DRD_PMA_BUFF_S ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define SRAM4_BASE SRAM4_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S +#define COMP2 COMP2_S +#define COMP2_BASE COMP2_BASE_S +#define COMP12_COMMON COMP12_COMMON_S +#define COMP12_COMMON_BASE COMP12_BASE_S +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S +#define GTZC_MPCBB4 GTZC_MPCBB4_S +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S +#define I3C1 I3C1_S +#define I3C1_BASE I3C1_BASE_S +#define I3C2 I3C2_S +#define I3C2_BASE I3C2_BASE_S +#define HSP1 HSP1_S +#define HSP1_BASE HSP1_BASE_S +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S +#define LCD LCD_S +#define LCD_BASE LCD_BASE_S +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S +#define OPAMP1 OPAMP1_S +#define OPAMP1_BASE OPAMP1_BASE_S +#define OPAMP2 OPAMP2_S +#define OPAMP2_BASE OPAMP2_BASE_S +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S +#define TIM12 TIM12_S +#define TIM12_BASE TIM12_BASE_S +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S +#define USB_DRD_FS USB_DRD_FS_S +#define USB_DRD_BASE USB_DRD_BASE_S +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_S +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_S +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#else /* CPU_IN_SECURE_STATE */ +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM3_BASE SRAM3_BASE_NS +#define SRAM4_BASE SRAM4_BASE_NS + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS +#define COMP12_COMMON COMP12_COMMON_NS +#define COMP12_COMMON_BASE COMP12_BASE_NS +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS +#define GTZC_MPCBB4 GTZC_MPCBB4_NS +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS +#define I3C1 I3C1_NS +#define I3C1_BASE I3C1_BASE_NS +#define I3C2 I3C2_NS +#define I3C2_BASE I3C2_BASE_NS +#define HSP1 HSP1_NS +#define HSP1_BASE HSP1_BASE_NS +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS +#define LCD LCD_NS +#define LCD_BASE LCD_BASE_NS +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS +#define OPAMP1 OPAMP1_NS +#define OPAMP1_BASE OPAMP1_BASE_NS +#define OPAMP2 OPAMP2_NS +#define OPAMP2_BASE OPAMP2_BASE_NS +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS +#define TIM12 TIM12_NS +#define TIM12_BASE TIM12_BASE_NS +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS +#define USB_DRD_FS USB_DRD_FS_NS +#define USB_DRD_BASE USB_DRD_BASE_NS +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_NS +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_NS +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS +#endif /* CPU_IN_SECURE_STATE */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 16000U /*!< LSI Maximum startup time in us : 4 cycles @ 250 Hz = 16 ms */ +/** + * @} + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ + +/* Specific device feature definitions */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0UL) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1UL) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2UL) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3UL) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4UL) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5UL) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6UL) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7UL) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8UL) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9UL) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10UL) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ +#define ADC_ISR_LDORDY_Pos (12UL) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC internal voltage regulator output ready flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0UL) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1UL) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2UL) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3UL) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4UL) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5UL) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6UL) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7UL) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8UL) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9UL) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10UL) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ +#define ADC_IER_LDORDYIE_Pos (12UL) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC internal voltage regulator interrupt*/ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0UL) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1UL) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2UL) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3UL) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4UL) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5UL) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28UL) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC internal voltage regulator */ +#define ADC_CR_DEEPPWD_Pos (29UL) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCAL_Pos (31UL) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register ******************/ +#define ADC_CFGR1_DMNGT_Pos (0UL) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC data management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2UL) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC_CFGR1_EXTSEL_Pos (5UL) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10UL) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12UL) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13UL) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_AUTDLY_Pos (14UL) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC low power auto wait */ + +#define ADC_CFGR1_DISCEN_Pos (16UL) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR1_DISCNUM_Pos (17UL) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20UL) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ + +#define ADC_CFGR1_JQM_Pos (21UL) +#define ADC_CFGR1_JQM_Msk (0x1UL << ADC_CFGR1_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_JQM ADC_CFGR1_JQM_Msk /*!< ADC group injected contexts queue mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22UL) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23UL) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR1_JAWD1EN_Pos (24UL) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR1_JAUTO_Pos (25UL) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26UL) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR1_JQDIS_Pos (31UL) +#define ADC_CFGR1_JQDIS_Msk (0x1UL << ADC_CFGR1_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR1_JQDIS ADC_CFGR1_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0UL) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1UL) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSS_Pos (5UL) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9UL) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10UL) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_BULB_Pos (13UL) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14UL) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15UL) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC sampling time control trigger mode */ + +#define ADC_CFGR2_OVSR_Pos (16UL) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_LFTRIG_Pos (27UL) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low-frequency trigge */ + +#define ADC_CFGR2_LSHIFT_Pos (28UL) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0UL) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3UL) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6UL) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9UL) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12UL) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15UL) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18UL) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21UL) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24UL) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27UL) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0UL) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3UL) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6UL) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9UL) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12UL) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15UL) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18UL) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21UL) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24UL) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27UL) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register *****************/ +#define ADC_PCSEL_PCSEL_Pos (0UL) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC channel preselection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0UL) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6UL) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12UL) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18UL) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24UL) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0UL) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6UL) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12UL) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18UL) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24UL) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0UL) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6UL) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12UL) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18UL) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24UL) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0UL) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6UL) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0UL) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_RDATA_0 (0x00000001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x00000002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x00000004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x00000008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x00000010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x00000020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x00000040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x00000080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x00000100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x00000200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x00000400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x00000800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x00001000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x00002000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x00004000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x00008000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_16 (0x00010000UL << ADC_DR_RDATA_Pos) /*!< 0x00010000 */ +#define ADC_DR_RDATA_17 (0x00020000UL << ADC_DR_RDATA_Pos) /*!< 0x00020000 */ +#define ADC_DR_RDATA_18 (0x00040000UL << ADC_DR_RDATA_Pos) /*!< 0x00040000 */ +#define ADC_DR_RDATA_19 (0x00080000UL << ADC_DR_RDATA_Pos) /*!< 0x00080000 */ +#define ADC_DR_RDATA_20 (0x00100000UL << ADC_DR_RDATA_Pos) /*!< 0x00100000 */ +#define ADC_DR_RDATA_21 (0x00200000UL << ADC_DR_RDATA_Pos) /*!< 0x00200000 */ +#define ADC_DR_RDATA_22 (0x00400000UL << ADC_DR_RDATA_Pos) /*!< 0x00400000 */ +#define ADC_DR_RDATA_23 (0x00800000UL << ADC_DR_RDATA_Pos) /*!< 0x00800000 */ +#define ADC_DR_RDATA_24 (0x01000000UL << ADC_DR_RDATA_Pos) /*!< 0x01000000 */ +#define ADC_DR_RDATA_25 (0x02000000UL << ADC_DR_RDATA_Pos) /*!< 0x02000000 */ +#define ADC_DR_RDATA_26 (0x04000000UL << ADC_DR_RDATA_Pos) /*!< 0x04000000 */ +#define ADC_DR_RDATA_27 (0x08000000UL << ADC_DR_RDATA_Pos) /*!< 0x08000000 */ +#define ADC_DR_RDATA_28 (0x10000000UL << ADC_DR_RDATA_Pos) /*!< 0x10000000 */ +#define ADC_DR_RDATA_29 (0x20000000UL << ADC_DR_RDATA_Pos) /*!< 0x20000000 */ +#define ADC_DR_RDATA_30 (0x40000000UL << ADC_DR_RDATA_Pos) /*!< 0x40000000 */ +#define ADC_DR_RDATA_31 (0x80000000UL << ADC_DR_RDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0UL) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2UL) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7UL) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9UL) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15UL) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21UL) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27UL) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR1 register ***************/ +#define ADC_OFCFGR1_POSOFF_Pos (24UL) +#define ADC_OFCFGR1_POSOFF_Msk (0x01UL << ADC_OFCFGR1_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR1_POSOFF ADC_OFCFGR1_POSOFF_Msk /*!< ADC offset instance 1 positive offset enable */ + +#define ADC_OFCFGR1_USAT_Pos (25UL) +#define ADC_OFCFGR1_USAT_Msk (0x01UL << ADC_OFCFGR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR1_USAT ADC_OFCFGR1_USAT_Msk /*!< ADC offset instance 1 unsigned saturation value */ + +#define ADC_OFCFGR1_SSAT_Pos (26UL) +#define ADC_OFCFGR1_SSAT_Msk (0x01UL << ADC_OFCFGR1_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR1_SSAT ADC_OFCFGR1_SSAT_Msk /*!< ADC offset instance 1 signed satuaration enable */ + +#define ADC_OFCFGR1_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR1_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR1_OFFSET_CH ADC_OFCFGR1_OFFSET_CH_Msk /*!< ADC offset instance 1 channel selection */ +#define ADC_OFCFGR1_OFFSET_CH_0 (0x01UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR1_OFFSET_CH_1 (0x02UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR1_OFFSET_CH_2 (0x03UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR1_OFFSET_CH_3 (0x04UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR1_OFFSET_CH_4 (0x05UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR2 register ***************/ +#define ADC_OFCFGR2_POSOFF_Pos (24UL) +#define ADC_OFCFGR2_POSOFF_Msk (0x01UL << ADC_OFCFGR2_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR2_POSOFF ADC_OFCFGR2_POSOFF_Msk /*!< ADC offset instance 2 positive offset enable */ + +#define ADC_OFCFGR2_USAT_Pos (25UL) +#define ADC_OFCFGR2_USAT_Msk (0x01UL << ADC_OFCFGR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR2_USAT ADC_OFCFGR2_USAT_Msk /*!< ADC offset instance 2 unsigned saturation value */ + +#define ADC_OFCFGR2_SSAT_Pos (26UL) +#define ADC_OFCFGR2_SSAT_Msk (0x01UL << ADC_OFCFGR2_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR2_SSAT ADC_OFCFGR2_SSAT_Msk /*!< ADC offset instance 2 signed satuaration enable */ + +#define ADC_OFCFGR2_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR2_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR2_OFFSET_CH ADC_OFCFGR2_OFFSET_CH_Msk /*!< ADC offset instance 2 channel selection */ +#define ADC_OFCFGR2_OFFSET_CH_0 (0x01UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR2_OFFSET_CH_1 (0x02UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR2_OFFSET_CH_2 (0x03UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR2_OFFSET_CH_3 (0x04UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR2_OFFSET_CH_4 (0x05UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR3 register ***************/ +#define ADC_OFCFGR3_POSOFF_Pos (24UL) +#define ADC_OFCFGR3_POSOFF_Msk (0x01UL << ADC_OFCFGR3_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR3_POSOFF ADC_OFCFGR3_POSOFF_Msk /*!< ADC offset instance 3 positive offset enable */ + +#define ADC_OFCFGR3_USAT_Pos (25UL) +#define ADC_OFCFGR3_USAT_Msk (0x01UL << ADC_OFCFGR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR3_USAT ADC_OFCFGR3_USAT_Msk /*!< ADC offset instance 3 unsigned saturation value */ + +#define ADC_OFCFGR3_SSAT_Pos (26UL) +#define ADC_OFCFGR3_SSAT_Msk (0x01UL << ADC_OFCFGR3_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR3_SSAT ADC_OFCFGR3_SSAT_Msk /*!< ADC offset instance 3 signed satuaration enable */ + +#define ADC_OFCFGR3_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR3_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR3_OFFSET_CH ADC_OFCFGR3_OFFSET_CH_Msk /*!< ADC offset instance 3 channel selection for the data offset */ +#define ADC_OFCFGR3_OFFSET_CH_0 (0x01UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR3_OFFSET_CH_1 (0x02UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR3_OFFSET_CH_2 (0x03UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR3_OFFSET_CH_3 (0x04UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR3_OFFSET_CH_4 (0x05UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR4 register ***************/ +#define ADC_OFCFGR4_POSOFF_Pos (24UL) +#define ADC_OFCFGR4_POSOFF_Msk (0x01UL << ADC_OFCFGR4_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR4_POSOFF ADC_OFCFGR4_POSOFF_Msk /*!< ADC offset instance 4 positive offset enable */ + +#define ADC_OFCFGR4_USAT_Pos (25UL) +#define ADC_OFCFGR4_USAT_Msk (0x01UL << ADC_OFCFGR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR4_USAT ADC_OFCFGR4_USAT_Msk /*!< ADC offset instance 4 unsigned saturation value */ + +#define ADC_OFCFGR4_SSAT_Pos (26UL) +#define ADC_OFCFGR4_SSAT_Msk (0x01UL << ADC_OFCFGR4_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR4_SSAT ADC_OFCFGR4_SSAT_Msk /*!< ADC offset instance 4 signed satuaration enable */ + +#define ADC_OFCFGR4_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR4_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR4_OFFSET_CH ADC_OFCFGR4_OFFSET_CH_Msk /*!< ADC offset instance 4 channel selection for the data offset */ +#define ADC_OFCFGR4_OFFSET_CH_0 (0x01UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR4_OFFSET_CH_1 (0x02UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR4_OFFSET_CH_2 (0x03UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR4_OFFSET_CH_3 (0x04UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR4_OFFSET_CH_4 (0x05UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET_Pos (0UL) +#define ADC_OFR1_OFFSET_Msk (0x03FFFFFUL << ADC_OFR1_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR1_OFFSET ADC_OFR1_OFFSET_Msk /*!< ADC offset instance 1 offset level */ +#define ADC_OFR1_OFFSET_0 (0x0000001UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET_1 (0x0000002UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET_2 (0x0000004UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET_3 (0x0000008UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET_4 (0x0000010UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET_5 (0x0000020UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET_6 (0x0000040UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET_7 (0x0000080UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET_8 (0x0000100UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET_9 (0x0000200UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET_10 (0x0000400UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET_11 (0x0000800UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET_12 (0x0001000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET_13 (0x0002000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET_14 (0x0004000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET_15 (0x0008000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET_16 (0x0010000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET_17 (0x0020000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET_18 (0x0040000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET_19 (0x0080000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET_20 (0x0100000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET_21 (0x0200000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET_Pos (0UL) +#define ADC_OFR2_OFFSET_Msk (0x03FFFFFUL << ADC_OFR2_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR2_OFFSET ADC_OFR2_OFFSET_Msk /*!< ADC offset instance 2 offset level */ +#define ADC_OFR2_OFFSET_0 (0x0000001UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET_1 (0x0000002UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET_2 (0x0000004UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET_3 (0x0000008UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET_4 (0x0000010UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET_5 (0x0000020UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET_6 (0x0000040UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET_7 (0x0000080UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET_8 (0x0000100UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET_9 (0x0000200UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET_10 (0x0000400UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET_11 (0x0000800UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET_12 (0x0001000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET_13 (0x0002000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET_14 (0x0004000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET_15 (0x0008000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET_16 (0x0010000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET_17 (0x0020000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET_18 (0x0040000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET_19 (0x0080000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET_20 (0x0100000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET_21 (0x0200000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET_Pos (0UL) +#define ADC_OFR3_OFFSET_Msk (0x03FFFFFUL << ADC_OFR3_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR3_OFFSET ADC_OFR3_OFFSET_Msk /*!< ADC offset instance 3 offset level */ +#define ADC_OFR3_OFFSET_0 (0x0000001UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET_1 (0x0000002UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET_2 (0x0000004UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET_3 (0x0000008UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET_4 (0x0000010UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET_5 (0x0000020UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET_6 (0x0000040UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET_7 (0x0000080UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET_8 (0x0000100UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET_9 (0x0000200UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET_10 (0x0000400UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET_11 (0x0000800UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET_12 (0x0001000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET_13 (0x0002000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET_14 (0x0004000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET_15 (0x0008000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET_16 (0x0010000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET_17 (0x0020000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET_18 (0x0040000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET_19 (0x0080000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET_20 (0x0100000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET_21 (0x0200000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET_Pos (0UL) +#define ADC_OFR4_OFFSET_Msk (0x03FFFFFUL << ADC_OFR4_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR4_OFFSET ADC_OFR4_OFFSET_Msk /*!< ADC offset instance 4 offset level */ +#define ADC_OFR4_OFFSET_0 (0x0000001UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET_1 (0x0000002UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET_2 (0x0000004UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET_3 (0x0000008UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET_4 (0x0000010UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET_5 (0x0000020UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET_6 (0x0000040UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET_7 (0x0000080UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET_8 (0x0000100UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET_9 (0x0000200UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET_10 (0x0000400UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET_11 (0x0000800UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET_12 (0x0001000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET_13 (0x0002000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET_14 (0x0004000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET_15 (0x0008000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET_16 (0x0010000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET_17 (0x0020000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET_18 (0x0040000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET_19 (0x0080000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET_20 (0x0100000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET_21 (0x0200000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_GCOMP register *****************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< Gain compensation coefficient */ +#define ADC_GCOMP_GCOMPCOEFF_0 (0x0001UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000001 */ +#define ADC_GCOMP_GCOMPCOEFF_1 (0x0002UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000002 */ +#define ADC_GCOMP_GCOMPCOEFF_2 (0x0004UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000004 */ +#define ADC_GCOMP_GCOMPCOEFF_3 (0x0008UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000008 */ +#define ADC_GCOMP_GCOMPCOEFF_4 (0x0010UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000010 */ +#define ADC_GCOMP_GCOMPCOEFF_5 (0x0020UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000020 */ +#define ADC_GCOMP_GCOMPCOEFF_6 (0x0040UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000040 */ +#define ADC_GCOMP_GCOMPCOEFF_7 (0x0080UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000080 */ +#define ADC_GCOMP_GCOMPCOEFF_8 (0x0100UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000100 */ +#define ADC_GCOMP_GCOMPCOEFF_9 (0x0200UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000200 */ +#define ADC_GCOMP_GCOMPCOEFF_10 (0x0400UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000400 */ +#define ADC_GCOMP_GCOMPCOEFF_11 (0x0800UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000800 */ +#define ADC_GCOMP_GCOMPCOEFF_12 (0x1000UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00001000 */ +#define ADC_GCOMP_GCOMPCOEFF_13 (0x2000UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00002000 */ + +#define ADC_GCOMP_GCOMP_Pos (31UL) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x80000000 */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< Gain compensation mode */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0UL) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0UL) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0UL) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0UL) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0UL) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0UL) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD1TR_LT register *************/ +#define ADC_AWD1LTR_LTR_Pos (0UL) +#define ADC_AWD1LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD1LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1LTR_LTR ADC_AWD1LTR_LTR_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1LTR_LTR_0 (0x000001UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1LTR_LTR_1 (0x000002UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1LTR_LTR_2 (0x000004UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1LTR_LTR_3 (0x000008UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1LTR_LTR_4 (0x000010UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1LTR_LTR_5 (0x000020UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1LTR_LTR_6 (0x000040UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1LTR_LTR_7 (0x000080UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1LTR_LTR_8 (0x000100UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1LTR_LTR_9 (0x000200UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1LTR_LTR_10 (0x000400UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1LTR_LTR_11 (0x000800UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1LTR_LTR_12 (0x001000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1LTR_LTR_13 (0x002000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1LTR_LTR_14 (0x004000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1LTR_LTR_15 (0x008000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1LTR_LTR_16 (0x010000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1LTR_LTR_17 (0x020000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1LTR_LTR_18 (0x040000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1LTR_LTR_19 (0x080000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1LTR_LTR_20 (0x100000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1LTR_LTR_21 (0x200000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1LTR_LTR_22 (0x400000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD1TR_HT register *******************/ +#define ADC_AWD1HTR_HTR_Pos (0UL) +#define ADC_AWD1HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD1HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1HTR_HTR ADC_AWD1HTR_HTR_Msk /*!< ADC analog watchdog 1 threshold high */ +#define ADC_AWD1HTR_HTR_0 (0x000001UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_HTR_1 (0x000002UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_HTR_2 (0x000004UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1HTR_HTR_3 (0x000008UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1HTR_HTR_4 (0x000010UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1HTR_HTR_5 (0x000020UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1HTR_HTR_6 (0x000040UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1HTR_HTR_7 (0x000080UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1HTR_HTR_8 (0x000100UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1HTR_HTR_9 (0x000200UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1HTR_HTR_10 (0x000400UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1HTR_HTR_11 (0x000800UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1HTR_HTR_12 (0x001000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1HTR_HTR_13 (0x002000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1HTR_HTR_14 (0x004000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1HTR_HTR_15 (0x008000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1HTR_HTR_16 (0x010000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1HTR_HTR_17 (0x020000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1HTR_HTR_18 (0x040000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1HTR_HTR_19 (0x080000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1HTR_HTR_20 (0x100000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1HTR_HTR_21 (0x200000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1HTR_HTR_22 (0x400000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00400000 */ + +#define ADC_AWD1HTR_AWDFILT_Pos (29UL) +#define ADC_AWD1HTR_AWDFILT_Msk (0x7UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000007 */ +#define ADC_AWD1HTR_AWDFILT ADC_AWD1HTR_AWDFILT_Msk /*!< ADC analog watchdog 1 filtering */ +#define ADC_AWD1HTR_AWDFILT_0 (0x000001UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_AWDFILT_1 (0x000002UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_AWDFILT_2 (0x000004UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000004 */ + +/******************** Bit definition for ADC_AWD2TR_LT register *******************/ +#define ADC_AWD2LTR_LTR_Pos (0UL) +#define ADC_AWD2LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD2LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2LTR_LTR ADC_AWD2LTR_LTR_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2LTR_LTR_0 (0x000001UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2LTR_LTR_1 (0x000002UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2LTR_LTR_2 (0x000004UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2LTR_LTR_3 (0x000008UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2LTR_LTR_4 (0x000010UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2LTR_LTR_5 (0x000020UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2LTR_LTR_6 (0x000040UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2LTR_LTR_7 (0x000080UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2LTR_LTR_8 (0x000100UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2LTR_LTR_9 (0x000200UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2LTR_LTR_10 (0x000400UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2LTR_LTR_11 (0x000800UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2LTR_LTR_12 (0x001000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2LTR_LTR_13 (0x002000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2LTR_LTR_14 (0x004000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2LTR_LTR_15 (0x008000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2LTR_LTR_16 (0x010000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2LTR_LTR_17 (0x020000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2LTR_LTR_18 (0x040000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2LTR_LTR_19 (0x080000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2LTR_LTR_20 (0x100000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2LTR_LTR_21 (0x200000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2LTR_LTR_22 (0x400000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD2TR_HT register *******************/ +#define ADC_AWD2HTR_HTR_Pos (0UL) +#define ADC_AWD2HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD2HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2HTR_HTR ADC_AWD2HTR_HTR_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2HTR_HTR_0 (0x000001UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2HTR_HTR_1 (0x000002UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2HTR_HTR_2 (0x000004UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2HTR_HTR_3 (0x000008UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2HTR_HTR_4 (0x000010UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2HTR_HTR_5 (0x000020UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2HTR_HTR_6 (0x000040UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2HTR_HTR_7 (0x000080UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2HTR_HTR_8 (0x000100UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2HTR_HTR_9 (0x000200UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2HTR_HTR_10 (0x000400UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2HTR_HTR_11 (0x000800UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2HTR_HTR_12 (0x001000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2HTR_HTR_13 (0x002000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2HTR_HTR_14 (0x004000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2HTR_HTR_15 (0x008000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2HTR_HTR_16 (0x010000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2HTR_HTR_17 (0x020000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2HTR_HTR_18 (0x040000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2HTR_HTR_19 (0x080000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2HTR_HTR_20 (0x100000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2HTR_HTR_21 (0x200000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2HTR_HTR_22 (0x400000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD3TR_LT register *******************/ +#define ADC_AWD3LTR_LTR_Pos (0UL) +#define ADC_AWD3LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD3LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3LTR_LTR ADC_AWD3LTR_LTR_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3LTR_LTR_0 (0x000001UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3LTR_LTR_1 (0x000002UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3LTR_LTR_2 (0x000004UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3LTR_LTR_3 (0x000008UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3LTR_LTR_4 (0x000010UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3LTR_LTR_5 (0x000020UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3LTR_LTR_6 (0x000040UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3LTR_LTR_7 (0x000080UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3LTR_LTR_8 (0x000100UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3LTR_LTR_9 (0x000200UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3LTR_LTR_10 (0x000400UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3LTR_LTR_11 (0x000800UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3LTR_LTR_12 (0x001000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3LTR_LTR_13 (0x002000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3LTR_LTR_14 (0x004000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3LTR_LTR_15 (0x008000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3LTR_LTR_16 (0x010000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3LTR_LTR_17 (0x020000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3LTR_LTR_18 (0x040000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3LTR_LTR_19 (0x080000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3LTR_LTR_20 (0x100000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3LTR_LTR_21 (0x200000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3LTR_LTR_22 (0x400000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD3TR_HT register *******************/ +#define ADC_AWD3HTR_HTR_Pos (0UL) +#define ADC_AWD3HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD3HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3HTR_HTR ADC_AWD3HTR_HTR_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3HTR_HTR_0 (0x000001UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3HTR_HTR_1 (0x000002UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3HTR_HTR_2 (0x000004UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3HTR_HTR_3 (0x000008UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3HTR_HTR_4 (0x000010UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3HTR_HTR_5 (0x000020UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3HTR_HTR_6 (0x000040UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3HTR_HTR_7 (0x000080UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3HTR_HTR_8 (0x000100UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3HTR_HTR_9 (0x000200UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3HTR_HTR_10 (0x000400UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3HTR_HTR_11 (0x000800UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3HTR_HTR_12 (0x001000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3HTR_HTR_13 (0x002000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3HTR_HTR_14 (0x004000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3HTR_HTR_15 (0x008000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3HTR_HTR_16 (0x010000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3HTR_HTR_17 (0x020000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3HTR_HTR_18 (0x040000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3HTR_HTR_19 (0x080000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3HTR_HTR_20 (0x100000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3HTR_HTR_21 (0x200000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3HTR_HTR_22 (0x400000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ + +#define ADC_CALFACT_CALFACT_Pos (0UL) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_7 (0x80UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT_CALFACT_8 (0x100UL<< ADC_CALFACT_CALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_CALFACT_9 (0x200UL<< ADC_CALFACT_CALFACT_Pos) /*!< 0x00000200 */ + + +/******************** Bit definition for ADC_OR option register ***************/ +#define ADC_OR_VDDCOREEN_Pos (0UL) +#define ADC_OR_VDDCOREEN_Msk (0x1UL << ADC_OR_VDDCOREEN_Pos) /*!< 0x00000004 */ +#define ADC_OR_VDDCOREEN ADC_OR_VDDCOREEN_Msk /*!< ADC internal path to VDDCORE */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0UL) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1UL) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2UL) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3UL) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4UL) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5UL) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6UL) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7UL) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8UL) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9UL) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10UL) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ +#define ADC_CSR_LDORDY_MST_Pos (12UL) +#define ADC_CSR_LDORDY_MST_Msk (0x1UL << ADC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADC_CSR_LDORDY_MST ADC_CSR_LDORDY_MST_Msk /*!< ADC multimode master internal voltage regulator output ready flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16UL) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17UL) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18UL) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19UL) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20UL) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21UL) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22UL) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23UL) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24UL) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25UL) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26UL) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ +#define ADC_CSR_LDORDY_SLV_Pos (28UL) +#define ADC_CSR_LDORDY_SLV_Msk (0x1UL << ADC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CSR_LDORDY_SLV ADC_CSR_LDORDY_SLV_Msk /*!< ADC multimode slave internal voltage regulator output ready flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0UL) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8UL) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DAMDF_Pos (14UL) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< ADC multimode data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_PRESC_Pos (18UL) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22UL) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ + +#define ADC_CCR_TSEN_Pos (23UL) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to Temperature sensor voltage enable */ + +#define ADC_CCR_VBATEN_Pos (24UL) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0UL) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16UL) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0UL) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< ADC multimode master or slave (alternated) group regular conversion data */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0UL) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0UL) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0UL) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3UL) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5UL) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7UL) +#define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ +#define CRC_CR_RTYPE_IN_Pos (9UL) +#define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ +#define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< RTYPE_IN Reverse Type Input bit */ +#define CRC_CR_RTYPE_OUT_Pos (10UL) +#define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ +#define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< RTYPE_OUT Reverse Type Output bit */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0UL) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0UL) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0UL) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1UL) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2UL) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3UL) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5UL) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6UL) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7UL) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8UL) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0UL) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16UL) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24UL) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28UL) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31UL) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0UL) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1UL) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2UL) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3UL) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8UL) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9UL) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10UL) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15UL) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16UL) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0UL) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1UL) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2UL) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3UL) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ +/*!< ****************** Bit definition for COMPx_CSR register ********************/ +#define COMP_CSR_EN_Pos (0UL) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< COMPx enable bit */ +#define COMP_CSR_INMSEL_Pos (4UL) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00070000 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< COMPx input minus selection bit */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00010000 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00020000 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00040000 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00080000 */ +#define COMP_CSR_INPSEL_Pos (8UL) +#define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00100000 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< COMPx input plus selection bit */ +#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) +#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) +#define COMP_CSR_WINMODE_Pos (11UL) +#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000010 */ +#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< COMPx Windows mode selection bit */ +#define COMP_CSR_WINOUT_Pos (14UL) +#define COMP_CSR_WINOUT_Msk (0x1UL << COMP_CSR_WINOUT_Pos) /*!< 0x00000008 */ +#define COMP_CSR_WINOUT COMP_CSR_WINOUT_Msk /*!< COMPx polarity selection bit */ +#define COMP_CSR_POLARITY_Pos (15UL) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00000008 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< COMPx polarity selection bit */ +#define COMP_CSR_HYST_Pos (16UL) +#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00000300 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< COMPx hysteresis selection bits */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00000100 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00000200 */ +#define COMP_CSR_PWRMODE_Pos (18UL) +#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00003000 */ +#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< COMPx Power Mode of the comparator */ +#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00001000 */ +#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00002000 */ +#define COMP_CSR_BLANKSEL_Pos (20UL) +#define COMP_CSR_BLANKSEL_Msk (0x1FUL << COMP_CSR_BLANKSEL_Pos) /*!< 0x0F000000 */ +#define COMP_CSR_BLANKSEL COMP_CSR_BLANKSEL_Msk /*!< COMPx blanking source selection bits */ +#define COMP_CSR_BLANKSEL_0 (0x1UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ +#define COMP_CSR_BLANKSEL_1 (0x2UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x02000000 */ +#define COMP_CSR_BLANKSEL_2 (0x4UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x04000000 */ +#define COMP_CSR_BLANKSEL_3 (0x8UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x08000000 */ +#define COMP_CSR_BLANKSEL_4 (0x10UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ +#define COMP2_CSR_BLANKSEL_2 COMP_CSR_BLANKSEL_2 /*!< COMP2 blanking source selection bit 2 */ +#define COMP_CSR_VALUE_Pos (30UL) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x00000001 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< COMPx enable bit */ +#define COMP_CSR_LOCK_Pos (31UL) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< COMPx Lock Bit */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0UL) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14UL) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16UL) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30UL) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!(1)) */ + +#define HSP_ITFENR_TRGOEN_Pos (12UL) +#define HSP_ITFENR_TRGOEN_Msk (0x1UL << HSP_ITFENR_TRGOEN_Pos) /*!< 0x00001000 */ +#define HSP_ITFENR_TRGOEN HSP_ITFENR_TRGOEN_Msk /*!< TRGOEN (TRGO enable bit (1)) */ + +#define HSP_ITFENR_TRGI0EN_Pos (16UL) +#define HSP_ITFENR_TRGI0EN_Msk (0x1UL << HSP_ITFENR_TRGI0EN_Pos) /*!< 0x00010000 */ +#define HSP_ITFENR_TRGI0EN HSP_ITFENR_TRGI0EN_Msk /*!< TRGI0EN (TRGIN0 enable bit (1)) */ + +#define HSP_ITFENR_TRGI1EN_Pos (17UL) +#define HSP_ITFENR_TRGI1EN_Msk (0x1UL << HSP_ITFENR_TRGI1EN_Pos) /*!< 0x00020000 */ +#define HSP_ITFENR_TRGI1EN HSP_ITFENR_TRGI1EN_Msk /*!< TRGI1EN (TRGIN1 enable bit (1)) */ + +#define HSP_ITFENR_TRGI2EN_Pos (18UL) +#define HSP_ITFENR_TRGI2EN_Msk (0x1UL << HSP_ITFENR_TRGI2EN_Pos) /*!< 0x00040000 */ +#define HSP_ITFENR_TRGI2EN HSP_ITFENR_TRGI2EN_Msk /*!< TRGI2EN (TRGIN2 enable bit (1)) */ + +#define HSP_ITFENR_TRGI3EN_Pos (19UL) +#define HSP_ITFENR_TRGI3EN_Msk (0x1UL << HSP_ITFENR_TRGI3EN_Pos) /*!< 0x00080000 */ +#define HSP_ITFENR_TRGI3EN HSP_ITFENR_TRGI3EN_Msk /*!< TRGI3EN (TRGIN3 enable bit (1)) */ + +#define HSP_ITFENR_TRGI4EN_Pos (20UL) +#define HSP_ITFENR_TRGI4EN_Msk (0x1UL << HSP_ITFENR_TRGI4EN_Pos) /*!< 0x00100000 */ +#define HSP_ITFENR_TRGI4EN HSP_ITFENR_TRGI4EN_Msk /*!< TRGI4EN (TRGIN4 enable bit (1)) */ + +#define HSP_ITFENR_TRGI5EN_Pos (21UL) +#define HSP_ITFENR_TRGI5EN_Msk (0x1UL << HSP_ITFENR_TRGI5EN_Pos) /*!< 0x00200000 */ +#define HSP_ITFENR_TRGI5EN HSP_ITFENR_TRGI5EN_Msk /*!< TRGI5EN (TRGIN5 enable bit (1)) */ + +#define HSP_ITFENR_TRGI6EN_Pos (22UL) +#define HSP_ITFENR_TRGI6EN_Msk (0x1UL << HSP_ITFENR_TRGI6EN_Pos) /*!< 0x00400000 */ +#define HSP_ITFENR_TRGI6EN HSP_ITFENR_TRGI6EN_Msk /*!< TRGI6EN (TRGIN6 enable bit (1)) */ + +#define HSP_ITFENR_TRGI7EN_Pos (23UL) +#define HSP_ITFENR_TRGI7EN_Msk (0x1UL << HSP_ITFENR_TRGI7EN_Pos) /*!< 0x00800000 */ +#define HSP_ITFENR_TRGI7EN HSP_ITFENR_TRGI7EN_Msk /*!< TRGI7EN (TRGIN7 enable bit (1)) */ + +#define HSP_ITFENR_TRGI8EN_Pos (24UL) +#define HSP_ITFENR_TRGI8EN_Msk (0x1UL << HSP_ITFENR_TRGI8EN_Pos) /*!< 0x01000000 */ +#define HSP_ITFENR_TRGI8EN HSP_ITFENR_TRGI8EN_Msk /*!< TRGI8EN (TRGIN8 enable bit (1)) */ + +#define HSP_ITFENR_TRGI9EN_Pos (25UL) +#define HSP_ITFENR_TRGI9EN_Msk (0x1UL << HSP_ITFENR_TRGI9EN_Pos) /*!< 0x02000000 */ +#define HSP_ITFENR_TRGI9EN HSP_ITFENR_TRGI9EN_Msk /*!< TRGI9EN (TRGIN9 enable bit (1)) */ + +#define HSP_ITFENR_DCMDDIS_Pos (27UL) +#define HSP_ITFENR_DCMDDIS_Msk (0x1UL << HSP_ITFENR_DCMDDIS_Pos) /*!< 0x08000000 */ +#define HSP_ITFENR_DCMDDIS HSP_ITFENR_DCMDDIS_Msk /*!< DCMDDIS (Direct command interface disable bit ) */ + +#define HSP_ITFENR_CSEGEN_Pos (28UL) +#define HSP_ITFENR_CSEGEN_Msk (0x1UL << HSP_ITFENR_CSEGEN_Pos) /*!< 0x10000000 */ +#define HSP_ITFENR_CSEGEN HSP_ITFENR_CSEGEN_Msk /*!< CSEGEN (CSEG interface enable bit (1)) */ + +#define HSP_ITFENR_CDEGEN_Pos (29UL) +#define HSP_ITFENR_CDEGEN_Msk (0x1UL << HSP_ITFENR_CDEGEN_Pos) /*!< 0x20000000 */ +#define HSP_ITFENR_CDEGEN HSP_ITFENR_CDEGEN_Msk /*!< CDEGEN (CDEG interface enable bit ) */ + +#define HSP_ITFENR_HSEGEN_Pos (30UL) +#define HSP_ITFENR_HSEGEN_Msk (0x1UL << HSP_ITFENR_HSEGEN_Pos) /*!< 0x40000000 */ +#define HSP_ITFENR_HSEGEN HSP_ITFENR_HSEGEN_Msk /*!< HSEGEN (HSEG interface enable bit ) */ + +#define HSP_ITFENR_HDEGEN_Pos (31UL) +#define HSP_ITFENR_HDEGEN_Msk (0x1UL << HSP_ITFENR_HDEGEN_Pos) /*!< 0x80000000 */ +#define HSP_ITFENR_HDEGEN HSP_ITFENR_HDEGEN_Msk /*!< HDEGEN (HDEG interface enable bit ) */ + +/******************** Bit definition for HSP_EVTSRC0R register ********************/ +#define HSP_EVTSRC0R_EVT1SRC_Pos (0UL) +#define HSP_EVTSRC0R_EVT1SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT1SRC_Pos) /*!< 0x00000007 */ +#define HSP_EVTSRC0R_EVT1SRC HSP_EVTSRC0R_EVT1SRC_Msk /*!< EVT1SRC[2:0] bits (Event source selection for priority encoder input 1) */ +#define HSP_EVTSRC0R_EVT1SRC_0 (0x1UL << HSP_EVTSRC0R_EVT1SRC_Pos) /*!< 0x00000001 */ +#define HSP_EVTSRC0R_EVT1SRC_1 (0x2UL << HSP_EVTSRC0R_EVT1SRC_Pos) /*!< 0x00000002 */ +#define HSP_EVTSRC0R_EVT1SRC_2 (0x4UL << HSP_EVTSRC0R_EVT1SRC_Pos) /*!< 0x00000004 */ + +#define HSP_EVTSRC0R_EVT2SRC_Pos (4UL) +#define HSP_EVTSRC0R_EVT2SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT2SRC_Pos) /*!< 0x00000070 */ +#define HSP_EVTSRC0R_EVT2SRC HSP_EVTSRC0R_EVT2SRC_Msk /*!< EVT2SRC[2:0] bits (Event source selection for priority encoder input 2) */ +#define HSP_EVTSRC0R_EVT2SRC_0 (0x1UL << HSP_EVTSRC0R_EVT2SRC_Pos) /*!< 0x00000010 */ +#define HSP_EVTSRC0R_EVT2SRC_1 (0x2UL << HSP_EVTSRC0R_EVT2SRC_Pos) /*!< 0x00000020 */ +#define HSP_EVTSRC0R_EVT2SRC_2 (0x4UL << HSP_EVTSRC0R_EVT2SRC_Pos) /*!< 0x00000040 */ + +#define HSP_EVTSRC0R_EVT3SRC_Pos (8UL) +#define HSP_EVTSRC0R_EVT3SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT3SRC_Pos) /*!< 0x00000700 */ +#define HSP_EVTSRC0R_EVT3SRC HSP_EVTSRC0R_EVT3SRC_Msk /*!< EVT3SRC[2:0] bits (Event source selection for priority encoder input 3) */ +#define HSP_EVTSRC0R_EVT3SRC_0 (0x1UL << HSP_EVTSRC0R_EVT3SRC_Pos) /*!< 0x00000100 */ +#define HSP_EVTSRC0R_EVT3SRC_1 (0x2UL << HSP_EVTSRC0R_EVT3SRC_Pos) /*!< 0x00000200 */ +#define HSP_EVTSRC0R_EVT3SRC_2 (0x4UL << HSP_EVTSRC0R_EVT3SRC_Pos) /*!< 0x00000400 */ + +#define HSP_EVTSRC0R_EVT4SRC_Pos (12UL) +#define HSP_EVTSRC0R_EVT4SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT4SRC_Pos) /*!< 0x00007000 */ +#define HSP_EVTSRC0R_EVT4SRC HSP_EVTSRC0R_EVT4SRC_Msk /*!< EVT4SRC[2:0] bits (Event source selection for priority encoder input 4) */ +#define HSP_EVTSRC0R_EVT4SRC_0 (0x1UL << HSP_EVTSRC0R_EVT4SRC_Pos) /*!< 0x00001000 */ +#define HSP_EVTSRC0R_EVT4SRC_1 (0x2UL << HSP_EVTSRC0R_EVT4SRC_Pos) /*!< 0x00002000 */ +#define HSP_EVTSRC0R_EVT4SRC_2 (0x4UL << HSP_EVTSRC0R_EVT4SRC_Pos) /*!< 0x00004000 */ + +#define HSP_EVTSRC0R_EVT5SRC_Pos (16UL) +#define HSP_EVTSRC0R_EVT5SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT5SRC_Pos) /*!< 0x00070000 */ +#define HSP_EVTSRC0R_EVT5SRC HSP_EVTSRC0R_EVT5SRC_Msk /*!< EVT5SRC[2:0] bits (Event source selection for priority encoder input 5) */ +#define HSP_EVTSRC0R_EVT5SRC_0 (0x1UL << HSP_EVTSRC0R_EVT5SRC_Pos) /*!< 0x00010000 */ +#define HSP_EVTSRC0R_EVT5SRC_1 (0x2UL << HSP_EVTSRC0R_EVT5SRC_Pos) /*!< 0x00020000 */ +#define HSP_EVTSRC0R_EVT5SRC_2 (0x4UL << HSP_EVTSRC0R_EVT5SRC_Pos) /*!< 0x00040000 */ + +#define HSP_EVTSRC0R_EVT6SRC_Pos (20UL) +#define HSP_EVTSRC0R_EVT6SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT6SRC_Pos) /*!< 0x00700000 */ +#define HSP_EVTSRC0R_EVT6SRC HSP_EVTSRC0R_EVT6SRC_Msk /*!< EVT6SRC[2:0] bits (Event source selection for priority encoder input 6) */ +#define HSP_EVTSRC0R_EVT6SRC_0 (0x1UL << HSP_EVTSRC0R_EVT6SRC_Pos) /*!< 0x00100000 */ +#define HSP_EVTSRC0R_EVT6SRC_1 (0x2UL << HSP_EVTSRC0R_EVT6SRC_Pos) /*!< 0x00200000 */ +#define HSP_EVTSRC0R_EVT6SRC_2 (0x4UL << HSP_EVTSRC0R_EVT6SRC_Pos) /*!< 0x00400000 */ + +#define HSP_EVTSRC0R_EVT7SRC_Pos (24UL) +#define HSP_EVTSRC0R_EVT7SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT7SRC_Pos) /*!< 0x07000000 */ +#define HSP_EVTSRC0R_EVT7SRC HSP_EVTSRC0R_EVT7SRC_Msk /*!< EVT7SRC[2:0] bits (Event source selection for priority encoder input 7) */ +#define HSP_EVTSRC0R_EVT7SRC_0 (0x1UL << HSP_EVTSRC0R_EVT7SRC_Pos) /*!< 0x01000000 */ +#define HSP_EVTSRC0R_EVT7SRC_1 (0x2UL << HSP_EVTSRC0R_EVT7SRC_Pos) /*!< 0x02000000 */ +#define HSP_EVTSRC0R_EVT7SRC_2 (0x4UL << HSP_EVTSRC0R_EVT7SRC_Pos) /*!< 0x04000000 */ + +#define HSP_EVTSRC0R_EVT8SRC_Pos (28UL) +#define HSP_EVTSRC0R_EVT8SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT8SRC_Pos) /*!< 0x70000000 */ +#define HSP_EVTSRC0R_EVT8SRC HSP_EVTSRC0R_EVT8SRC_Msk /*!< EVT8SRC[2:0] bits (Event source selection for priority encoder input 8) */ +#define HSP_EVTSRC0R_EVT8SRC_0 (0x1UL << HSP_EVTSRC0R_EVT8SRC_Pos) /*!< 0x10000000 */ +#define HSP_EVTSRC0R_EVT8SRC_1 (0x2UL << HSP_EVTSRC0R_EVT8SRC_Pos) /*!< 0x20000000 */ +#define HSP_EVTSRC0R_EVT8SRC_2 (0x4UL << HSP_EVTSRC0R_EVT8SRC_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for HSP_EVTSRC1R register ********************/ +#define HSP_EVTSRC1R_EVT9SRC_Pos (0UL) +#define HSP_EVTSRC1R_EVT9SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT9SRC_Pos) /*!< 0x00000007 */ +#define HSP_EVTSRC1R_EVT9SRC HSP_EVTSRC1R_EVT9SRC_Msk /*!< EVT9SRC[2:0] bits (Event source selection for priority encoder input 9) */ +#define HSP_EVTSRC1R_EVT9SRC_0 (0x1UL << HSP_EVTSRC1R_EVT9SRC_Pos) /*!< 0x00000001 */ +#define HSP_EVTSRC1R_EVT9SRC_1 (0x2UL << HSP_EVTSRC1R_EVT9SRC_Pos) /*!< 0x00000002 */ +#define HSP_EVTSRC1R_EVT9SRC_2 (0x4UL << HSP_EVTSRC1R_EVT9SRC_Pos) /*!< 0x00000004 */ + +#define HSP_EVTSRC1R_EVT10SRC_Pos (4UL) +#define HSP_EVTSRC1R_EVT10SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT10SRC_Pos) /*!< 0x00000070 */ +#define HSP_EVTSRC1R_EVT10SRC HSP_EVTSRC1R_EVT10SRC_Msk /*!< EVT10SRC[2:0] bits (Event source selection for priority encoder input 10) */ +#define HSP_EVTSRC1R_EVT10SRC_0 (0x1UL << HSP_EVTSRC1R_EVT10SRC_Pos) /*!< 0x00000010 */ +#define HSP_EVTSRC1R_EVT10SRC_1 (0x2UL << HSP_EVTSRC1R_EVT10SRC_Pos) /*!< 0x00000020 */ +#define HSP_EVTSRC1R_EVT10SRC_2 (0x4UL << HSP_EVTSRC1R_EVT10SRC_Pos) /*!< 0x00000040 */ + +#define HSP_EVTSRC1R_EVT11SRC_Pos (8UL) +#define HSP_EVTSRC1R_EVT11SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT11SRC_Pos) /*!< 0x00000700 */ +#define HSP_EVTSRC1R_EVT11SRC HSP_EVTSRC1R_EVT11SRC_Msk /*!< EVT11SRC[2:0] bits (Event source selection for priority encoder input 11) */ +#define HSP_EVTSRC1R_EVT11SRC_0 (0x1UL << HSP_EVTSRC1R_EVT11SRC_Pos) /*!< 0x00000100 */ +#define HSP_EVTSRC1R_EVT11SRC_1 (0x2UL << HSP_EVTSRC1R_EVT11SRC_Pos) /*!< 0x00000200 */ +#define HSP_EVTSRC1R_EVT11SRC_2 (0x4UL << HSP_EVTSRC1R_EVT11SRC_Pos) /*!< 0x00000400 */ + +#define HSP_EVTSRC1R_EVT12SRC_Pos (12UL) +#define HSP_EVTSRC1R_EVT12SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT12SRC_Pos) /*!< 0x00007000 */ +#define HSP_EVTSRC1R_EVT12SRC HSP_EVTSRC1R_EVT12SRC_Msk /*!< EVT12SRC[2:0] bits (Event source selection for priority encoder input 12) */ +#define HSP_EVTSRC1R_EVT12SRC_0 (0x1UL << HSP_EVTSRC1R_EVT12SRC_Pos) /*!< 0x00001000 */ +#define HSP_EVTSRC1R_EVT12SRC_1 (0x2UL << HSP_EVTSRC1R_EVT12SRC_Pos) /*!< 0x00002000 */ +#define HSP_EVTSRC1R_EVT12SRC_2 (0x4UL << HSP_EVTSRC1R_EVT12SRC_Pos) /*!< 0x00004000 */ + +#define HSP_EVTSRC1R_EVT13SRC_Pos (16UL) +#define HSP_EVTSRC1R_EVT13SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT13SRC_Pos) /*!< 0x00070000 */ +#define HSP_EVTSRC1R_EVT13SRC HSP_EVTSRC1R_EVT13SRC_Msk /*!< EVT13SRC[2:0] bits (Event source selection for priority encoder input 13) */ +#define HSP_EVTSRC1R_EVT13SRC_0 (0x1UL << HSP_EVTSRC1R_EVT13SRC_Pos) /*!< 0x00010000 */ +#define HSP_EVTSRC1R_EVT13SRC_1 (0x2UL << HSP_EVTSRC1R_EVT13SRC_Pos) /*!< 0x00020000 */ +#define HSP_EVTSRC1R_EVT13SRC_2 (0x4UL << HSP_EVTSRC1R_EVT13SRC_Pos) /*!< 0x00040000 */ + +#define HSP_EVTSRC1R_EVT14SRC_Pos (20UL) +#define HSP_EVTSRC1R_EVT14SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT14SRC_Pos) /*!< 0x00700000 */ +#define HSP_EVTSRC1R_EVT14SRC HSP_EVTSRC1R_EVT14SRC_Msk /*!< EVT14SRC[2:0] bits (Event source selection for priority encoder input 14) */ +#define HSP_EVTSRC1R_EVT14SRC_0 (0x1UL << HSP_EVTSRC1R_EVT14SRC_Pos) /*!< 0x00100000 */ +#define HSP_EVTSRC1R_EVT14SRC_1 (0x2UL << HSP_EVTSRC1R_EVT14SRC_Pos) /*!< 0x00200000 */ +#define HSP_EVTSRC1R_EVT14SRC_2 (0x4UL << HSP_EVTSRC1R_EVT14SRC_Pos) /*!< 0x00400000 */ + +#define HSP_EVTSRC1R_EVT15SRC_Pos (24UL) +#define HSP_EVTSRC1R_EVT15SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT15SRC_Pos) /*!< 0x07000000 */ +#define HSP_EVTSRC1R_EVT15SRC HSP_EVTSRC1R_EVT15SRC_Msk /*!< EVT15SRC[2:0] bits (Event source selection for priority encoder input 15) */ +#define HSP_EVTSRC1R_EVT15SRC_0 (0x1UL << HSP_EVTSRC1R_EVT15SRC_Pos) /*!< 0x01000000 */ +#define HSP_EVTSRC1R_EVT15SRC_1 (0x2UL << HSP_EVTSRC1R_EVT15SRC_Pos) /*!< 0x02000000 */ +#define HSP_EVTSRC1R_EVT15SRC_2 (0x4UL << HSP_EVTSRC1R_EVT15SRC_Pos) /*!< 0x04000000 */ + +#define HSP_EVTSRC1R_EVT16SRC_Pos (28UL) +#define HSP_EVTSRC1R_EVT16SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT16SRC_Pos) /*!< 0x70000000 */ +#define HSP_EVTSRC1R_EVT16SRC HSP_EVTSRC1R_EVT16SRC_Msk /*!< EVT16SRC[2:0] bits (Event source selection for priority encoder input 16) */ +#define HSP_EVTSRC1R_EVT16SRC_0 (0x1UL << HSP_EVTSRC1R_EVT16SRC_Pos) /*!< 0x10000000 */ +#define HSP_EVTSRC1R_EVT16SRC_1 (0x2UL << HSP_EVTSRC1R_EVT16SRC_Pos) /*!< 0x20000000 */ +#define HSP_EVTSRC1R_EVT16SRC_2 (0x4UL << HSP_EVTSRC1R_EVT16SRC_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for HSP_EVTSRC2R register ********************/ +#define HSP_EVTSRC2R_EVT17SRC_Pos (0UL) +#define HSP_EVTSRC2R_EVT17SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT17SRC_Pos) /*!< 0x00000007 */ +#define HSP_EVTSRC2R_EVT17SRC HSP_EVTSRC2R_EVT17SRC_Msk /*!< EVT17SRC[2:0] bits (Event source selection for priority encoder input 17) */ +#define HSP_EVTSRC2R_EVT17SRC_0 (0x1UL << HSP_EVTSRC2R_EVT17SRC_Pos) /*!< 0x00000001 */ +#define HSP_EVTSRC2R_EVT17SRC_1 (0x2UL << HSP_EVTSRC2R_EVT17SRC_Pos) /*!< 0x00000002 */ +#define HSP_EVTSRC2R_EVT17SRC_2 (0x4UL << HSP_EVTSRC2R_EVT17SRC_Pos) /*!< 0x00000004 */ + +#define HSP_EVTSRC2R_EVT18SRC_Pos (4UL) +#define HSP_EVTSRC2R_EVT18SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT18SRC_Pos) /*!< 0x00000070 */ +#define HSP_EVTSRC2R_EVT18SRC HSP_EVTSRC2R_EVT18SRC_Msk /*!< EVT18SRC[2:0] bits (Event source selection for priority encoder input 18) */ +#define HSP_EVTSRC2R_EVT18SRC_0 (0x1UL << HSP_EVTSRC2R_EVT18SRC_Pos) /*!< 0x00000010 */ +#define HSP_EVTSRC2R_EVT18SRC_1 (0x2UL << HSP_EVTSRC2R_EVT18SRC_Pos) /*!< 0x00000020 */ +#define HSP_EVTSRC2R_EVT18SRC_2 (0x4UL << HSP_EVTSRC2R_EVT18SRC_Pos) /*!< 0x00000040 */ + +#define HSP_EVTSRC2R_EVT19SRC_Pos (8UL) +#define HSP_EVTSRC2R_EVT19SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT19SRC_Pos) /*!< 0x00000700 */ +#define HSP_EVTSRC2R_EVT19SRC HSP_EVTSRC2R_EVT19SRC_Msk /*!< EVT19SRC[2:0] bits (Event source selection for priority encoder input 19) */ +#define HSP_EVTSRC2R_EVT19SRC_0 (0x1UL << HSP_EVTSRC2R_EVT19SRC_Pos) /*!< 0x00000100 */ +#define HSP_EVTSRC2R_EVT19SRC_1 (0x2UL << HSP_EVTSRC2R_EVT19SRC_Pos) /*!< 0x00000200 */ +#define HSP_EVTSRC2R_EVT19SRC_2 (0x4UL << HSP_EVTSRC2R_EVT19SRC_Pos) /*!< 0x00000400 */ + +#define HSP_EVTSRC2R_EVT20SRC_Pos (12UL) +#define HSP_EVTSRC2R_EVT20SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT20SRC_Pos) /*!< 0x00007000 */ +#define HSP_EVTSRC2R_EVT20SRC HSP_EVTSRC2R_EVT20SRC_Msk /*!< EVT20SRC[2:0] bits (Event source selection for priority encoder input 20) */ +#define HSP_EVTSRC2R_EVT20SRC_0 (0x1UL << HSP_EVTSRC2R_EVT20SRC_Pos) /*!< 0x00001000 */ +#define HSP_EVTSRC2R_EVT20SRC_1 (0x2UL << HSP_EVTSRC2R_EVT20SRC_Pos) /*!< 0x00002000 */ +#define HSP_EVTSRC2R_EVT20SRC_2 (0x4UL << HSP_EVTSRC2R_EVT20SRC_Pos) /*!< 0x00004000 */ + +#define HSP_EVTSRC2R_EVT21SRC_Pos (16UL) +#define HSP_EVTSRC2R_EVT21SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT21SRC_Pos) /*!< 0x00070000 */ +#define HSP_EVTSRC2R_EVT21SRC HSP_EVTSRC2R_EVT21SRC_Msk /*!< EVT21SRC[2:0] bits (Event source selection for priority encoder input 21) */ +#define HSP_EVTSRC2R_EVT21SRC_0 (0x1UL << HSP_EVTSRC2R_EVT21SRC_Pos) /*!< 0x00010000 */ +#define HSP_EVTSRC2R_EVT21SRC_1 (0x2UL << HSP_EVTSRC2R_EVT21SRC_Pos) /*!< 0x00020000 */ +#define HSP_EVTSRC2R_EVT21SRC_2 (0x4UL << HSP_EVTSRC2R_EVT21SRC_Pos) /*!< 0x00040000 */ + +#define HSP_EVTSRC2R_EVT22SRC_Pos (20UL) +#define HSP_EVTSRC2R_EVT22SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT22SRC_Pos) /*!< 0x00700000 */ +#define HSP_EVTSRC2R_EVT22SRC HSP_EVTSRC2R_EVT22SRC_Msk /*!< EVT22SRC[2:0] bits (Event source selection for priority encoder input 22) */ +#define HSP_EVTSRC2R_EVT22SRC_0 (0x1UL << HSP_EVTSRC2R_EVT22SRC_Pos) /*!< 0x00100000 */ +#define HSP_EVTSRC2R_EVT22SRC_1 (0x2UL << HSP_EVTSRC2R_EVT22SRC_Pos) /*!< 0x00200000 */ +#define HSP_EVTSRC2R_EVT22SRC_2 (0x4UL << HSP_EVTSRC2R_EVT22SRC_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for HSP_BUFFCFGR register ********************/ +#define HSP_BUFFCFGR_BUFF0DIR_Pos (0UL) +#define HSP_BUFFCFGR_BUFF0DIR_Msk (0x1UL << HSP_BUFFCFGR_BUFF0DIR_Pos) /*!< 0x00000001 */ +#define HSP_BUFFCFGR_BUFF0DIR HSP_BUFFCFGR_BUFF0DIR_Msk /*!< BUFF0DIR (Direction selection of BUFF0 (1)) */ + +#define HSP_BUFFCFGR_BUFF1DIR_Pos (1UL) +#define HSP_BUFFCFGR_BUFF1DIR_Msk (0x1UL << HSP_BUFFCFGR_BUFF1DIR_Pos) /*!< 0x00000002 */ +#define HSP_BUFFCFGR_BUFF1DIR HSP_BUFFCFGR_BUFF1DIR_Msk /*!< BUFF1DIR (Direction selection of BUFF1 (1)) */ + +#define HSP_BUFFCFGR_BUFF2DIR_Pos (2UL) +#define HSP_BUFFCFGR_BUFF2DIR_Msk (0x1UL << HSP_BUFFCFGR_BUFF2DIR_Pos) /*!< 0x00000004 */ +#define HSP_BUFFCFGR_BUFF2DIR HSP_BUFFCFGR_BUFF2DIR_Msk /*!< BUFF2DIR (Direction selection of BUFF2 (1)) */ + +#define HSP_BUFFCFGR_BUFF3DIR_Pos (3UL) +#define HSP_BUFFCFGR_BUFF3DIR_Msk (0x1UL << HSP_BUFFCFGR_BUFF3DIR_Pos) /*!< 0x00000008 */ +#define HSP_BUFFCFGR_BUFF3DIR HSP_BUFFCFGR_BUFF3DIR_Msk /*!< BUFF3DIR (Direction selection of BUFF3 (1)) */ + +#define HSP_BUFFCFGR_I2FEN_Pos (8UL) +#define HSP_BUFFCFGR_I2FEN_Msk (0x1UL << HSP_BUFFCFGR_I2FEN_Pos) /*!< 0x00000100 */ +#define HSP_BUFFCFGR_I2FEN HSP_BUFFCFGR_I2FEN_Msk /*!< I2FEN (integer to float32 conversion (1)) */ + +#define HSP_BUFFCFGR_COMB0_Pos (16UL) +#define HSP_BUFFCFGR_COMB0_Msk (0x1UL << HSP_BUFFCFGR_COMB0_Pos) /*!< 0x00010000 */ +#define HSP_BUFFCFGR_COMB0 HSP_BUFFCFGR_COMB0_Msk /*!< COMB0 (BUFCMB control for buff_evt[0] (1)) */ + +#define HSP_BUFFCFGR_COMB1_Pos (17UL) +#define HSP_BUFFCFGR_COMB1_Msk (0x1UL << HSP_BUFFCFGR_COMB1_Pos) /*!< 0x00020000 */ +#define HSP_BUFFCFGR_COMB1 HSP_BUFFCFGR_COMB1_Msk /*!< COMB1 (BUFCMB control for buff_evt[1] (1)) */ + +#define HSP_BUFFCFGR_COMB2_Pos (18UL) +#define HSP_BUFFCFGR_COMB2_Msk (0x1UL << HSP_BUFFCFGR_COMB2_Pos) /*!< 0x00040000 */ +#define HSP_BUFFCFGR_COMB2 HSP_BUFFCFGR_COMB2_Msk /*!< COMB2 (BUFCMB control for buff_evt[2] ) */ + +/******************** Bit definition for HSP_BUFFxDR register ********************/ +#define HSP_BUFFDR_BUFFDAT_Pos (0UL) +#define HSP_BUFFDR_BUFFDAT_Msk (0xFFFFFFFFUL << HSP_BUFFDR_BUFFDAT_Pos) /*!< 0xFFFFFFFF */ +#define HSP_BUFFDR_BUFFDAT HSP_BUFFDR_BUFFDAT_Msk /*!< BUFFDAT[31:0] bits (Data buffer) */ + +/******************** Bit definition for HSP_TRGINCFGR register ********************/ +#define HSP_TRGINCFGR_TRG0POL_Pos (0UL) +#define HSP_TRGINCFGR_TRG0POL_Msk (0x1UL << HSP_TRGINCFGR_TRG0POL_Pos) /*!< 0x00000001 */ +#define HSP_TRGINCFGR_TRG0POL HSP_TRGINCFGR_TRG0POL_Msk /*!< TRG0POL (Polarity selection for TRGIN0) */ + +#define HSP_TRGINCFGR_TRG1POL_Pos (1UL) +#define HSP_TRGINCFGR_TRG1POL_Msk (0x1UL << HSP_TRGINCFGR_TRG1POL_Pos) /*!< 0x00000002 */ +#define HSP_TRGINCFGR_TRG1POL HSP_TRGINCFGR_TRG1POL_Msk /*!< TRG1POL (Polarity selection for TRGIN1) */ + +#define HSP_TRGINCFGR_TRG2POL_Pos (2UL) +#define HSP_TRGINCFGR_TRG2POL_Msk (0x1UL << HSP_TRGINCFGR_TRG2POL_Pos) /*!< 0x00000004 */ +#define HSP_TRGINCFGR_TRG2POL HSP_TRGINCFGR_TRG2POL_Msk /*!< TRG2POL (Polarity selection for TRGIN2) */ + +#define HSP_TRGINCFGR_TRG3POL_Pos (3UL) +#define HSP_TRGINCFGR_TRG3POL_Msk (0x1UL << HSP_TRGINCFGR_TRG3POL_Pos) /*!< 0x00000008 */ +#define HSP_TRGINCFGR_TRG3POL HSP_TRGINCFGR_TRG3POL_Msk /*!< TRG3POL (Polarity selection for TRGIN3) */ + +#define HSP_TRGINCFGR_TRG4POL_Pos (4UL) +#define HSP_TRGINCFGR_TRG4POL_Msk (0x1UL << HSP_TRGINCFGR_TRG4POL_Pos) /*!< 0x00000010 */ +#define HSP_TRGINCFGR_TRG4POL HSP_TRGINCFGR_TRG4POL_Msk /*!< TRG4POL (Polarity selection for TRGIN4) */ + +#define HSP_TRGINCFGR_TRG5POL_Pos (5UL) +#define HSP_TRGINCFGR_TRG5POL_Msk (0x1UL << HSP_TRGINCFGR_TRG5POL_Pos) /*!< 0x00000020 */ +#define HSP_TRGINCFGR_TRG5POL HSP_TRGINCFGR_TRG5POL_Msk /*!< TRG5POL (Polarity selection for TRGIN5) */ + +#define HSP_TRGINCFGR_TRG6POL_Pos (6UL) +#define HSP_TRGINCFGR_TRG6POL_Msk (0x1UL << HSP_TRGINCFGR_TRG6POL_Pos) /*!< 0x00000040 */ +#define HSP_TRGINCFGR_TRG6POL HSP_TRGINCFGR_TRG6POL_Msk /*!< TRG6POL (Polarity selection for TRGIN6) */ + +#define HSP_TRGINCFGR_TRG7POL_Pos (7UL) +#define HSP_TRGINCFGR_TRG7POL_Msk (0x1UL << HSP_TRGINCFGR_TRG7POL_Pos) /*!< 0x00000080 */ +#define HSP_TRGINCFGR_TRG7POL HSP_TRGINCFGR_TRG7POL_Msk /*!< TRG7POL (Polarity selection for TRGIN7) */ + +#define HSP_TRGINCFGR_TRG8POL_Pos (8UL) +#define HSP_TRGINCFGR_TRG8POL_Msk (0x1UL << HSP_TRGINCFGR_TRG8POL_Pos) /*!< 0x00000100 */ +#define HSP_TRGINCFGR_TRG8POL HSP_TRGINCFGR_TRG8POL_Msk /*!< TRG8POL (Polarity selection for TRGIN8) */ + +#define HSP_TRGINCFGR_TRG9POL_Pos (9UL) +#define HSP_TRGINCFGR_TRG9POL_Msk (0x1UL << HSP_TRGINCFGR_TRG9POL_Pos) /*!< 0x00000200 */ +#define HSP_TRGINCFGR_TRG9POL HSP_TRGINCFGR_TRG9POL_Msk /*!< TRG9POL (Polarity selection for TRGIN9) */ + +/******************** Bit definition for HSP_TRGOCFGR register ********************/ +#define HSP_TRGOCFGR_TRGO0SRC_Pos (0UL) +#define HSP_TRGOCFGR_TRGO0SRC_Msk (0x3UL << HSP_TRGOCFGR_TRGO0SRC_Pos) /*!< 0x00000003 */ +#define HSP_TRGOCFGR_TRGO0SRC HSP_TRGOCFGR_TRGO0SRC_Msk /*!< TRGO0SRC[1:0] bits (Trigger source selection for hsp_trg_out[0] (1)) */ +#define HSP_TRGOCFGR_TRGO0SRC_0 (0x1UL << HSP_TRGOCFGR_TRGO0SRC_Pos) /*!< 0x00000001 */ +#define HSP_TRGOCFGR_TRGO0SRC_1 (0x2UL << HSP_TRGOCFGR_TRGO0SRC_Pos) /*!< 0x00000002 */ + +#define HSP_TRGOCFGR_TRGO1SRC_Pos (2UL) +#define HSP_TRGOCFGR_TRGO1SRC_Msk (0x3UL << HSP_TRGOCFGR_TRGO1SRC_Pos) /*!< 0x0000000C */ +#define HSP_TRGOCFGR_TRGO1SRC HSP_TRGOCFGR_TRGO1SRC_Msk /*!< TRGO1SRC[1:0] bits (Trigger source selection for hsp_trg_out[1] (1)) */ +#define HSP_TRGOCFGR_TRGO1SRC_0 (0x1UL << HSP_TRGOCFGR_TRGO1SRC_Pos) /*!< 0x00000004 */ +#define HSP_TRGOCFGR_TRGO1SRC_1 (0x2UL << HSP_TRGOCFGR_TRGO1SRC_Pos) /*!< 0x00000008 */ + +#define HSP_TRGOCFGR_TRGO2SRC_Pos (4UL) +#define HSP_TRGOCFGR_TRGO2SRC_Msk (0x3UL << HSP_TRGOCFGR_TRGO2SRC_Pos) /*!< 0x00000030 */ +#define HSP_TRGOCFGR_TRGO2SRC HSP_TRGOCFGR_TRGO2SRC_Msk /*!< TRGO2SRC[1:0] bits (Trigger source selection for hsp_trg_out[2] (1)) */ +#define HSP_TRGOCFGR_TRGO2SRC_0 (0x1UL << HSP_TRGOCFGR_TRGO2SRC_Pos) /*!< 0x00000010 */ +#define HSP_TRGOCFGR_TRGO2SRC_1 (0x2UL << HSP_TRGOCFGR_TRGO2SRC_Pos) /*!< 0x00000020 */ + +#define HSP_TRGOCFGR_TRGO3SRC_Pos (6UL) +#define HSP_TRGOCFGR_TRGO3SRC_Msk (0x3UL << HSP_TRGOCFGR_TRGO3SRC_Pos) /*!< 0x000000C0 */ +#define HSP_TRGOCFGR_TRGO3SRC HSP_TRGOCFGR_TRGO3SRC_Msk /*!< TRGO3SRC[1:0] bits (Trigger source selection for hsp_trg_out[3] ) */ +#define HSP_TRGOCFGR_TRGO3SRC_0 (0x1UL << HSP_TRGOCFGR_TRGO3SRC_Pos) /*!< 0x00000040 */ +#define HSP_TRGOCFGR_TRGO3SRC_1 (0x2UL << HSP_TRGOCFGR_TRGO3SRC_Pos) /*!< 0x00000080 */ + +/******************** Bit definition for HSP_CSEGR register ********************/ +#define HSP_CSEGR_CSEVT_Pos (1UL) +#define HSP_CSEGR_CSEVT_Msk (0x3FFFFFUL << HSP_CSEGR_CSEVT_Pos) /*!< 0x007FFFFE */ +#define HSP_CSEGR_CSEVT HSP_CSEGR_CSEVT_Msk /*!< CSEVT[21:0] bits (CPU Shared Software Event ) */ +#define HSP_CSEGR_CSEVT_0 (0x0001UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000002 */ +#define HSP_CSEGR_CSEVT_1 (0x0002UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000004 */ +#define HSP_CSEGR_CSEVT_2 (0x0004UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000008 */ +#define HSP_CSEGR_CSEVT_3 (0x0008UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000010 */ +#define HSP_CSEGR_CSEVT_4 (0x0010UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000020 */ +#define HSP_CSEGR_CSEVT_5 (0x0020UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000040 */ +#define HSP_CSEGR_CSEVT_6 (0x0040UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000080 */ +#define HSP_CSEGR_CSEVT_7 (0x0080UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000100 */ +#define HSP_CSEGR_CSEVT_8 (0x0100UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000200 */ +#define HSP_CSEGR_CSEVT_9 (0x0200UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000400 */ +#define HSP_CSEGR_CSEVT_10 (0x0400UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000800 */ +#define HSP_CSEGR_CSEVT_11 (0x0800UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00001000 */ +#define HSP_CSEGR_CSEVT_12 (0x1000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00002000 */ +#define HSP_CSEGR_CSEVT_13 (0x2000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00004000 */ +#define HSP_CSEGR_CSEVT_14 (0x4000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00008000 */ +#define HSP_CSEGR_CSEVT_15 (0x8000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00010000 */ +#define HSP_CSEGR_CSEVT_16 (0x10000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00020000 */ +#define HSP_CSEGR_CSEVT_17 (0x20000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00040000 */ +#define HSP_CSEGR_CSEVT_18 (0x40000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00080000 */ +#define HSP_CSEGR_CSEVT_19 (0x80000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00100000 */ +#define HSP_CSEGR_CSEVT_20 (0x100000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00200000 */ +#define HSP_CSEGR_CSEVT_21 (0x200000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for HSP_CDEGR register ********************/ +#define HSP_CDEGR_CTSKN_Pos (0UL) +#define HSP_CDEGR_CTSKN_Msk (0x3FUL << HSP_CDEGR_CTSKN_Pos) /*!< 0x0000003F */ +#define HSP_CDEGR_CTSKN HSP_CDEGR_CTSKN_Msk /*!< CTSKN[5:0] bits (CPU Task number) */ + +#define HSP_CDEGR_CDEGBSY_Pos (31UL) +#define HSP_CDEGR_CDEGBSY_Msk (0x1UL << HSP_CDEGR_CDEGBSY_Pos) /*!< 0x80000000 */ +#define HSP_CDEGR_CDEGBSY HSP_CDEGR_CDEGBSY_Msk /*!< CDEGBSY (CPU dedicated event generator busy) */ + +/******************** Bit definition for HSP_TRGINSELR0 register ********************/ +#define HSP_TRGINSELR0_TRG0SEL_Pos (0UL) +#define HSP_TRGINSELR0_TRG0SEL_Msk (0x3FUL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x0000003F */ +#define HSP_TRGINSELR0_TRG0SEL HSP_TRGINSELR0_TRG0SEL_Msk /*!< TRG0SEL[5:0] bits (Input trigger selection for TRGIN0) */ +#define HSP_TRGINSELR0_TRG0SEL_0 (0x01UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000001 */ +#define HSP_TRGINSELR0_TRG0SEL_1 (0x02UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000002 */ +#define HSP_TRGINSELR0_TRG0SEL_2 (0x04UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000004 */ +#define HSP_TRGINSELR0_TRG0SEL_3 (0x08UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000008 */ +#define HSP_TRGINSELR0_TRG0SEL_4 (0x10UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000010 */ +#define HSP_TRGINSELR0_TRG0SEL_5 (0x20UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000020 */ + +#define HSP_TRGINSELR0_TRG1SEL_Pos (8UL) +#define HSP_TRGINSELR0_TRG1SEL_Msk (0x3FUL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00003F00 */ +#define HSP_TRGINSELR0_TRG1SEL HSP_TRGINSELR0_TRG1SEL_Msk /*!< TRG1SEL[5:0] bits (Input trigger selection for TRGIN1) */ +#define HSP_TRGINSELR0_TRG1SEL_0 (0x01UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00000100 */ +#define HSP_TRGINSELR0_TRG1SEL_1 (0x02UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00000200 */ +#define HSP_TRGINSELR0_TRG1SEL_2 (0x04UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00000400 */ +#define HSP_TRGINSELR0_TRG1SEL_3 (0x08UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00000800 */ +#define HSP_TRGINSELR0_TRG1SEL_4 (0x10UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00001000 */ +#define HSP_TRGINSELR0_TRG1SEL_5 (0x20UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00002000 */ + +#define HSP_TRGINSELR0_TRG2SEL_Pos (16UL) +#define HSP_TRGINSELR0_TRG2SEL_Msk (0x3FUL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x003F0000 */ +#define HSP_TRGINSELR0_TRG2SEL HSP_TRGINSELR0_TRG2SEL_Msk /*!< TRG2SEL[5:0] bits (Input trigger selection for TRGIN2) */ +#define HSP_TRGINSELR0_TRG2SEL_0 (0x01UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00010000 */ +#define HSP_TRGINSELR0_TRG2SEL_1 (0x02UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00020000 */ +#define HSP_TRGINSELR0_TRG2SEL_2 (0x04UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00040000 */ +#define HSP_TRGINSELR0_TRG2SEL_3 (0x08UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00080000 */ +#define HSP_TRGINSELR0_TRG2SEL_4 (0x10UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00100000 */ +#define HSP_TRGINSELR0_TRG2SEL_5 (0x20UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00200000 */ + +#define HSP_TRGINSELR0_TRG3SEL_Pos (24UL) +#define HSP_TRGINSELR0_TRG3SEL_Msk (0x3FUL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x3F000000 */ +#define HSP_TRGINSELR0_TRG3SEL HSP_TRGINSELR0_TRG3SEL_Msk /*!< TRG3SEL[5:0] bits (Input trigger selection for TRGIN3) */ +#define HSP_TRGINSELR0_TRG3SEL_0 (0x01UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x01000000 */ +#define HSP_TRGINSELR0_TRG3SEL_1 (0x02UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x02000000 */ +#define HSP_TRGINSELR0_TRG3SEL_2 (0x04UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x04000000 */ +#define HSP_TRGINSELR0_TRG3SEL_3 (0x08UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x08000000 */ +#define HSP_TRGINSELR0_TRG3SEL_4 (0x10UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x10000000 */ +#define HSP_TRGINSELR0_TRG3SEL_5 (0x20UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for HSP_TRGINSELR1 register ********************/ +#define HSP_TRGINSELR1_TRG4SEL_Pos (0UL) +#define HSP_TRGINSELR1_TRG4SEL_Msk (0x3FUL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x0000003F */ +#define HSP_TRGINSELR1_TRG4SEL HSP_TRGINSELR1_TRG4SEL_Msk /*!< TRG4SEL[5:0] bits (Input trigger selection for TRGIN4) */ +#define HSP_TRGINSELR1_TRG4SEL_0 (0x01UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000001 */ +#define HSP_TRGINSELR1_TRG4SEL_1 (0x02UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000002 */ +#define HSP_TRGINSELR1_TRG4SEL_2 (0x04UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000004 */ +#define HSP_TRGINSELR1_TRG4SEL_3 (0x08UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000008 */ +#define HSP_TRGINSELR1_TRG4SEL_4 (0x10UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000010 */ +#define HSP_TRGINSELR1_TRG4SEL_5 (0x20UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000020 */ + +#define HSP_TRGINSELR1_TRG5SEL_Pos (8UL) +#define HSP_TRGINSELR1_TRG5SEL_Msk (0x3FUL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00003F00 */ +#define HSP_TRGINSELR1_TRG5SEL HSP_TRGINSELR1_TRG5SEL_Msk /*!< TRG5SEL[5:0] bits (Input trigger selection for TRGIN5) */ +#define HSP_TRGINSELR1_TRG5SEL_0 (0x01UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00000100 */ +#define HSP_TRGINSELR1_TRG5SEL_1 (0x02UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00000200 */ +#define HSP_TRGINSELR1_TRG5SEL_2 (0x04UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00000400 */ +#define HSP_TRGINSELR1_TRG5SEL_3 (0x08UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00000800 */ +#define HSP_TRGINSELR1_TRG5SEL_4 (0x10UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00001000 */ +#define HSP_TRGINSELR1_TRG5SEL_5 (0x20UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00002000 */ + +#define HSP_TRGINSELR1_TRG6SEL_Pos (16UL) +#define HSP_TRGINSELR1_TRG6SEL_Msk (0x3FUL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x003F0000 */ +#define HSP_TRGINSELR1_TRG6SEL HSP_TRGINSELR1_TRG6SEL_Msk /*!< TRG6SEL[5:0] bits (Input trigger selection for TRGIN6) */ +#define HSP_TRGINSELR1_TRG6SEL_0 (0x01UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00010000 */ +#define HSP_TRGINSELR1_TRG6SEL_1 (0x02UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00020000 */ +#define HSP_TRGINSELR1_TRG6SEL_2 (0x04UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00040000 */ +#define HSP_TRGINSELR1_TRG6SEL_3 (0x08UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00080000 */ +#define HSP_TRGINSELR1_TRG6SEL_4 (0x10UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00100000 */ +#define HSP_TRGINSELR1_TRG6SEL_5 (0x20UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00200000 */ + +#define HSP_TRGINSELR1_TRG7SEL_Pos (24UL) +#define HSP_TRGINSELR1_TRG7SEL_Msk (0x3FUL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x3F000000 */ +#define HSP_TRGINSELR1_TRG7SEL HSP_TRGINSELR1_TRG7SEL_Msk /*!< TRG7SEL[5:0] bits (Input trigger selection for TRGIN7) */ +#define HSP_TRGINSELR1_TRG7SEL_0 (0x01UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x01000000 */ +#define HSP_TRGINSELR1_TRG7SEL_1 (0x02UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x02000000 */ +#define HSP_TRGINSELR1_TRG7SEL_2 (0x04UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x04000000 */ +#define HSP_TRGINSELR1_TRG7SEL_3 (0x08UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x08000000 */ +#define HSP_TRGINSELR1_TRG7SEL_4 (0x10UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x10000000 */ +#define HSP_TRGINSELR1_TRG7SEL_5 (0x20UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for HSP_TRGINSELR2 register ********************/ +#define HSP_TRGINSELR2_TRG8SEL_Pos (0UL) +#define HSP_TRGINSELR2_TRG8SEL_Msk (0x3FUL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x0000003F */ +#define HSP_TRGINSELR2_TRG8SEL HSP_TRGINSELR2_TRG8SEL_Msk /*!< TRG8SEL[5:0] bits (Input trigger selection for TRGIN8) */ +#define HSP_TRGINSELR2_TRG8SEL_0 (0x01UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000001 */ +#define HSP_TRGINSELR2_TRG8SEL_1 (0x02UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000002 */ +#define HSP_TRGINSELR2_TRG8SEL_2 (0x04UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000004 */ +#define HSP_TRGINSELR2_TRG8SEL_3 (0x08UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000008 */ +#define HSP_TRGINSELR2_TRG8SEL_4 (0x10UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000010 */ +#define HSP_TRGINSELR2_TRG8SEL_5 (0x20UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000020 */ + +#define HSP_TRGINSELR2_TRG9SEL_Pos (8UL) +#define HSP_TRGINSELR2_TRG9SEL_Msk (0x3FUL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00003F00 */ +#define HSP_TRGINSELR2_TRG9SEL HSP_TRGINSELR2_TRG9SEL_Msk /*!< TRG9SEL[5:0] bits (Input trigger selection for TRGIN9) */ +#define HSP_TRGINSELR2_TRG9SEL_0 (0x01UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00000100 */ +#define HSP_TRGINSELR2_TRG9SEL_1 (0x02UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00000200 */ +#define HSP_TRGINSELR2_TRG9SEL_2 (0x04UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00000400 */ +#define HSP_TRGINSELR2_TRG9SEL_3 (0x08UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00000800 */ +#define HSP_TRGINSELR2_TRG9SEL_4 (0x10UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00001000 */ +#define HSP_TRGINSELR2_TRG9SEL_5 (0x20UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00002000 */ + +/******************** Bit definition for HSP_BKOxCFGR register ********************/ +#define HSP_BKOCFGR_ACCEREN_Pos (0U) +#define HSP_BKOCFGR_ACCEREN_Msk (0x1UL << HSP_BKOCFGR_ACCEREN_Pos) /*!< 0x00000001 */ +#define HSP_BKOCFGR_ACCEREN HSP_BKOCFGR_ACCEREN_Msk /*!< ACCEREN (Access error break enable for ACCERRF (1)) */ + +#define HSP_BKOCFGR_FPUEREN_Pos (1U) +#define HSP_BKOCFGR_FPUEREN_Msk (0x1UL << HSP_BKOCFGR_FPUEREN_Pos) /*!< 0x00000002 */ +#define HSP_BKOCFGR_FPUEREN HSP_BKOCFGR_FPUEREN_Msk /*!< FPUEREN (FPU error break enable for FPUERRF (1)) */ + +#define HSP_BKOCFGR_OPCEREN_Pos (2U) +#define HSP_BKOCFGR_OPCEREN_Msk (0x1UL << HSP_BKOCFGR_OPCEREN_Pos) /*!< 0x00000004 */ +#define HSP_BKOCFGR_OPCEREN HSP_BKOCFGR_OPCEREN_Msk /*!< OPCEREN (Opcode error break enable for OPCOERRF ) */ + +#define HSP_BKOCFGR_PFCT28EN_Pos (4U) +#define HSP_BKOCFGR_PFCT28EN_Msk (0x1UL << HSP_BKOCFGR_PFCT28EN_Pos) /*!< 0x00000010 */ +#define HSP_BKOCFGR_PFCT28EN HSP_BKOCFGR_PFCT28EN_Msk /*!< PFCT28EN (Processing function flag break enable for PFCTF[28] (1)) */ + +#define HSP_BKOCFGR_PFCT29EN_Pos (5U) +#define HSP_BKOCFGR_PFCT29EN_Msk (0x1UL << HSP_BKOCFGR_PFCT29EN_Pos) /*!< 0x00000020 */ +#define HSP_BKOCFGR_PFCT29EN HSP_BKOCFGR_PFCT29EN_Msk /*!< PFCT29EN (Processing function flag break enable for PFCTF[29] (1)) */ + +#define HSP_BKOCFGR_PFCT30EN_Pos (6U) +#define HSP_BKOCFGR_PFCT30EN_Msk (0x1UL << HSP_BKOCFGR_PFCT30EN_Pos) /*!< 0x00000040 */ +#define HSP_BKOCFGR_PFCT30EN HSP_BKOCFGR_PFCT30EN_Msk /*!< PFCT30EN (Processing function flag break enable for PFCTF[30] (1)) */ + +#define HSP_BKOCFGR_PFCT31EN_Pos (7U) +#define HSP_BKOCFGR_PFCT31EN_Msk (0x1UL << HSP_BKOCFGR_PFCT31EN_Pos) /*!< 0x00000080 */ +#define HSP_BKOCFGR_PFCT31EN HSP_BKOCFGR_PFCT31EN_Msk /*!< PFCT31EN (Processing function flag break enable for PFCTF[31] (1)) */ + +#define HSP_BKOCFGR_FWEREN_Pos (12U) +#define HSP_BKOCFGR_FWEREN_Msk (0x1UL << HSP_BKOCFGR_FWEREN_Pos) /*!< 0x00001000 */ +#define HSP_BKOCFGR_FWEREN HSP_BKOCFGR_FWEREN_Msk /*!< FWEREN (Firmware error break enable for FWERRF (1)) */ + +#define HSP_BKOCFGR_HDEGOVEN_Pos (13U) +#define HSP_BKOCFGR_HDEGOVEN_Msk (0x1UL << HSP_BKOCFGR_HDEGOVEN_Pos) /*!< 0x00002000 */ +#define HSP_BKOCFGR_HDEGOVEN HSP_BKOCFGR_HDEGOVEN_Msk /*!< HDEGOVEN (HSP dedicated event generator overrun break enable for HDEGOVRF (1)) */ + +/******************** Bit definition for HSP_BKICFGR register ********************/ +#define HSP_BKICFGR_ACCEREN_Pos (0UL) +#define HSP_BKICFGR_ACCEREN_Msk (0x1UL << HSP_BKICFGR_ACCEREN_Pos) /*!< 0x00000001 */ +#define HSP_BKICFGR_ACCEREN HSP_BKICFGR_ACCEREN_Msk /*!< ACCEREN (Access error break enable for ACCERRF (1)) */ + +#define HSP_BKICFGR_FPUEREN_Pos (1UL) +#define HSP_BKICFGR_FPUEREN_Msk (0x1UL << HSP_BKICFGR_FPUEREN_Pos) /*!< 0x00000002 */ +#define HSP_BKICFGR_FPUEREN HSP_BKICFGR_FPUEREN_Msk /*!< FPUEREN (FPU error break enable for FPUERRF (1)) */ + +#define HSP_BKICFGR_OPCEREN_Pos (2UL) +#define HSP_BKICFGR_OPCEREN_Msk (0x1UL << HSP_BKICFGR_OPCEREN_Pos) /*!< 0x00000004 */ +#define HSP_BKICFGR_OPCEREN HSP_BKICFGR_OPCEREN_Msk /*!< OPCEREN (Opcode error break enable for OPCOERRF ) */ + +#define HSP_BKICFGR_PFCT28EN_Pos (4UL) +#define HSP_BKICFGR_PFCT28EN_Msk (0x1UL << HSP_BKICFGR_PFCT28EN_Pos) /*!< 0x00000010 */ +#define HSP_BKICFGR_PFCT28EN HSP_BKICFGR_PFCT28EN_Msk /*!< PFCT28EN (Processing function flag break enable for PFCTF[28] (1)) */ + +#define HSP_BKICFGR_PFCT29EN_Pos (5UL) +#define HSP_BKICFGR_PFCT29EN_Msk (0x1UL << HSP_BKICFGR_PFCT29EN_Pos) /*!< 0x00000020 */ +#define HSP_BKICFGR_PFCT29EN HSP_BKICFGR_PFCT29EN_Msk /*!< PFCT29EN (Processing function flag break enable for PFCTF[29] (1)) */ + +#define HSP_BKICFGR_PFCT30EN_Pos (6UL) +#define HSP_BKICFGR_PFCT30EN_Msk (0x1UL << HSP_BKICFGR_PFCT30EN_Pos) /*!< 0x00000040 */ +#define HSP_BKICFGR_PFCT30EN HSP_BKICFGR_PFCT30EN_Msk /*!< PFCT30EN (Processing function flag break enable for PFCTF[30] (1)) */ + +#define HSP_BKICFGR_PFCT31EN_Pos (7UL) +#define HSP_BKICFGR_PFCT31EN_Msk (0x1UL << HSP_BKICFGR_PFCT31EN_Pos) /*!< 0x00000080 */ +#define HSP_BKICFGR_PFCT31EN HSP_BKICFGR_PFCT31EN_Msk /*!< PFCT31EN (Processing function flag break enable for PFCTF[31] (1)) */ + +#define HSP_BKICFGR_FWEREN_Pos (12UL) +#define HSP_BKICFGR_FWEREN_Msk (0x1UL << HSP_BKICFGR_FWEREN_Pos) /*!< 0x00001000 */ +#define HSP_BKICFGR_FWEREN HSP_BKICFGR_FWEREN_Msk /*!< FWEREN (Firmware error break enable for FWERRF (1)) */ + +#define HSP_BKICFGR_HDEGOVEN_Pos (13UL) +#define HSP_BKICFGR_HDEGOVEN_Msk (0x1UL << HSP_BKICFGR_HDEGOVEN_Pos) /*!< 0x00002000 */ +#define HSP_BKICFGR_HDEGOVEN HSP_BKICFGR_HDEGOVEN_Msk /*!< HDEGOVEN (HSP dedicated event generator overrun break enable for HDEGOVRF (1)) */ + +#define HSP_BKICFGR_FSATEN_Pos (14UL) +#define HSP_BKICFGR_FSATEN_Msk (0x1UL << HSP_BKICFGR_FSATEN_Pos) /*!< 0x00004000 */ +#define HSP_BKICFGR_FSATEN HSP_BKICFGR_FSATEN_Msk /*!< FSATEN (FPU saturation break enable for FPUSATF (1)) */ + +#define HSP_BKICFGR_SSEN_Pos (17UL) +#define HSP_BKICFGR_SSEN_Msk (0x1UL << HSP_BKICFGR_SSEN_Pos) /*!< 0x00020000 */ +#define HSP_BKICFGR_SSEN HSP_BKICFGR_SSEN_Msk /*!< SSEN (Single step enable (1)) */ + +/******************** Bit definition for HSP_FWERR register ********************/ +#define HSP_FWERR_FWERRN_Pos (0UL) +#define HSP_FWERR_FWERRN_Msk (0x3FFUL << HSP_FWERR_FWERRN_Pos) /*!< 0x000003FF */ +#define HSP_FWERR_FWERRN HSP_FWERR_FWERRN_Msk /*!< FWERRN[9:0] bits (Firmware error number) */ + +/******************** Bit definition for HSP_PARAMR0 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR0_PARAM_Pos (0UL) +#define HSP_PARAMR0_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR0_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR0_PARAM HSP_PARAMR0_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR1 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR1_PARAM_Pos (0UL) +#define HSP_PARAMR1_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR1_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR1_PARAM HSP_PARAMR1_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR2 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR2_PARAM_Pos (0UL) +#define HSP_PARAMR2_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR2_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR2_PARAM HSP_PARAMR2_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR3 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR3_PARAM_Pos (0UL) +#define HSP_PARAMR3_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR3_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR3_PARAM HSP_PARAMR3_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR4 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR4_PARAM_Pos (0UL) +#define HSP_PARAMR4_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR4_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR4_PARAM HSP_PARAMR4_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR5 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR5_PARAM_Pos (0UL) +#define HSP_PARAMR5_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR5_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR5_PARAM HSP_PARAMR5_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR6 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR6_PARAM_Pos (0UL) +#define HSP_PARAMR6_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR6_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR6_PARAM HSP_PARAMR6_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR7 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR7_PARAM_Pos (0UL) +#define HSP_PARAMR7_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR7_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR7_PARAM HSP_PARAMR7_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR8 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR8_PARAM_Pos (0UL) +#define HSP_PARAMR8_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR8_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR8_PARAM HSP_PARAMR8_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR9 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR9_PARAM_Pos (0UL) +#define HSP_PARAMR9_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR9_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR9_PARAM HSP_PARAMR9_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR10 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR10_PARAM_Pos (0UL) +#define HSP_PARAMR10_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR10_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR10_PARAM HSP_PARAMR10_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR11 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR11_PARAM_Pos (0UL) +#define HSP_PARAMR11_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR11_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR11_PARAM HSP_PARAMR11_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR12 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR12_PARAM_Pos (0UL) +#define HSP_PARAMR12_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR12_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR12_PARAM HSP_PARAMR12_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR13 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR13_PARAM_Pos (0UL) +#define HSP_PARAMR13_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR13_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR13_PARAM HSP_PARAMR13_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR14 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR14_PARAM_Pos (0UL) +#define HSP_PARAMR14_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR14_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR14_PARAM HSP_PARAMR14_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR15 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR15_PARAM_Pos (0UL) +#define HSP_PARAMR15_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR15_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR15_PARAM HSP_PARAMR15_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_SPE_IER register ********************/ +#define HSP_SPE_IER_C2HMRDYIE_Pos (0UL) +#define HSP_SPE_IER_C2HMRDYIE_Msk (0x1UL << HSP_SPE_IER_C2HMRDYIE_Pos) /*!< 0x00000001 */ +#define HSP_SPE_IER_C2HMRDYIE HSP_SPE_IER_C2HMRDYIE_Msk /*!< C2HMRDYIE (CPU to SPE message ready interrupt enable) */ + +#define HSP_SPE_IER_H2CMFREEIE_Pos (1UL) +#define HSP_SPE_IER_H2CMFREEIE_Msk (0x1UL << HSP_SPE_IER_H2CMFREEIE_Pos) /*!< 0x00000002 */ +#define HSP_SPE_IER_H2CMFREEIE HSP_SPE_IER_H2CMFREEIE_Msk /*!< H2CMFREEIE (SPE to CPU message free interrupt enable) */ + +/******************** Bit definition for HSP_SPE_ISR register ********************/ +#define HSP_SPE_ISR_C2HMRDYF_Pos (0UL) +#define HSP_SPE_ISR_C2HMRDYF_Msk (0x1UL << HSP_SPE_ISR_C2HMRDYF_Pos) /*!< 0x00000001 */ +#define HSP_SPE_ISR_C2HMRDYF HSP_SPE_ISR_C2HMRDYF_Msk /*!< C2HMRDYF (CPU to SPE message box status) */ + +#define HSP_SPE_ISR_H2CMFREEF_Pos (1UL) +#define HSP_SPE_ISR_H2CMFREEF_Msk (0x1UL << HSP_SPE_ISR_H2CMFREEF_Pos) /*!< 0x00000002 */ +#define HSP_SPE_ISR_H2CMFREEF HSP_SPE_ISR_H2CMFREEF_Msk /*!< H2CMFREEF (SPE to CPU message box status) */ + +#define HSP_SPE_ISR_RSTREQF_Pos (4UL) +#define HSP_SPE_ISR_RSTREQF_Msk (0x1UL << HSP_SPE_ISR_RSTREQF_Pos) /*!< 0x00000010 */ +#define HSP_SPE_ISR_RSTREQF HSP_SPE_ISR_RSTREQF_Msk /*!< RSTREQF (HSP reset request) */ + +#define HSP_SPE_ISR_BUF0EVTF_Pos (12UL) +#define HSP_SPE_ISR_BUF0EVTF_Msk (0x1UL << HSP_SPE_ISR_BUF0EVTF_Pos) /*!< 0x00001000 */ +#define HSP_SPE_ISR_BUF0EVTF HSP_SPE_ISR_BUF0EVTF_Msk /*!< BUF0EVTF (BUF0 status) */ + +#define HSP_SPE_ISR_BUF1EVTF_Pos (13UL) +#define HSP_SPE_ISR_BUF1EVTF_Msk (0x1UL << HSP_SPE_ISR_BUF1EVTF_Pos) /*!< 0x00002000 */ +#define HSP_SPE_ISR_BUF1EVTF HSP_SPE_ISR_BUF1EVTF_Msk /*!< BUF1EVTF (BUF1 status) */ + +#define HSP_SPE_ISR_BUF2EVTF_Pos (14UL) +#define HSP_SPE_ISR_BUF2EVTF_Msk (0x1UL << HSP_SPE_ISR_BUF2EVTF_Pos) /*!< 0x00004000 */ +#define HSP_SPE_ISR_BUF2EVTF HSP_SPE_ISR_BUF2EVTF_Msk /*!< BUF2EVTF (BUF2 status) */ + +#define HSP_SPE_ISR_BUF3EVTF_Pos (15UL) +#define HSP_SPE_ISR_BUF3EVTF_Msk (0x1UL << HSP_SPE_ISR_BUF3EVTF_Pos) /*!< 0x00008000 */ +#define HSP_SPE_ISR_BUF3EVTF HSP_SPE_ISR_BUF3EVTF_Msk /*!< BUF3EVTF (BUF3 status) */ + +/******************** Bit definition for HSP_TCUCFGR register ********************/ +#define HSP_TCUCFGR_TSKCMP0_Pos (0UL) +#define HSP_TCUCFGR_TSKCMP0_Msk (0x3FUL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x0000003F */ +#define HSP_TCUCFGR_TSKCMP0 HSP_TCUCFGR_TSKCMP0_Msk /*!< TSKCMP0[5:0] bits (Task compare 0 (1)) */ +#define HSP_TCUCFGR_TSKCMP0_0 (0x01UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000001 */ +#define HSP_TCUCFGR_TSKCMP0_1 (0x02UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000002 */ +#define HSP_TCUCFGR_TSKCMP0_2 (0x04UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000004 */ +#define HSP_TCUCFGR_TSKCMP0_3 (0x08UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000008 */ +#define HSP_TCUCFGR_TSKCMP0_4 (0x10UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000010 */ +#define HSP_TCUCFGR_TSKCMP0_5 (0x20UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000020 */ + +#define HSP_TCUCFGR_TC0EN_Pos (7UL) +#define HSP_TCUCFGR_TC0EN_Msk (0x1UL << HSP_TCUCFGR_TC0EN_Pos) /*!< 0x00000080 */ +#define HSP_TCUCFGR_TC0EN HSP_TCUCFGR_TC0EN_Msk /*!< TC0EN (Task comparator 0 enable (1)) */ + +#define HSP_TCUCFGR_TSKCMP1_Pos (8UL) +#define HSP_TCUCFGR_TSKCMP1_Msk (0x3FUL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00003F00 */ +#define HSP_TCUCFGR_TSKCMP1 HSP_TCUCFGR_TSKCMP1_Msk /*!< TSKCMP1[5:0] bits (Task compare 1 (1)) */ +#define HSP_TCUCFGR_TSKCMP1_0 (0x01UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00000100 */ +#define HSP_TCUCFGR_TSKCMP1_1 (0x02UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00000200 */ +#define HSP_TCUCFGR_TSKCMP1_2 (0x04UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00000400 */ +#define HSP_TCUCFGR_TSKCMP1_3 (0x08UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00000800 */ +#define HSP_TCUCFGR_TSKCMP1_4 (0x10UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00001000 */ +#define HSP_TCUCFGR_TSKCMP1_5 (0x20UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00002000 */ + +#define HSP_TCUCFGR_TC1EN_Pos (15UL) +#define HSP_TCUCFGR_TC1EN_Msk (0x1UL << HSP_TCUCFGR_TC1EN_Pos) /*!< 0x00008000 */ +#define HSP_TCUCFGR_TC1EN HSP_TCUCFGR_TC1EN_Msk /*!< TC1EN (Task comparator 1 enable (1)) */ + +#define HSP_TCUCFGR_TSKCMP2_Pos (16UL) +#define HSP_TCUCFGR_TSKCMP2_Msk (0x3FUL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x003F0000 */ +#define HSP_TCUCFGR_TSKCMP2 HSP_TCUCFGR_TSKCMP2_Msk /*!< TSKCMP2[5:0] bits (Task compare 2 (1)) */ +#define HSP_TCUCFGR_TSKCMP2_0 (0x01UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00010000 */ +#define HSP_TCUCFGR_TSKCMP2_1 (0x02UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00020000 */ +#define HSP_TCUCFGR_TSKCMP2_2 (0x04UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00040000 */ +#define HSP_TCUCFGR_TSKCMP2_3 (0x08UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00080000 */ +#define HSP_TCUCFGR_TSKCMP2_4 (0x10UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00100000 */ +#define HSP_TCUCFGR_TSKCMP2_5 (0x20UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00200000 */ + +#define HSP_TCUCFGR_TC2EN_Pos (23UL) +#define HSP_TCUCFGR_TC2EN_Msk (0x1UL << HSP_TCUCFGR_TC2EN_Pos) /*!< 0x00800000 */ +#define HSP_TCUCFGR_TC2EN HSP_TCUCFGR_TC2EN_Msk /*!< TC2EN (Task comparator 2 enable (1)) */ + +#define HSP_TCUCFGR_TSKCMP3_Pos (24UL) +#define HSP_TCUCFGR_TSKCMP3_Msk (0x3FUL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x3F000000 */ +#define HSP_TCUCFGR_TSKCMP3 HSP_TCUCFGR_TSKCMP3_Msk /*!< TSKCMP3[5:0] bits (Task compare 3 (1)) */ +#define HSP_TCUCFGR_TSKCMP3_0 (0x01UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x01000000 */ +#define HSP_TCUCFGR_TSKCMP3_1 (0x02UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x02000000 */ +#define HSP_TCUCFGR_TSKCMP3_2 (0x04UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x04000000 */ +#define HSP_TCUCFGR_TSKCMP3_3 (0x08UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x08000000 */ +#define HSP_TCUCFGR_TSKCMP3_4 (0x10UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x10000000 */ +#define HSP_TCUCFGR_TSKCMP3_5 (0x20UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x20000000 */ + +#define HSP_TCUCFGR_TC3EN_Pos (31UL) +#define HSP_TCUCFGR_TC3EN_Msk (0x1UL << HSP_TCUCFGR_TC3EN_Pos) /*!< 0x80000000 */ +#define HSP_TCUCFGR_TC3EN HSP_TCUCFGR_TC3EN_Msk /*!< TC3EN (Task comparator 3 enable ) */ + +/******************** Bit definition for HSP_TOVLPCR register ********************/ +#define HSP_TOVLPCR_TOVLPEN_Pos (0UL) +#define HSP_TOVLPCR_TOVLPEN_Msk (0x1UL << HSP_TOVLPCR_TOVLPEN_Pos) /*!< 0x00000001 */ +#define HSP_TOVLPCR_TOVLPEN HSP_TOVLPCR_TOVLPEN_Msk /*!< TOVLPEN (Task overlap enable (1)) */ + +#define HSP_TOVLPCR_LTNB_Pos (8UL) +#define HSP_TOVLPCR_LTNB_Msk (0x3FUL << HSP_TOVLPCR_LTNB_Pos) /*!< 0x00003F00 */ +#define HSP_TOVLPCR_LTNB HSP_TOVLPCR_LTNB_Msk /*!< LTNB[5:0] bits (Lower task number value (1)) */ + +#define HSP_TOVLPCR_HTNB_Pos (16UL) +#define HSP_TOVLPCR_HTNB_Msk (0x3FUL << HSP_TOVLPCR_HTNB_Pos) /*!< 0x003F0000 */ +#define HSP_TOVLPCR_HTNB HSP_TOVLPCR_HTNB_Msk /*!< HTNB[5:0] bits (Higher task number value ) */ + +/******************** Bit definition for HSP_SNPR register ********************/ +#define HSP_SNPR_SNPSELA_Pos (0UL) +#define HSP_SNPR_SNPSELA_Msk (0x7UL << HSP_SNPR_SNPSELA_Pos) /*!< 0x00000007 */ +#define HSP_SNPR_SNPSELA HSP_SNPR_SNPSELA_Msk /*!< SNPSELA[2:0] bits (Snoop group A signal selection) */ +#define HSP_SNPR_SNPSELA_0 (0x1UL << HSP_SNPR_SNPSELA_Pos) /*!< 0x00000001 */ +#define HSP_SNPR_SNPSELA_1 (0x2UL << HSP_SNPR_SNPSELA_Pos) /*!< 0x00000002 */ +#define HSP_SNPR_SNPSELA_2 (0x4UL << HSP_SNPR_SNPSELA_Pos) /*!< 0x00000004 */ + +#define HSP_SNPR_SNPSELB_Pos (4UL) +#define HSP_SNPR_SNPSELB_Msk (0x7UL << HSP_SNPR_SNPSELB_Pos) /*!< 0x00000070 */ +#define HSP_SNPR_SNPSELB HSP_SNPR_SNPSELB_Msk /*!< SNPSELB[2:0] bits (Snoop group B signal selection) */ +#define HSP_SNPR_SNPSELB_0 (0x1UL << HSP_SNPR_SNPSELB_Pos) /*!< 0x00000010 */ +#define HSP_SNPR_SNPSELB_1 (0x2UL << HSP_SNPR_SNPSELB_Pos) /*!< 0x00000020 */ +#define HSP_SNPR_SNPSELB_2 (0x4UL << HSP_SNPR_SNPSELB_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for HSP_CCNTR register ********************/ +#define HSP_CCNTR_CCNTR_Pos (0UL) +#define HSP_CCNTR_CCNTR_Msk (0xFFFFFFFFUL << HSP_CCNTR_CCNTR_Pos) /*!< 0xFFFFFFFF */ +#define HSP_CCNTR_CCNTR HSP_CCNTR_CCNTR_Msk /*!< CCNTR[31:0] bits (Conflict counter) */ + +/****************** Bit definition for HSP_CAPDR register *******************/ +#define HSP_CAPDR_TSTAMP_Pos (0UL) +#define HSP_CAPDR_TSTAMP_Msk (0x3FFFUL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00003FFF */ +#define HSP_CAPDR_TSTAMP HSP_CAPDR_TSTAMP_Msk /*!< Time-stamp value */ +#define HSP_CAPDR_IFHIST_Pos (14UL) +#define HSP_CAPDR_IFHIST_Msk (0xFFUL << HSP_CAPDR_IFHIST_Pos) /*!< 0x003FC000 */ +#define HSP_CAPDR_IFHIST HSP_CAPDR_IFHIST_Msk /*!< IF condition history */ +#define HSP_CAPDR_IFCNT_Pos (22UL) +#define HSP_CAPDR_IFCNT_Msk (0xFUL << HSP_CAPDR_IFCNT_Pos) /*!< 0x03C00000 */ +#define HSP_CAPDR_IFCNT HSP_CAPDR_IFCNT_Msk /*!< IF instruction counter */ +#define HSP_CAPDR_TSKNB_Pos (26UL) +#define HSP_CAPDR_TSKNB_Msk (0x3FUL << HSP_CAPDR_TSKNB_Pos) /*!< 0xFC000000 */ +#define HSP_CAPDR_TSKNB HSP_CAPDR_TSKNB_Msk /*!< Last captured task number */ + +#define HSP_CAPDR_ALT_IFHIST_Pos (0UL) +#define HSP_CAPDR_ALT_IFHIST_Msk (0x7FFFUL << HSP_CAPDR_ALT_IFHIST_Pos) /*!< 0x00007FFF */ +#define HSP_CAPDR_ALT_IFHIST HSP_CAPDR_IFHIST_Msk /*!< IF condition history */ +#define HSP_CAPDR_ALT_PFCTNB_Pos (16UL) +#define HSP_CAPDR_ALT_PFCTNB_Msk (0x3FUL << HSP_CAPDR_ALT_PFCTNB_Pos) /*!< 0x0003F0000 */ +#define HSP_CAPDR_ALT_PFCTNB HSP_CAPDR_TSTAMP_Msk /*!< Processing Function Number */ +#define HSP_CAPDR_ALT_IFCNT_Pos (22UL) +#define HSP_CAPDR_ALT_IFCNT_Msk (0xFUL << HSP_CAPDR_ALT_IFCNT_Pos) /*!< 0x03C00000 */ +#define HSP_CAPDR_ALT_IFCNT HSP_CAPDR_IFCNT_Msk /*!< IF instruction counter */ +#define HSP_CAPDR_ALT_TSKNB_Pos (26UL) +#define HSP_CAPDR_ALT_TSKNB_Msk (0x3FUL << HSP_CAPDR_ALT_TSKNB_Pos) /*!< 0xFC000000 */ +#define HSP_CAPDR_ALT_TSKNB HSP_CAPDR_TSKNB_Msk /*!< Last captured task number */ + +/******************** Bit definition for HSP_CAPCR register ********************/ +#define HSP_CAPCR_CAPMOD_Pos (0UL) +#define HSP_CAPCR_CAPMOD_Msk (0x3UL << HSP_CAPCR_CAPMOD_Pos) /*!< 0x00000003 */ +#define HSP_CAPCR_CAPMOD HSP_CAPCR_CAPMOD_Msk /*!< CAPMOD[1:0] bits (Capture mode ) */ +#define HSP_CAPCR_CAPMOD_0 (0x1UL << HSP_CAPCR_CAPMOD_Pos) /*!< 0x00000001 */ +#define HSP_CAPCR_CAPMOD_1 (0x2UL << HSP_CAPCR_CAPMOD_Pos) /*!< 0x00000002 */ + +#define HSP_CAPCR_FRCNTEN_Pos (2UL) +#define HSP_CAPCR_FRCNTEN_Msk (0x1UL << HSP_CAPCR_FRCNTEN_Pos) /*!< 0x00000004 */ +#define HSP_CAPCR_FRCNTEN HSP_CAPCR_FRCNTEN_Msk /*!< FRCNTEN (Free-running counter enable ) */ + +#define HSP_CAPCR_PRESC_Pos (4UL) +#define HSP_CAPCR_PRESC_Msk (0x1FUL << HSP_CAPCR_PRESC_Pos) /*!< 0x000001F0 */ +#define HSP_CAPCR_PRESC HSP_CAPCR_PRESC_Msk /*!< PRESC[4:0] bits (Time-stamp prescaler value ) */ +#define HSP_CAPCR_PRESC_0 (0x01UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000010 */ +#define HSP_CAPCR_PRESC_1 (0x02UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000020 */ +#define HSP_CAPCR_PRESC_2 (0x04UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000040 */ +#define HSP_CAPCR_PRESC_3 (0x08UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000080 */ +#define HSP_CAPCR_PRESC_4 (0x10UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000100 */ + +#define HSP_CAPCR_TSKFLT_Pos (12UL) +#define HSP_CAPCR_TSKFLT_Msk (0x1UL << HSP_CAPCR_TSKFLT_Pos) /*!< 0x00001000 */ +#define HSP_CAPCR_TSKFLT HSP_CAPCR_TSKFLT_Msk /*!< TSKFLT (Task filter enable (1)) */ + +#define HSP_CAPCR_CCNTREN_Pos (16UL) +#define HSP_CAPCR_CCNTREN_Msk (0x1UL << HSP_CAPCR_CCNTREN_Pos) /*!< 0x00010000 */ +#define HSP_CAPCR_CCNTREN HSP_CAPCR_CCNTREN_Msk /*!< CCNTREN (Conflict counter enable ) */ + +/******************** Bit definition for HSP_ERR_IER register ********************/ +#define HSP_ERR_IER_TRGIOVRIE_Pos (8UL) +#define HSP_ERR_IER_TRGIOVRIE_Msk (0x1UL << HSP_ERR_IER_TRGIOVRIE_Pos) /*!< 0x00000100 */ +#define HSP_ERR_IER_TRGIOVRIE HSP_ERR_IER_TRGIOVRIE_Msk /*!< TRGIOVRIE (TRGITF overrun interrupt enable) */ + +#define HSP_ERR_IER_B0ERRIE_Pos (12UL) +#define HSP_ERR_IER_B0ERRIE_Msk (0x1UL << HSP_ERR_IER_B0ERRIE_Pos) /*!< 0x00001000 */ +#define HSP_ERR_IER_B0ERRIE HSP_ERR_IER_B0ERRIE_Msk /*!< B0ERRIE (H2CBUFF0 underrun or C2HBUFF0 overrun interrupt enable) */ + +#define HSP_ERR_IER_B1ERRIE_Pos (13UL) +#define HSP_ERR_IER_B1ERRIE_Msk (0x1UL << HSP_ERR_IER_B1ERRIE_Pos) /*!< 0x00002000 */ +#define HSP_ERR_IER_B1ERRIE HSP_ERR_IER_B1ERRIE_Msk /*!< B1ERRIE (H2CBUFF1 underrun or C2HBUFF1 overrun interrupt enable) */ + +#define HSP_ERR_IER_B2ERRIE_Pos (14UL) +#define HSP_ERR_IER_B2ERRIE_Msk (0x1UL << HSP_ERR_IER_B2ERRIE_Pos) /*!< 0x00004000 */ +#define HSP_ERR_IER_B2ERRIE HSP_ERR_IER_B2ERRIE_Msk /*!< B2ERRIE (H2CBUFF2 underrun or C2HBUFF2 overrun interrupt enable) */ + +#define HSP_ERR_IER_B3ERRIE_Pos (15UL) +#define HSP_ERR_IER_B3ERRIE_Msk (0x1UL << HSP_ERR_IER_B3ERRIE_Pos) /*!< 0x00008000 */ +#define HSP_ERR_IER_B3ERRIE HSP_ERR_IER_B3ERRIE_Msk /*!< B3ERRIE (H2CBUFF3 underrun or C2HBUFF3 overrun interrupt enable) */ + +#define HSP_ERR_IER_CAPOVRIE_Pos (16UL) +#define HSP_ERR_IER_CAPOVRIE_Msk (0x1UL << HSP_ERR_IER_CAPOVRIE_Pos) /*!< 0x00010000 */ +#define HSP_ERR_IER_CAPOVRIE HSP_ERR_IER_CAPOVRIE_Msk /*!< CAPOVRIE (Capture register overrun interrupt enable) */ + +#define HSP_ERR_IER_FWERRIE_Pos (17UL) +#define HSP_ERR_IER_FWERRIE_Msk (0x1UL << HSP_ERR_IER_FWERRIE_Pos) /*!< 0x00020000 */ +#define HSP_ERR_IER_FWERRIE HSP_ERR_IER_FWERRIE_Msk /*!< FWERRIE (Firmware error interrupt enable) */ + +#define HSP_ERR_IER_SCHERRIE_Pos (18UL) +#define HSP_ERR_IER_SCHERRIE_Msk (0x1UL << HSP_ERR_IER_SCHERRIE_Pos) /*!< 0x00040000 */ +#define HSP_ERR_IER_SCHERRIE HSP_ERR_IER_SCHERRIE_Msk /*!< SCHERRIE (Scheduler error interrupt enable) */ + +#define HSP_ERR_IER_BKINIE_Pos (19UL) +#define HSP_ERR_IER_BKINIE_Msk (0x1UL << HSP_ERR_IER_BKINIE_Pos) /*!< 0x00080000 */ +#define HSP_ERR_IER_BKINIE HSP_ERR_IER_BKINIE_Msk /*!< BKINIE (Break input interrupt enable) */ + +#define HSP_ERR_IER_HDEGOVRIE_Pos (20UL) +#define HSP_ERR_IER_HDEGOVRIE_Msk (0x1UL << HSP_ERR_IER_HDEGOVRIE_Pos) /*!< 0x00100000 */ +#define HSP_ERR_IER_HDEGOVRIE HSP_ERR_IER_HDEGOVRIE_Msk /*!< HDEGOVRIE (SPE event overrun interrupt enable) */ + +#define HSP_ERR_IER_OPCOERRIE_Pos (22UL) +#define HSP_ERR_IER_OPCOERRIE_Msk (0x1UL << HSP_ERR_IER_OPCOERRIE_Pos) /*!< 0x00400000 */ +#define HSP_ERR_IER_OPCOERRIE HSP_ERR_IER_OPCOERRIE_Msk /*!< OPCOERRIE (Invalid Op. code error interrupt enable) */ + +#define HSP_ERR_IER_ACCERRIE_Pos (23UL) +#define HSP_ERR_IER_ACCERRIE_Msk (0x1UL << HSP_ERR_IER_ACCERRIE_Pos) /*!< 0x00800000 */ +#define HSP_ERR_IER_ACCERRIE HSP_ERR_IER_ACCERRIE_Msk /*!< ACCERRIE (SPE access error interrupt enable) */ + +#define HSP_ERR_IER_UDFIE_Pos (24UL) +#define HSP_ERR_IER_UDFIE_Msk (0x1UL << HSP_ERR_IER_UDFIE_Pos) /*!< 0x01000000 */ +#define HSP_ERR_IER_UDFIE HSP_ERR_IER_UDFIE_Msk /*!< UDFIE (FPU Underflow exception interrupt enable) */ + +#define HSP_ERR_IER_OVFIE_Pos (25UL) +#define HSP_ERR_IER_OVFIE_Msk (0x1UL << HSP_ERR_IER_OVFIE_Pos) /*!< 0x02000000 */ +#define HSP_ERR_IER_OVFIE HSP_ERR_IER_OVFIE_Msk /*!< OVFIE (FPU Overflow exception interrupt enable) */ + +#define HSP_ERR_IER_DBZIE_Pos (26UL) +#define HSP_ERR_IER_DBZIE_Msk (0x1UL << HSP_ERR_IER_DBZIE_Pos) /*!< 0x04000000 */ +#define HSP_ERR_IER_DBZIE HSP_ERR_IER_DBZIE_Msk /*!< DBZIE (FPU division-by-zero exception interrupt enable) */ + +#define HSP_ERR_IER_INVIE_Pos (27UL) +#define HSP_ERR_IER_INVIE_Msk (0x1UL << HSP_ERR_IER_INVIE_Pos) /*!< 0x08000000 */ +#define HSP_ERR_IER_INVIE HSP_ERR_IER_INVIE_Msk /*!< INVIE (FPU Invalid exception interrupt enable) */ + +#define HSP_ERR_IER_DENORMIE_Pos (28UL) +#define HSP_ERR_IER_DENORMIE_Msk (0x1UL << HSP_ERR_IER_DENORMIE_Pos) /*!< 0x10000000 */ +#define HSP_ERR_IER_DENORMIE HSP_ERR_IER_DENORMIE_Msk /*!< DENORMIE (FPU denormal interrupt enable) */ + +/******************** Bit definition for HSP_EVT_IER register ********************/ +#define HSP_EVT_IER_H2CMRDYIE_Pos (0UL) +#define HSP_EVT_IER_H2CMRDYIE_Msk (0x1UL << HSP_EVT_IER_H2CMRDYIE_Pos) /*!< 0x00000001 */ +#define HSP_EVT_IER_H2CMRDYIE HSP_EVT_IER_H2CMRDYIE_Msk /*!< H2CMRDYIE (HSP to CPU message ready interrupt enable) */ + +#define HSP_EVT_IER_C2HMFREEIE_Pos (1UL) +#define HSP_EVT_IER_C2HMFREEIE_Msk (0x1UL << HSP_EVT_IER_C2HMFREEIE_Pos) /*!< 0x00000002 */ +#define HSP_EVT_IER_C2HMFREEIE HSP_EVT_IER_C2HMFREEIE_Msk /*!< C2HMFREEIE (CPU to HSP message box free interrupt enable) */ + +#define HSP_EVT_IER_DCDONEIE_Pos (2UL) +#define HSP_EVT_IER_DCDONEIE_Msk (0x1UL << HSP_EVT_IER_DCDONEIE_Pos) /*!< 0x00000004 */ +#define HSP_EVT_IER_DCDONEIE HSP_EVT_IER_DCDONEIE_Msk /*!< DCDONEIE (Direct command done interrupt enable) */ + +#define HSP_EVT_IER_CAPRDYIE_Pos (4UL) +#define HSP_EVT_IER_CAPRDYIE_Msk (0x1UL << HSP_EVT_IER_CAPRDYIE_Pos) /*!< 0x00000010 */ +#define HSP_EVT_IER_CAPRDYIE HSP_EVT_IER_CAPRDYIE_Msk /*!< CAPRDYIE (Capture buffer data ready interrupt enable) */ + +#define HSP_EVT_IER_CDEGRDYIE_Pos (7UL) +#define HSP_EVT_IER_CDEGRDYIE_Msk (0x1UL << HSP_EVT_IER_CDEGRDYIE_Pos) /*!< 0x00000080 */ +#define HSP_EVT_IER_CDEGRDYIE HSP_EVT_IER_CDEGRDYIE_Msk /*!< CDEGRDYIE (CPU Dedicated event generator ready interrupt enable) */ + +#define HSP_EVT_IER_SOFWFEIE_Pos (8UL) +#define HSP_EVT_IER_SOFWFEIE_Msk (0x1UL << HSP_EVT_IER_SOFWFEIE_Pos) /*!< 0x00000100 */ +#define HSP_EVT_IER_SOFWFEIE HSP_EVT_IER_SOFWFEIE_Msk /*!< SOFWFEIE (Start of WFE interrupt enable) */ + +#define HSP_EVT_IER_EOFWFEIE_Pos (9UL) +#define HSP_EVT_IER_EOFWFEIE_Msk (0x1UL << HSP_EVT_IER_EOFWFEIE_Pos) /*!< 0x00000200 */ +#define HSP_EVT_IER_EOFWFEIE HSP_EVT_IER_EOFWFEIE_Msk /*!< EOFWFEIE (End of WFE interrupt enable) */ + +#define HSP_EVT_IER_B0EVTIE_Pos (12UL) +#define HSP_EVT_IER_B0EVTIE_Msk (0x1UL << HSP_EVT_IER_B0EVTIE_Pos) /*!< 0x00001000 */ +#define HSP_EVT_IER_B0EVTIE HSP_EVT_IER_B0EVTIE_Msk /*!< B0EVTIE (BUFF0 event interrupt enable) */ + +#define HSP_EVT_IER_B1EVTIE_Pos (13UL) +#define HSP_EVT_IER_B1EVTIE_Msk (0x1UL << HSP_EVT_IER_B1EVTIE_Pos) /*!< 0x00002000 */ +#define HSP_EVT_IER_B1EVTIE HSP_EVT_IER_B1EVTIE_Msk /*!< B1EVTIE (BUFF1 event interrupt enable) */ + +#define HSP_EVT_IER_B2EVTIE_Pos (14UL) +#define HSP_EVT_IER_B2EVTIE_Msk (0x1UL << HSP_EVT_IER_B2EVTIE_Pos) /*!< 0x00004000 */ +#define HSP_EVT_IER_B2EVTIE HSP_EVT_IER_B2EVTIE_Msk /*!< B2EVTIE (BUFF2 event interrupt enable) */ + +#define HSP_EVT_IER_B3EVTIE_Pos (15UL) +#define HSP_EVT_IER_B3EVTIE_Msk (0x1UL << HSP_EVT_IER_B3EVTIE_Pos) /*!< 0x00008000 */ +#define HSP_EVT_IER_B3EVTIE HSP_EVT_IER_B3EVTIE_Msk /*!< B3EVTIE (BUFF3 event interrupt enable) */ + +#define HSP_EVT_IER_SOTECP0IE_Pos (16UL) +#define HSP_EVT_IER_SOTECP0IE_Msk (0x1UL << HSP_EVT_IER_SOTECP0IE_Pos) /*!< 0x00010000 */ +#define HSP_EVT_IER_SOTECP0IE HSP_EVT_IER_SOTECP0IE_Msk /*!< SOTECP0IE (Start of task generated by event comparator 0 interrupt enable) */ + +#define HSP_EVT_IER_SOTECP1IE_Pos (17UL) +#define HSP_EVT_IER_SOTECP1IE_Msk (0x1UL << HSP_EVT_IER_SOTECP1IE_Pos) /*!< 0x00020000 */ +#define HSP_EVT_IER_SOTECP1IE HSP_EVT_IER_SOTECP1IE_Msk /*!< SOTECP1IE (Start of task generated by event comparator 1 interrupt enable) */ + +#define HSP_EVT_IER_SOTECP2IE_Pos (18UL) +#define HSP_EVT_IER_SOTECP2IE_Msk (0x1UL << HSP_EVT_IER_SOTECP2IE_Pos) /*!< 0x00040000 */ +#define HSP_EVT_IER_SOTECP2IE HSP_EVT_IER_SOTECP2IE_Msk /*!< SOTECP2IE (Start of task generated by event comparator 2 interrupt enable) */ + +#define HSP_EVT_IER_SOTECP3IE_Pos (19UL) +#define HSP_EVT_IER_SOTECP3IE_Msk (0x1UL << HSP_EVT_IER_SOTECP3IE_Pos) /*!< 0x00080000 */ +#define HSP_EVT_IER_SOTECP3IE HSP_EVT_IER_SOTECP3IE_Msk /*!< SOTECP3IE (Start of task generated by event comparator 3 interrupt enable) */ + +#define HSP_EVT_IER_EOTECP0IE_Pos (20UL) +#define HSP_EVT_IER_EOTECP0IE_Msk (0x1UL << HSP_EVT_IER_EOTECP0IE_Pos) /*!< 0x00100000 */ +#define HSP_EVT_IER_EOTECP0IE HSP_EVT_IER_EOTECP0IE_Msk /*!< EOTECP0IE (End of task generated by event comparator 0 interrupt enable) */ + +#define HSP_EVT_IER_EOTECP1IE_Pos (21UL) +#define HSP_EVT_IER_EOTECP1IE_Msk (0x1UL << HSP_EVT_IER_EOTECP1IE_Pos) /*!< 0x00200000 */ +#define HSP_EVT_IER_EOTECP1IE HSP_EVT_IER_EOTECP1IE_Msk /*!< EOTECP1IE (End of task generated by event comparator 1 interrupt enable) */ + +#define HSP_EVT_IER_EOTECP2IE_Pos (22UL) +#define HSP_EVT_IER_EOTECP2IE_Msk (0x1UL << HSP_EVT_IER_EOTECP2IE_Pos) /*!< 0x00400000 */ +#define HSP_EVT_IER_EOTECP2IE HSP_EVT_IER_EOTECP2IE_Msk /*!< EOTECP2IE (End of task generated by event comparator 2 interrupt enable) */ + +#define HSP_EVT_IER_EOTECP3IE_Pos (23UL) +#define HSP_EVT_IER_EOTECP3IE_Msk (0x1UL << HSP_EVT_IER_EOTECP3IE_Pos) /*!< 0x00800000 */ +#define HSP_EVT_IER_EOTECP3IE HSP_EVT_IER_EOTECP3IE_Msk /*!< EOTECP3IE (End of task generated by event comparator 3 interrupt enable) */ + +#define HSP_EVT_IER_TOVLPIE_Pos (28UL) +#define HSP_EVT_IER_TOVLPIE_Msk (0x1UL << HSP_EVT_IER_TOVLPIE_Pos) /*!< 0x10000000 */ +#define HSP_EVT_IER_TOVLPIE HSP_EVT_IER_TOVLPIE_Msk /*!< TOVLPIE (Task overlap flag interrupt enable) */ + +#define HSP_EVT_IER_FPUSATIE_Pos (31UL) +#define HSP_EVT_IER_FPUSATIE_Msk (0x1UL << HSP_EVT_IER_FPUSATIE_Pos) /*!< 0x80000000 */ +#define HSP_EVT_IER_FPUSATIE HSP_EVT_IER_FPUSATIE_Msk /*!< FPUSATIE (Saturation flag interrupt enable) */ + +/******************** Bit definition for HSP_PFCTEVT_IER register ********************/ +#define HSP_PFCTEVT_IER_PFCTIE_Pos (0UL) +#define HSP_PFCTEVT_IER_PFCTIE_Msk (0xFFFFFFFFUL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PFCTEVT_IER_PFCTIE HSP_PFCTEVT_IER_PFCTIE_Msk /*!< PFCTIE[31:0] bits (Processing function flags interrupt enable) */ +#define HSP_PFCTEVT_IER_PFCTIE_0 (0x00001UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000001 */ +#define HSP_PFCTEVT_IER_PFCTIE_1 (0x00002UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000002 */ +#define HSP_PFCTEVT_IER_PFCTIE_2 (0x00004UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000004 */ +#define HSP_PFCTEVT_IER_PFCTIE_3 (0x00008UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000008 */ +#define HSP_PFCTEVT_IER_PFCTIE_4 (0x00010UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000010 */ +#define HSP_PFCTEVT_IER_PFCTIE_5 (0x00020UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000020 */ +#define HSP_PFCTEVT_IER_PFCTIE_6 (0x00040UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000040 */ +#define HSP_PFCTEVT_IER_PFCTIE_7 (0x00080UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000080 */ +#define HSP_PFCTEVT_IER_PFCTIE_8 (0x00100UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000100 */ +#define HSP_PFCTEVT_IER_PFCTIE_9 (0x00200UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000200 */ +#define HSP_PFCTEVT_IER_PFCTIE_10 (0x00400UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000400 */ +#define HSP_PFCTEVT_IER_PFCTIE_11 (0x00800UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000800 */ +#define HSP_PFCTEVT_IER_PFCTIE_12 (0x01000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00001000 */ +#define HSP_PFCTEVT_IER_PFCTIE_13 (0x02000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00002000 */ +#define HSP_PFCTEVT_IER_PFCTIE_14 (0x04000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00004000 */ +#define HSP_PFCTEVT_IER_PFCTIE_15 (0x08000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00008000 */ +#define HSP_PFCTEVT_IER_PFCTIE_16 (0x10000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00010000 */ +#define HSP_PFCTEVT_IER_PFCTIE_17 (0x20000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00020000 */ +#define HSP_PFCTEVT_IER_PFCTIE_18 (0x40000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00040000 */ +#define HSP_PFCTEVT_IER_PFCTIE_19 (0x80000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00080000 */ +#define HSP_PFCTEVT_IER_PFCTIE_20 (0x100000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00100000 */ +#define HSP_PFCTEVT_IER_PFCTIE_21 (0x200000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00200000 */ +#define HSP_PFCTEVT_IER_PFCTIE_22 (0x400000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00400000 */ +#define HSP_PFCTEVT_IER_PFCTIE_23 (0x800000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00800000 */ +#define HSP_PFCTEVT_IER_PFCTIE_24 (0x1000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x01000000 */ +#define HSP_PFCTEVT_IER_PFCTIE_25 (0x2000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x02000000 */ +#define HSP_PFCTEVT_IER_PFCTIE_26 (0x4000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x04000000 */ +#define HSP_PFCTEVT_IER_PFCTIE_27 (0x8000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x08000000 */ +#define HSP_PFCTEVT_IER_PFCTIE_28 (0x10000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x10000000 */ +#define HSP_PFCTEVT_IER_PFCTIE_29 (0x20000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x20000000 */ +#define HSP_PFCTEVT_IER_PFCTIE_30 (0x40000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x40000000 */ +#define HSP_PFCTEVT_IER_PFCTIE_31 (0x80000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for HSP_ERR_ISR register ********************/ +#define HSP_ERR_ISR_TRGIOVRF_Pos (8UL) +#define HSP_ERR_ISR_TRGIOVRF_Msk (0x1UL << HSP_ERR_ISR_TRGIOVRF_Pos) /*!< 0x00000100 */ +#define HSP_ERR_ISR_TRGIOVRF HSP_ERR_ISR_TRGIOVRF_Msk /*!< TRGIOVRF (TRGITF overrun flag) */ + +#define HSP_ERR_ISR_B0ERRF_Pos (12UL) +#define HSP_ERR_ISR_B0ERRF_Msk (0x1UL << HSP_ERR_ISR_B0ERRF_Pos) /*!< 0x00001000 */ +#define HSP_ERR_ISR_B0ERRF HSP_ERR_ISR_B0ERRF_Msk /*!< B0ERRF (H2CBUFF0 underrun or C2HBUFF0 overrun flag) */ + +#define HSP_ERR_ISR_B1ERRF_Pos (13UL) +#define HSP_ERR_ISR_B1ERRF_Msk (0x1UL << HSP_ERR_ISR_B1ERRF_Pos) /*!< 0x00002000 */ +#define HSP_ERR_ISR_B1ERRF HSP_ERR_ISR_B1ERRF_Msk /*!< B1ERRF (H2CBUFF1 underrun or C2HBUFF1 overrun flag) */ + +#define HSP_ERR_ISR_B2ERRF_Pos (14UL) +#define HSP_ERR_ISR_B2ERRF_Msk (0x1UL << HSP_ERR_ISR_B2ERRF_Pos) /*!< 0x00004000 */ +#define HSP_ERR_ISR_B2ERRF HSP_ERR_ISR_B2ERRF_Msk /*!< B2ERRF (H2CBUFF2 underrun or C2HBUFF2 overrun flag) */ + +#define HSP_ERR_ISR_B3ERRF_Pos (15UL) +#define HSP_ERR_ISR_B3ERRF_Msk (0x1UL << HSP_ERR_ISR_B3ERRF_Pos) /*!< 0x00008000 */ +#define HSP_ERR_ISR_B3ERRF HSP_ERR_ISR_B3ERRF_Msk /*!< B3ERRF (H2CBUFF3 underrun or C2HBUFF3 overrun flag) */ + +#define HSP_ERR_ISR_CAPOVRF_Pos (16UL) +#define HSP_ERR_ISR_CAPOVRF_Msk (0x1UL << HSP_ERR_ISR_CAPOVRF_Pos) /*!< 0x00010000 */ +#define HSP_ERR_ISR_CAPOVRF HSP_ERR_ISR_CAPOVRF_Msk /*!< CAPOVRF (Capture register overrun flag) */ + +#define HSP_ERR_ISR_FWERRF_Pos (17UL) +#define HSP_ERR_ISR_FWERRF_Msk (0x1UL << HSP_ERR_ISR_FWERRF_Pos) /*!< 0x00020000 */ +#define HSP_ERR_ISR_FWERRF HSP_ERR_ISR_FWERRF_Msk /*!< FWERRF (Firmware error flag) */ + +#define HSP_ERR_ISR_SCHERRF_Pos (18UL) +#define HSP_ERR_ISR_SCHERRF_Msk (0x1UL << HSP_ERR_ISR_SCHERRF_Pos) /*!< 0x00040000 */ +#define HSP_ERR_ISR_SCHERRF HSP_ERR_ISR_SCHERRF_Msk /*!< SCHERRF (Scheduler error flag) */ + +#define HSP_ERR_ISR_BKINF_Pos (19UL) +#define HSP_ERR_ISR_BKINF_Msk (0x1UL << HSP_ERR_ISR_BKINF_Pos) /*!< 0x00080000 */ +#define HSP_ERR_ISR_BKINF HSP_ERR_ISR_BKINF_Msk /*!< BKINF (Break input flag) */ + +#define HSP_ERR_ISR_HDEGOVRF_Pos (20UL) +#define HSP_ERR_ISR_HDEGOVRF_Msk (0x1UL << HSP_ERR_ISR_HDEGOVRF_Pos) /*!< 0x00100000 */ +#define HSP_ERR_ISR_HDEGOVRF HSP_ERR_ISR_HDEGOVRF_Msk /*!< HDEGOVRF (SPE event overrun flag) */ + +#define HSP_ERR_ISR_OPCOERRF_Pos (22UL) +#define HSP_ERR_ISR_OPCOERRF_Msk (0x1UL << HSP_ERR_ISR_OPCOERRF_Pos) /*!< 0x00400000 */ +#define HSP_ERR_ISR_OPCOERRF HSP_ERR_ISR_OPCOERRF_Msk /*!< OPCOERRF (Invalid OpCode error flag) */ + +#define HSP_ERR_ISR_ACCERRF_Pos (23UL) +#define HSP_ERR_ISR_ACCERRF_Msk (0x1UL << HSP_ERR_ISR_ACCERRF_Pos) /*!< 0x00800000 */ +#define HSP_ERR_ISR_ACCERRF HSP_ERR_ISR_ACCERRF_Msk /*!< ACCERRF (SPE Access error flag) */ + +#define HSP_ERR_ISR_FPUERRF_Pos (24UL) +#define HSP_ERR_ISR_FPUERRF_Msk (0x1UL << HSP_ERR_ISR_FPUERRF_Pos) /*!< 0x01000000 */ +#define HSP_ERR_ISR_FPUERRF HSP_ERR_ISR_FPUERRF_Msk /*!< FPUERRF (Computation error flag) */ + +/******************** Bit definition for HSP_EVT_ISR register ********************/ +#define HSP_EVT_ISR_H2CMRDYF_Pos (0UL) +#define HSP_EVT_ISR_H2CMRDYF_Msk (0x1UL << HSP_EVT_ISR_H2CMRDYF_Pos) /*!< 0x00000001 */ +#define HSP_EVT_ISR_H2CMRDYF HSP_EVT_ISR_H2CMRDYF_Msk /*!< H2CMRDYF (HSP to CPU message ready flag) */ + +#define HSP_EVT_ISR_C2HMFREEF_Pos (1UL) +#define HSP_EVT_ISR_C2HMFREEF_Msk (0x1UL << HSP_EVT_ISR_C2HMFREEF_Pos) /*!< 0x00000002 */ +#define HSP_EVT_ISR_C2HMFREEF HSP_EVT_ISR_C2HMFREEF_Msk /*!< C2HMFREEF (CPU to HSP message box free flag) */ + +#define HSP_EVT_ISR_DCDONEF_Pos (2UL) +#define HSP_EVT_ISR_DCDONEF_Msk (0x1UL << HSP_EVT_ISR_DCDONEF_Pos) /*!< 0x00000004 */ +#define HSP_EVT_ISR_DCDONEF HSP_EVT_ISR_DCDONEF_Msk /*!< DCDONEF (Direct command done flag) */ + +#define HSP_EVT_ISR_CAPRDYF_Pos (4UL) +#define HSP_EVT_ISR_CAPRDYF_Msk (0x1UL << HSP_EVT_ISR_CAPRDYF_Pos) /*!< 0x00000010 */ +#define HSP_EVT_ISR_CAPRDYF HSP_EVT_ISR_CAPRDYF_Msk /*!< CAPRDYF (Capture buffer data ready flag) */ + +#define HSP_EVT_ISR_CDEGRDYF_Pos (7UL) +#define HSP_EVT_ISR_CDEGRDYF_Msk (0x1UL << HSP_EVT_ISR_CDEGRDYF_Pos) /*!< 0x00000080 */ +#define HSP_EVT_ISR_CDEGRDYF HSP_EVT_ISR_CDEGRDYF_Msk /*!< CDEGRDYF (CPU Dedicated event generator ready flag) */ + +#define HSP_EVT_ISR_SOFWFEF_Pos (8UL) +#define HSP_EVT_ISR_SOFWFEF_Msk (0x1UL << HSP_EVT_ISR_SOFWFEF_Pos) /*!< 0x00000100 */ +#define HSP_EVT_ISR_SOFWFEF HSP_EVT_ISR_SOFWFEF_Msk /*!< SOFWFEF (Start of WFE flag) */ + +#define HSP_EVT_ISR_EOFWFEF_Pos (9UL) +#define HSP_EVT_ISR_EOFWFEF_Msk (0x1UL << HSP_EVT_ISR_EOFWFEF_Pos) /*!< 0x00000200 */ +#define HSP_EVT_ISR_EOFWFEF HSP_EVT_ISR_EOFWFEF_Msk /*!< EOFWFEF (End of WFE flag) */ + +#define HSP_EVT_ISR_B0EVTF_Pos (12UL) +#define HSP_EVT_ISR_B0EVTF_Msk (0x1UL << HSP_EVT_ISR_B0EVTF_Pos) /*!< 0x00001000 */ +#define HSP_EVT_ISR_B0EVTF HSP_EVT_ISR_B0EVTF_Msk /*!< B0EVTF (BUFF0 event flag) */ + +#define HSP_EVT_ISR_B1EVTF_Pos (13UL) +#define HSP_EVT_ISR_B1EVTF_Msk (0x1UL << HSP_EVT_ISR_B1EVTF_Pos) /*!< 0x00002000 */ +#define HSP_EVT_ISR_B1EVTF HSP_EVT_ISR_B1EVTF_Msk /*!< B1EVTF (BUFF1 event flag) */ + +#define HSP_EVT_ISR_B2EVTF_Pos (14UL) +#define HSP_EVT_ISR_B2EVTF_Msk (0x1UL << HSP_EVT_ISR_B2EVTF_Pos) /*!< 0x00004000 */ +#define HSP_EVT_ISR_B2EVTF HSP_EVT_ISR_B2EVTF_Msk /*!< B2EVTF (BUFF2 event flag) */ + +#define HSP_EVT_ISR_B3EVTF_Pos (15UL) +#define HSP_EVT_ISR_B3EVTF_Msk (0x1UL << HSP_EVT_ISR_B3EVTF_Pos) /*!< 0x00008000 */ +#define HSP_EVT_ISR_B3EVTF HSP_EVT_ISR_B3EVTF_Msk /*!< B3EVTF (BUFF3 event flag) */ + +#define HSP_EVT_ISR_SOTECP0F_Pos (16UL) +#define HSP_EVT_ISR_SOTECP0F_Msk (0x1UL << HSP_EVT_ISR_SOTECP0F_Pos) /*!< 0x00010000 */ +#define HSP_EVT_ISR_SOTECP0F HSP_EVT_ISR_SOTECP0F_Msk /*!< SOTECP0F (Start of task flag, for event comparator 0) */ + +#define HSP_EVT_ISR_SOTECP1F_Pos (17UL) +#define HSP_EVT_ISR_SOTECP1F_Msk (0x1UL << HSP_EVT_ISR_SOTECP1F_Pos) /*!< 0x00020000 */ +#define HSP_EVT_ISR_SOTECP1F HSP_EVT_ISR_SOTECP1F_Msk /*!< SOTECP1F (Start of task flag, for event comparator 1) */ + +#define HSP_EVT_ISR_SOTECP2F_Pos (18UL) +#define HSP_EVT_ISR_SOTECP2F_Msk (0x1UL << HSP_EVT_ISR_SOTECP2F_Pos) /*!< 0x00040000 */ +#define HSP_EVT_ISR_SOTECP2F HSP_EVT_ISR_SOTECP2F_Msk /*!< SOTECP2F (Start of task flag, for event comparator 2) */ + +#define HSP_EVT_ISR_SOTECP3F_Pos (19UL) +#define HSP_EVT_ISR_SOTECP3F_Msk (0x1UL << HSP_EVT_ISR_SOTECP3F_Pos) /*!< 0x00080000 */ +#define HSP_EVT_ISR_SOTECP3F HSP_EVT_ISR_SOTECP3F_Msk /*!< SOTECP3F (Start of task flag, for event comparator 3) */ + +#define HSP_EVT_ISR_EOTECP0F_Pos (20UL) +#define HSP_EVT_ISR_EOTECP0F_Msk (0x1UL << HSP_EVT_ISR_EOTECP0F_Pos) /*!< 0x00100000 */ +#define HSP_EVT_ISR_EOTECP0F HSP_EVT_ISR_EOTECP0F_Msk /*!< EOTECP0F (End of task flag, for event comparator 0) */ + +#define HSP_EVT_ISR_EOTECP1F_Pos (21UL) +#define HSP_EVT_ISR_EOTECP1F_Msk (0x1UL << HSP_EVT_ISR_EOTECP1F_Pos) /*!< 0x00200000 */ +#define HSP_EVT_ISR_EOTECP1F HSP_EVT_ISR_EOTECP1F_Msk /*!< EOTECP1F (End of task flag, for event comparator 1) */ + +#define HSP_EVT_ISR_EOTECP2F_Pos (22UL) +#define HSP_EVT_ISR_EOTECP2F_Msk (0x1UL << HSP_EVT_ISR_EOTECP2F_Pos) /*!< 0x00400000 */ +#define HSP_EVT_ISR_EOTECP2F HSP_EVT_ISR_EOTECP2F_Msk /*!< EOTECP2F (End of task flag, for event comparator 2) */ + +#define HSP_EVT_ISR_EOTECP3F_Pos (23UL) +#define HSP_EVT_ISR_EOTECP3F_Msk (0x1UL << HSP_EVT_ISR_EOTECP3F_Pos) /*!< 0x00800000 */ +#define HSP_EVT_ISR_EOTECP3F HSP_EVT_ISR_EOTECP3F_Msk /*!< EOTECP3F (End of task flag, for event comparator 3) */ + +#define HSP_EVT_ISR_TOVLPF_Pos (28UL) +#define HSP_EVT_ISR_TOVLPF_Msk (0x1UL << HSP_EVT_ISR_TOVLPF_Pos) /*!< 0x10000000 */ +#define HSP_EVT_ISR_TOVLPF HSP_EVT_ISR_TOVLPF_Msk /*!< TOVLPF (Task overlap flag) */ + +#define HSP_EVT_ISR_FPUSATF_Pos (31UL) +#define HSP_EVT_ISR_FPUSATF_Msk (0x1UL << HSP_EVT_ISR_FPUSATF_Pos) /*!< 0x80000000 */ +#define HSP_EVT_ISR_FPUSATF HSP_EVT_ISR_FPUSATF_Msk /*!< FPUSATF (FPU saturation flag) */ + +/******************** Bit definition for HSP_PFCTEVT_ISR register ********************/ +#define HSP_PFCTEVT_ISR_PFCTF_Pos (0UL) +#define HSP_PFCTEVT_ISR_PFCTF_Msk (0xFFFFFFFFUL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PFCTEVT_ISR_PFCTF HSP_PFCTEVT_ISR_PFCTF_Msk /*!< PFCTF[31:0] bits (Flags generated by SPE processing functions ) */ +#define HSP_PFCTEVT_ISR_PFCTF_0 (0x00001UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000001 */ +#define HSP_PFCTEVT_ISR_PFCTF_1 (0x00002UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000002 */ +#define HSP_PFCTEVT_ISR_PFCTF_2 (0x00004UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000004 */ +#define HSP_PFCTEVT_ISR_PFCTF_3 (0x00008UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000008 */ +#define HSP_PFCTEVT_ISR_PFCTF_4 (0x00010UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000010 */ +#define HSP_PFCTEVT_ISR_PFCTF_5 (0x00020UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000020 */ +#define HSP_PFCTEVT_ISR_PFCTF_6 (0x00040UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000040 */ +#define HSP_PFCTEVT_ISR_PFCTF_7 (0x00080UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000080 */ +#define HSP_PFCTEVT_ISR_PFCTF_8 (0x00100UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000100 */ +#define HSP_PFCTEVT_ISR_PFCTF_9 (0x00200UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000200 */ +#define HSP_PFCTEVT_ISR_PFCTF_10 (0x00400UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000400 */ +#define HSP_PFCTEVT_ISR_PFCTF_11 (0x00800UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000800 */ +#define HSP_PFCTEVT_ISR_PFCTF_12 (0x01000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00001000 */ +#define HSP_PFCTEVT_ISR_PFCTF_13 (0x02000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00002000 */ +#define HSP_PFCTEVT_ISR_PFCTF_14 (0x04000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00004000 */ +#define HSP_PFCTEVT_ISR_PFCTF_15 (0x08000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00008000 */ +#define HSP_PFCTEVT_ISR_PFCTF_16 (0x10000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00010000 */ +#define HSP_PFCTEVT_ISR_PFCTF_17 (0x20000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00020000 */ +#define HSP_PFCTEVT_ISR_PFCTF_18 (0x40000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00040000 */ +#define HSP_PFCTEVT_ISR_PFCTF_19 (0x80000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00080000 */ +#define HSP_PFCTEVT_ISR_PFCTF_20 (0x100000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00100000 */ +#define HSP_PFCTEVT_ISR_PFCTF_21 (0x200000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00200000 */ +#define HSP_PFCTEVT_ISR_PFCTF_22 (0x400000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00400000 */ +#define HSP_PFCTEVT_ISR_PFCTF_23 (0x800000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00800000 */ +#define HSP_PFCTEVT_ISR_PFCTF_24 (0x1000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x01000000 */ +#define HSP_PFCTEVT_ISR_PFCTF_25 (0x2000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x02000000 */ +#define HSP_PFCTEVT_ISR_PFCTF_26 (0x4000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x04000000 */ +#define HSP_PFCTEVT_ISR_PFCTF_27 (0x8000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x08000000 */ +#define HSP_PFCTEVT_ISR_PFCTF_28 (0x10000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x10000000 */ +#define HSP_PFCTEVT_ISR_PFCTF_29 (0x20000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x20000000 */ +#define HSP_PFCTEVT_ISR_PFCTF_30 (0x40000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x40000000 */ +#define HSP_PFCTEVT_ISR_PFCTF_31 (0x80000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for HSP_ERRINFR register ********************/ +#define HSP_ERRINFR_INEXACT_Pos (0UL) +#define HSP_ERRINFR_INEXACT_Msk (0x1UL << HSP_ERRINFR_INEXACT_Pos) /*!< 0x00000001 */ +#define HSP_ERRINFR_INEXACT HSP_ERRINFR_INEXACT_Msk /*!< INEXACT (INEXACT exception flag) */ + +#define HSP_ERRINFR_UDFLOW_Pos (1UL) +#define HSP_ERRINFR_UDFLOW_Msk (0x1UL << HSP_ERRINFR_UDFLOW_Pos) /*!< 0x00000002 */ +#define HSP_ERRINFR_UDFLOW HSP_ERRINFR_UDFLOW_Msk /*!< UDFLOW (UNDERFLOW exception flag) */ + +#define HSP_ERRINFR_OVFLOW_Pos (2UL) +#define HSP_ERRINFR_OVFLOW_Msk (0x1UL << HSP_ERRINFR_OVFLOW_Pos) /*!< 0x00000004 */ +#define HSP_ERRINFR_OVFLOW HSP_ERRINFR_OVFLOW_Msk /*!< OVFLOW (OVERFLOW exception flag) */ + +#define HSP_ERRINFR_DIVZERO_Pos (3UL) +#define HSP_ERRINFR_DIVZERO_Msk (0x1UL << HSP_ERRINFR_DIVZERO_Pos) /*!< 0x00000008 */ +#define HSP_ERRINFR_DIVZERO HSP_ERRINFR_DIVZERO_Msk /*!< DIVZERO (Division by zero exception flag) */ + +#define HSP_ERRINFR_INVALID_Pos (4UL) +#define HSP_ERRINFR_INVALID_Msk (0x1UL << HSP_ERRINFR_INVALID_Pos) /*!< 0x00000010 */ +#define HSP_ERRINFR_INVALID HSP_ERRINFR_INVALID_Msk /*!< INVALID (INVALID exception flag) */ + +#define HSP_ERRINFR_DENORM_Pos (5UL) +#define HSP_ERRINFR_DENORM_Msk (0x1UL << HSP_ERRINFR_DENORM_Pos) /*!< 0x00000020 */ +#define HSP_ERRINFR_DENORM HSP_ERRINFR_DENORM_Msk /*!< DENORM (DENORMAL exception flag) */ + +#define HSP_ERRINFR_CMERR_Pos (8UL) +#define HSP_ERRINFR_CMERR_Msk (0x1UL << HSP_ERRINFR_CMERR_Pos) /*!< 0x00000100 */ +#define HSP_ERRINFR_CMERR HSP_ERRINFR_CMERR_Msk /*!< CMERR (Code memory access error flag) */ + +#define HSP_ERRINFR_DMERR_Pos (9UL) +#define HSP_ERRINFR_DMERR_Msk (0x1UL << HSP_ERRINFR_DMERR_Pos) /*!< 0x00000200 */ +#define HSP_ERRINFR_DMERR HSP_ERRINFR_DMERR_Msk /*!< DMERR (Data memory access error flag) */ + +#define HSP_ERRINFR_MAHBERR_Pos (11UL) +#define HSP_ERRINFR_MAHBERR_Msk (0x1UL << HSP_ERRINFR_MAHBERR_Pos) /*!< 0x00000800 */ +#define HSP_ERRINFR_MAHBERR HSP_ERRINFR_MAHBERR_Msk /*!< MAHBERR (Internal AHB access error flag) */ + +#define HSP_ERRINFR_SAHBERR_Pos (12UL) +#define HSP_ERRINFR_SAHBERR_Msk (0x1UL << HSP_ERRINFR_SAHBERR_Pos) /*!< 0x00001000 */ +#define HSP_ERRINFR_SAHBERR HSP_ERRINFR_SAHBERR_Msk /*!< SAHBERR (Slave AHB access error flag) */ + +#define HSP_ERRINFR_TRGIERR_Pos (16UL) +#define HSP_ERRINFR_TRGIERR_Msk (0x3FFUL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x03FF0000 */ +#define HSP_ERRINFR_TRGIERR HSP_ERRINFR_TRGIERR_Msk /*!< TRGIERR[9:0] bits (TRGIN error information) */ +#define HSP_ERRINFR_TRGIERR_0 (0x001UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00010000 */ +#define HSP_ERRINFR_TRGIERR_1 (0x002UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00020000 */ +#define HSP_ERRINFR_TRGIERR_2 (0x004UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00040000 */ +#define HSP_ERRINFR_TRGIERR_3 (0x008UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00080000 */ +#define HSP_ERRINFR_TRGIERR_4 (0x010UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00100000 */ +#define HSP_ERRINFR_TRGIERR_5 (0x020UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00200000 */ +#define HSP_ERRINFR_TRGIERR_6 (0x040UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00400000 */ +#define HSP_ERRINFR_TRGIERR_7 (0x080UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00800000 */ +#define HSP_ERRINFR_TRGIERR_8 (0x100UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x01000000 */ +#define HSP_ERRINFR_TRGIERR_9 (0x200UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x02000000 */ + +/******************** Bit definition for HSP_ERR_ICR register ********************/ +#define HSP_ERR_ICR_TRGIOVRC_Pos (8UL) +#define HSP_ERR_ICR_TRGIOVRC_Msk (0x1UL << HSP_ERR_ICR_TRGIOVRC_Pos) /*!< 0x00000100 */ +#define HSP_ERR_ICR_TRGIOVRC HSP_ERR_ICR_TRGIOVRC_Msk /*!< TRGIOVRC (Clear TRGIOVRF flag) */ + +#define HSP_ERR_ICR_B0ERRC_Pos (12UL) +#define HSP_ERR_ICR_B0ERRC_Msk (0x1UL << HSP_ERR_ICR_B0ERRC_Pos) /*!< 0x00001000 */ +#define HSP_ERR_ICR_B0ERRC HSP_ERR_ICR_B0ERRC_Msk /*!< B0ERRC (Clear B0ERRF flag) */ + +#define HSP_ERR_ICR_B1ERRC_Pos (13UL) +#define HSP_ERR_ICR_B1ERRC_Msk (0x1UL << HSP_ERR_ICR_B1ERRC_Pos) /*!< 0x00002000 */ +#define HSP_ERR_ICR_B1ERRC HSP_ERR_ICR_B1ERRC_Msk /*!< B1ERRC (Clear B1ERRF flag) */ + +#define HSP_ERR_ICR_B2ERRC_Pos (14UL) +#define HSP_ERR_ICR_B2ERRC_Msk (0x1UL << HSP_ERR_ICR_B2ERRC_Pos) /*!< 0x00004000 */ +#define HSP_ERR_ICR_B2ERRC HSP_ERR_ICR_B2ERRC_Msk /*!< B2ERRC (Clear B2ERRF flag) */ + +#define HSP_ERR_ICR_B3ERRC_Pos (15UL) +#define HSP_ERR_ICR_B3ERRC_Msk (0x1UL << HSP_ERR_ICR_B3ERRC_Pos) /*!< 0x00008000 */ +#define HSP_ERR_ICR_B3ERRC HSP_ERR_ICR_B3ERRC_Msk /*!< B3ERRC (Clear B3ERRF flag) */ + +#define HSP_ERR_ICR_CAPOVRC_Pos (16UL) +#define HSP_ERR_ICR_CAPOVRC_Msk (0x1UL << HSP_ERR_ICR_CAPOVRC_Pos) /*!< 0x00010000 */ +#define HSP_ERR_ICR_CAPOVRC HSP_ERR_ICR_CAPOVRC_Msk /*!< CAPOVRC (Clear CAPOVRF flag) */ + +#define HSP_ERR_ICR_FWERRC_Pos (17UL) +#define HSP_ERR_ICR_FWERRC_Msk (0x1UL << HSP_ERR_ICR_FWERRC_Pos) /*!< 0x00020000 */ +#define HSP_ERR_ICR_FWERRC HSP_ERR_ICR_FWERRC_Msk /*!< FWERRC (Clear FWERRF flag) */ + +#define HSP_ERR_ICR_SCHERRC_Pos (18UL) +#define HSP_ERR_ICR_SCHERRC_Msk (0x1UL << HSP_ERR_ICR_SCHERRC_Pos) /*!< 0x00040000 */ +#define HSP_ERR_ICR_SCHERRC HSP_ERR_ICR_SCHERRC_Msk /*!< SCHERRC (Clear SCHERRF flag) */ + +#define HSP_ERR_ICR_BKINC_Pos (19UL) +#define HSP_ERR_ICR_BKINC_Msk (0x1UL << HSP_ERR_ICR_BKINC_Pos) /*!< 0x00080000 */ +#define HSP_ERR_ICR_BKINC HSP_ERR_ICR_BKINC_Msk /*!< BKINC (Clear BKINF flag) */ + +#define HSP_ERR_ICR_HDEGOVRC_Pos (20UL) +#define HSP_ERR_ICR_HDEGOVRC_Msk (0x1UL << HSP_ERR_ICR_HDEGOVRC_Pos) /*!< 0x00100000 */ +#define HSP_ERR_ICR_HDEGOVRC HSP_ERR_ICR_HDEGOVRC_Msk /*!< HDEGOVRC (Clear HDEGOVRF flag) */ + +#define HSP_ERR_ICR_OPCOERRC_Pos (22UL) +#define HSP_ERR_ICR_OPCOERRC_Msk (0x1UL << HSP_ERR_ICR_OPCOERRC_Pos) /*!< 0x00400000 */ +#define HSP_ERR_ICR_OPCOERRC HSP_ERR_ICR_OPCOERRC_Msk /*!< OPCOERRC (Clear OPCOERRF flag) */ + +#define HSP_ERR_ICR_ACCERRC_Pos (23UL) +#define HSP_ERR_ICR_ACCERRC_Msk (0x1UL << HSP_ERR_ICR_ACCERRC_Pos) /*!< 0x00800000 */ +#define HSP_ERR_ICR_ACCERRC HSP_ERR_ICR_ACCERRC_Msk /*!< ACCERRC (Clear ACCERRF flag) */ + +#define HSP_ERR_ICR_FPUERRC_Pos (24UL) +#define HSP_ERR_ICR_FPUERRC_Msk (0x1UL << HSP_ERR_ICR_FPUERRC_Pos) /*!< 0x01000000 */ +#define HSP_ERR_ICR_FPUERRC HSP_ERR_ICR_FPUERRC_Msk /*!< FPUERRC (Clear FPUERRF flag) */ + +/******************** Bit definition for HSP_EVT_ICR register ********************/ +#define HSP_EVT_ICR_H2CMRDYC_Pos (0UL) +#define HSP_EVT_ICR_H2CMRDYC_Msk (0x1UL << HSP_EVT_ICR_H2CMRDYC_Pos) /*!< 0x00000001 */ +#define HSP_EVT_ICR_H2CMRDYC HSP_EVT_ICR_H2CMRDYC_Msk /*!< H2CMRDYC (Clear H2CMRDYF flag) */ + +#define HSP_EVT_ICR_C2HMFREEC_Pos (1UL) +#define HSP_EVT_ICR_C2HMFREEC_Msk (0x1UL << HSP_EVT_ICR_C2HMFREEC_Pos) /*!< 0x00000002 */ +#define HSP_EVT_ICR_C2HMFREEC HSP_EVT_ICR_C2HMFREEC_Msk /*!< C2HMFREEC (Clear C2HMFREEF flag) */ + +#define HSP_EVT_ICR_DCDONEC_Pos (2UL) +#define HSP_EVT_ICR_DCDONEC_Msk (0x1UL << HSP_EVT_ICR_DCDONEC_Pos) /*!< 0x00000004 */ +#define HSP_EVT_ICR_DCDONEC HSP_EVT_ICR_DCDONEC_Msk /*!< DCDONEC (Clear DCDONEF flag) */ + +#define HSP_EVT_ICR_CDEGRDYC_Pos (7UL) +#define HSP_EVT_ICR_CDEGRDYC_Msk (0x1UL << HSP_EVT_ICR_CDEGRDYC_Pos) /*!< 0x00000080 */ +#define HSP_EVT_ICR_CDEGRDYC HSP_EVT_ICR_CDEGRDYC_Msk /*!< CDEGRDYC (Clear of CDEGRDYF flag) */ + +#define HSP_EVT_ICR_SOFWFEC_Pos (8UL) +#define HSP_EVT_ICR_SOFWFEC_Msk (0x1UL << HSP_EVT_ICR_SOFWFEC_Pos) /*!< 0x00000100 */ +#define HSP_EVT_ICR_SOFWFEC HSP_EVT_ICR_SOFWFEC_Msk /*!< SOFWFEC (Clear of SOFWFEF flag) */ + +#define HSP_EVT_ICR_EOFWFEC_Pos (9UL) +#define HSP_EVT_ICR_EOFWFEC_Msk (0x1UL << HSP_EVT_ICR_EOFWFEC_Pos) /*!< 0x00000200 */ +#define HSP_EVT_ICR_EOFWFEC HSP_EVT_ICR_EOFWFEC_Msk /*!< EOFWFEC (Clear of EOFWFEF flag) */ + +#define HSP_EVT_ICR_SOTECP0C_Pos (16UL) +#define HSP_EVT_ICR_SOTECP0C_Msk (0x1UL << HSP_EVT_ICR_SOTECP0C_Pos) /*!< 0x00010000 */ +#define HSP_EVT_ICR_SOTECP0C HSP_EVT_ICR_SOTECP0C_Msk /*!< SOTECP0C (Clear SOTECP0F flag) */ + +#define HSP_EVT_ICR_SOTECP1C_Pos (17UL) +#define HSP_EVT_ICR_SOTECP1C_Msk (0x1UL << HSP_EVT_ICR_SOTECP1C_Pos) /*!< 0x00020000 */ +#define HSP_EVT_ICR_SOTECP1C HSP_EVT_ICR_SOTECP1C_Msk /*!< SOTECP1C (Clear SOTECP1F flag) */ + +#define HSP_EVT_ICR_SOTECP2C_Pos (18UL) +#define HSP_EVT_ICR_SOTECP2C_Msk (0x1UL << HSP_EVT_ICR_SOTECP2C_Pos) /*!< 0x00040000 */ +#define HSP_EVT_ICR_SOTECP2C HSP_EVT_ICR_SOTECP2C_Msk /*!< SOTECP2C (Clear SOTECP2F flag) */ + +#define HSP_EVT_ICR_SOTECP3C_Pos (19UL) +#define HSP_EVT_ICR_SOTECP3C_Msk (0x1UL << HSP_EVT_ICR_SOTECP3C_Pos) /*!< 0x00080000 */ +#define HSP_EVT_ICR_SOTECP3C HSP_EVT_ICR_SOTECP3C_Msk /*!< SOTECP3C (Clear SOTECP3F flag) */ + +#define HSP_EVT_ICR_EOTECP0C_Pos (20UL) +#define HSP_EVT_ICR_EOTECP0C_Msk (0x1UL << HSP_EVT_ICR_EOTECP0C_Pos) /*!< 0x00100000 */ +#define HSP_EVT_ICR_EOTECP0C HSP_EVT_ICR_EOTECP0C_Msk /*!< EOTECP0C (Clear EOTECP0F flag) */ + +#define HSP_EVT_ICR_EOTECP1C_Pos (21UL) +#define HSP_EVT_ICR_EOTECP1C_Msk (0x1UL << HSP_EVT_ICR_EOTECP1C_Pos) /*!< 0x00200000 */ +#define HSP_EVT_ICR_EOTECP1C HSP_EVT_ICR_EOTECP1C_Msk /*!< EOTECP1C (Clear EOTECP1F flag) */ + +#define HSP_EVT_ICR_EOTECP2C_Pos (22UL) +#define HSP_EVT_ICR_EOTECP2C_Msk (0x1UL << HSP_EVT_ICR_EOTECP2C_Pos) /*!< 0x00400000 */ +#define HSP_EVT_ICR_EOTECP2C HSP_EVT_ICR_EOTECP2C_Msk /*!< EOTECP2C (Clear EOTECP2F flag) */ + +#define HSP_EVT_ICR_EOTECP3C_Pos (23UL) +#define HSP_EVT_ICR_EOTECP3C_Msk (0x1UL << HSP_EVT_ICR_EOTECP3C_Pos) /*!< 0x00800000 */ +#define HSP_EVT_ICR_EOTECP3C HSP_EVT_ICR_EOTECP3C_Msk /*!< EOTECP3C (Clear EOTECP3F flag) */ + +#define HSP_EVT_ICR_TOVLPC_Pos (28UL) +#define HSP_EVT_ICR_TOVLPC_Msk (0x1UL << HSP_EVT_ICR_TOVLPC_Pos) /*!< 0x10000000 */ +#define HSP_EVT_ICR_TOVLPC HSP_EVT_ICR_TOVLPC_Msk /*!< TOVLPC (Clear TOVLPF flag) */ + +#define HSP_EVT_ICR_FPUSATC_Pos (31UL) +#define HSP_EVT_ICR_FPUSATC_Msk (0x1UL << HSP_EVT_ICR_FPUSATC_Pos) /*!< 0x80000000 */ +#define HSP_EVT_ICR_FPUSATC HSP_EVT_ICR_FPUSATC_Msk /*!< FPUSATC (Clear FPUSATF flag) */ + +/******************** Bit definition for HSP_PFCTEVT_ICR register ********************/ +#define HSP_PFCTEVT_ICR_PFCTC_Pos (0UL) +#define HSP_PFCTEVT_ICR_PFCTC_Msk (0xFFFFFFFFUL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PFCTEVT_ICR_PFCTC HSP_PFCTEVT_ICR_PFCTC_Msk /*!< PFCTC[31:0] bits (Clear PFCTF[31:0] flag) */ +#define HSP_PFCTEVT_ICR_PFCTC_0 (0x00001UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000001 */ +#define HSP_PFCTEVT_ICR_PFCTC_1 (0x00002UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000002 */ +#define HSP_PFCTEVT_ICR_PFCTC_2 (0x00004UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000004 */ +#define HSP_PFCTEVT_ICR_PFCTC_3 (0x00008UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000008 */ +#define HSP_PFCTEVT_ICR_PFCTC_4 (0x00010UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000010 */ +#define HSP_PFCTEVT_ICR_PFCTC_5 (0x00020UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000020 */ +#define HSP_PFCTEVT_ICR_PFCTC_6 (0x00040UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000040 */ +#define HSP_PFCTEVT_ICR_PFCTC_7 (0x00080UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000080 */ +#define HSP_PFCTEVT_ICR_PFCTC_8 (0x00100UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000100 */ +#define HSP_PFCTEVT_ICR_PFCTC_9 (0x00200UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000200 */ +#define HSP_PFCTEVT_ICR_PFCTC_10 (0x00400UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000400 */ +#define HSP_PFCTEVT_ICR_PFCTC_11 (0x00800UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000800 */ +#define HSP_PFCTEVT_ICR_PFCTC_12 (0x01000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00001000 */ +#define HSP_PFCTEVT_ICR_PFCTC_13 (0x02000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00002000 */ +#define HSP_PFCTEVT_ICR_PFCTC_14 (0x04000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00004000 */ +#define HSP_PFCTEVT_ICR_PFCTC_15 (0x08000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00008000 */ +#define HSP_PFCTEVT_ICR_PFCTC_16 (0x10000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00010000 */ +#define HSP_PFCTEVT_ICR_PFCTC_17 (0x20000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00020000 */ +#define HSP_PFCTEVT_ICR_PFCTC_18 (0x40000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00040000 */ +#define HSP_PFCTEVT_ICR_PFCTC_19 (0x80000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00080000 */ +#define HSP_PFCTEVT_ICR_PFCTC_20 (0x100000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00100000 */ +#define HSP_PFCTEVT_ICR_PFCTC_21 (0x200000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00200000 */ +#define HSP_PFCTEVT_ICR_PFCTC_22 (0x400000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00400000 */ +#define HSP_PFCTEVT_ICR_PFCTC_23 (0x800000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00800000 */ +#define HSP_PFCTEVT_ICR_PFCTC_24 (0x1000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x01000000 */ +#define HSP_PFCTEVT_ICR_PFCTC_25 (0x2000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x02000000 */ +#define HSP_PFCTEVT_ICR_PFCTC_26 (0x4000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x04000000 */ +#define HSP_PFCTEVT_ICR_PFCTC_27 (0x8000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x08000000 */ +#define HSP_PFCTEVT_ICR_PFCTC_28 (0x10000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x10000000 */ +#define HSP_PFCTEVT_ICR_PFCTC_29 (0x20000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x20000000 */ +#define HSP_PFCTEVT_ICR_PFCTC_30 (0x40000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x40000000 */ +#define HSP_PFCTEVT_ICR_PFCTC_31 (0x80000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for HSP_FWVERR register ********************/ +#define HSP_FWVERR_CRAMINREV_Pos (0UL) +#define HSP_FWVERR_CRAMINREV_Msk (0xFFUL << HSP_FWVERR_CRAMINREV_Pos) /*!< 0x000000FF */ +#define HSP_FWVERR_CRAMINREV HSP_FWVERR_CRAMINREV_Msk /*!< CRAMINREV[7:0] bits (Code RAM Minor revision) */ + +#define HSP_FWVERR_CRAMAJREV_Pos (8UL) +#define HSP_FWVERR_CRAMAJREV_Msk (0xFUL << HSP_FWVERR_CRAMAJREV_Pos) /*!< 0x00000F00 */ +#define HSP_FWVERR_CRAMAJREV HSP_FWVERR_CRAMAJREV_Msk /*!< CRAMAJREV[3:0] bits (Code RAM Major revision) */ + +#define HSP_FWVERR_CROMINREV_Pos (12UL) +#define HSP_FWVERR_CROMINREV_Msk (0xFFUL << HSP_FWVERR_CROMINREV_Pos) /*!< 0x000FF000 */ +#define HSP_FWVERR_CROMINREV HSP_FWVERR_CROMINREV_Msk /*!< CROMINREV[7:0] bits (Code ROM Minor revision) */ + +#define HSP_FWVERR_CROMAJREV_Pos (20UL) +#define HSP_FWVERR_CROMAJREV_Msk (0xFUL << HSP_FWVERR_CROMAJREV_Pos) /*!< 0x000F0000 */ +#define HSP_FWVERR_CROMAJREV HSP_FWVERR_CROMAJREV_Msk /*!< CROMAJREV[3:0] bits (Code ROM Major revision) */ + +#define HSP_FWVERR_DROMINREV_Pos (24UL) +#define HSP_FWVERR_DROMINREV_Msk (0xFUL << HSP_FWVERR_DROMINREV_Pos) /*!< 0x00F00000 */ +#define HSP_FWVERR_DROMINREV HSP_FWVERR_DROMINREV_Msk /*!< DROMINREV[3:0] bits (Data ROM Minor revision) */ + +#define HSP_FWVERR_DROMAJREV_Pos (28UL) +#define HSP_FWVERR_DROMAJREV_Msk (0xFUL << HSP_FWVERR_DROMAJREV_Pos) /*!< 0x0F000000 */ +#define HSP_FWVERR_DROMAJREV HSP_FWVERR_DROMAJREV_Msk /*!< DROMAJREV[3:0] bits (Data ROM Major revision) */ + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0UL) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1UL) +#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2UL) +#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3UL) +#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4UL) +#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5UL) +#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6UL) +#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7UL) +#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8UL) +#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12UL) +#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_SWRST_Pos (13UL) +#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ +#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ +#define I2C_CR1_TXDMAEN_Pos (14UL) +#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15UL) +#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16UL) +#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17UL) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18UL) +#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19UL) +#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20UL) +#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21UL) +#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22UL) +#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23UL) +#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ +#define I2C_CR1_FMP_Pos (24UL) +#define I2C_CR1_FMP_Msk (0x1UL << I2C_CR1_FMP_Pos) /*!< 0x01000000 */ +#define I2C_CR1_FMP I2C_CR1_FMP_Msk /*!< FMP enable */ +#define I2C_CR1_ADDRACLR_Pos (30UL) +#define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ +#define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ +#define I2C_CR1_STOPFACLR_Pos (31UL) +#define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ +#define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0UL) +#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10UL) +#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11UL) +#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12UL) +#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13UL) +#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14UL) +#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15UL) +#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16UL) +#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24UL) +#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25UL) +#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26UL) +#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0UL) +#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10UL) +#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15UL) +#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1UL) +#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8UL) +#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8UL) +#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9UL) +#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8UL) +#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10UL) +#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8UL) +#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9UL) +#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8UL) +#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15UL) +#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *******************/ +#define I2C_TIMINGR_SCLL_Pos (0UL) +#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8UL) +#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16UL) +#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20UL) +#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28UL) +#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *******************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0UL) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12UL) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15UL) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16UL) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31UL) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE_Pos (0UL) +#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1UL) +#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2UL) +#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3UL) +#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4UL) +#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5UL) +#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6UL) +#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7UL) +#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8UL) +#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9UL) +#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10UL) +#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11UL) +#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12UL) +#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13UL) +#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15UL) +#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16UL) +#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17UL) +#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF_Pos (3UL) +#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4UL) +#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5UL) +#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8UL) +#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9UL) +#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10UL) +#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11UL) +#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12UL) +#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13UL) +#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register *********************/ +#define I2C_PECR_PEC_Pos (0UL) +#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0UL) +#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA_Pos (0UL) +#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ + +/****************** Bit definition for I2C_AUTOCR register ********************/ +#define I2C_AUTOCR_TCDMAEN_Pos (6UL) +#define I2C_AUTOCR_TCDMAEN_Msk (0x1UL << I2C_AUTOCR_TCDMAEN_Pos) /*!< 0x00000040 */ +#define I2C_AUTOCR_TCDMAEN I2C_AUTOCR_TCDMAEN_Msk /*!< DMA request enable on Transfer Complete event */ +#define I2C_AUTOCR_TCRDMAEN_Pos (7UL) +#define I2C_AUTOCR_TCRDMAEN_Msk (0x1UL << I2C_AUTOCR_TCRDMAEN_Pos) /*!< 0x00000080 */ +#define I2C_AUTOCR_TCRDMAEN I2C_AUTOCR_TCRDMAEN_Msk /*!< DMA request enable on Transfer Complete Reload event */ +#define I2C_AUTOCR_TRIGSEL_Pos (16UL) +#define I2C_AUTOCR_TRIGSEL_Msk (0xFUL << I2C_AUTOCR_TRIGSEL_Pos) /*!< 0x000F0000 */ +#define I2C_AUTOCR_TRIGSEL I2C_AUTOCR_TRIGSEL_Msk /*!< Trigger selection */ +#define I2C_AUTOCR_TRIGPOL_Pos (20UL) +#define I2C_AUTOCR_TRIGPOL_Msk (0x1UL << I2C_AUTOCR_TRIGPOL_Pos) /*!< 0x000100000 */ +#define I2C_AUTOCR_TRIGPOL I2C_AUTOCR_TRIGPOL_Msk /*!< Trigger polarity */ +#define I2C_AUTOCR_TRIGEN_Pos (21UL) +#define I2C_AUTOCR_TRIGEN_Msk (0x1UL << I2C_AUTOCR_TRIGEN_Pos) /*!< 0x000200000 */ +#define I2C_AUTOCR_TRIGEN I2C_AUTOCR_TRIGEN_Msk /*!< Trigger enable */ + +/******************************************************************************/ +/* */ +/* Improved Inter-integrated Circuit Interface (I3C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I3C_CR register *********************/ +#define I3C_CR_DCNT_Pos (0UL) +#define I3C_CR_DCNT_Msk (0xFFFFUL << I3C_CR_DCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_CR_DCNT I3C_CR_DCNT_Msk /*!< Data Byte Count */ +#define I3C_CR_RNW_Pos (16UL) +#define I3C_CR_RNW_Msk (0x1UL << I3C_CR_RNW_Pos) /*!< 0x00010000 */ +#define I3C_CR_RNW I3C_CR_RNW_Msk /*!< Read Not Write */ +#define I3C_CR_CCC_Pos (16UL) +#define I3C_CR_CCC_Msk (0xFFUL << I3C_CR_CCC_Pos) /*!< 0x00FF0000 */ +#define I3C_CR_CCC I3C_CR_CCC_Msk /*!< 8-Bit CCC code */ +#define I3C_CR_ADD_Pos (17UL) +#define I3C_CR_ADD_Msk (0x7FUL << I3C_CR_ADD_Pos) /*!< 0x00FE0000 */ +#define I3C_CR_ADD I3C_CR_ADD_Msk /*!< Target Address */ +#define I3C_CR_MTYPE_Pos (27UL) +#define I3C_CR_MTYPE_Msk (0xFUL << I3C_CR_MTYPE_Pos) /*!< 0xF8000000 */ +#define I3C_CR_MTYPE I3C_CR_MTYPE_Msk /*!< Message Type */ +#define I3C_CR_MTYPE_0 (0x1UL << I3C_CR_MTYPE_Pos) /*!< 0x08000000 */ +#define I3C_CR_MTYPE_1 (0x2UL << I3C_CR_MTYPE_Pos) /*!< 0x10000000 */ +#define I3C_CR_MTYPE_2 (0x4UL << I3C_CR_MTYPE_Pos) /*!< 0x20000000 */ +#define I3C_CR_MTYPE_3 (0x8UL << I3C_CR_MTYPE_Pos) /*!< 0x40000000 */ +#define I3C_CR_MEND_Pos (31UL) +#define I3C_CR_MEND_Msk (0x1UL << I3C_CR_MEND_Pos) /*!< 0x80000000 */ +#define I3C_CR_MEND I3C_CR_MEND_Msk /*!< Message End */ + +/******************* Bit definition for I3C_CFGR register *******************/ +#define I3C_CFGR_EN_Pos (0UL) +#define I3C_CFGR_EN_Msk (0x1UL << I3C_CFGR_EN_Pos) /*!< 0x00000001 */ +#define I3C_CFGR_EN I3C_CFGR_EN_Msk /*!< Peripheral Enable */ +#define I3C_CFGR_CRINIT_Pos (1UL) +#define I3C_CFGR_CRINIT_Msk (0x1UL << I3C_CFGR_CRINIT_Pos) /*!< 0x00000002 */ +#define I3C_CFGR_CRINIT I3C_CFGR_CRINIT_Msk /*!< Peripheral Init mode (Target/Controller) */ +#define I3C_CFGR_NOARBH_Pos (2UL) +#define I3C_CFGR_NOARBH_Msk (0x1UL << I3C_CFGR_NOARBH_Pos) /*!< 0x00000004 */ +#define I3C_CFGR_NOARBH I3C_CFGR_NOARBH_Msk /*!< No Arbitration Header (7'h7E)*/ +#define I3C_CFGR_RSTPTRN_Pos (3UL) +#define I3C_CFGR_RSTPTRN_Msk (0x1UL << I3C_CFGR_RSTPTRN_Pos) /*!< 0x00000008 */ +#define I3C_CFGR_RSTPTRN I3C_CFGR_RSTPTRN_Msk /*!< Reset Pattern enable */ +#define I3C_CFGR_EXITPTRN_Pos (4UL) +#define I3C_CFGR_EXITPTRN_Msk (0x1UL << I3C_CFGR_EXITPTRN_Pos) /*!< 0x00000010 */ +#define I3C_CFGR_EXITPTRN I3C_CFGR_EXITPTRN_Msk /*!< Exit Pattern enable */ +#define I3C_CFGR_HKSDAEN_Pos (5UL) +#define I3C_CFGR_HKSDAEN_Msk (0x1UL << I3C_CFGR_HKSDAEN_Pos) /*!< 0x00000020 */ +#define I3C_CFGR_HKSDAEN I3C_CFGR_HKSDAEN_Msk /*!< High-Keeper on SDA Enable */ +#define I3C_CFGR_HJACK_Pos (7UL) +#define I3C_CFGR_HJACK_Msk (0x1UL << I3C_CFGR_HJACK_Pos) /*!< 0x00000080 */ +#define I3C_CFGR_HJACK I3C_CFGR_HJACK_Msk /*!< Hot Join Acknowledgment */ +#define I3C_CFGR_RXDMAEN_Pos (8UL) +#define I3C_CFGR_RXDMAEN_Msk (0x1UL << I3C_CFGR_RXDMAEN_Pos) /*!< 0x00000100 */ +#define I3C_CFGR_RXDMAEN I3C_CFGR_RXDMAEN_Msk /*!< RX FIFO DMA mode Enable */ +#define I3C_CFGR_RXFLUSH_Pos (9UL) +#define I3C_CFGR_RXFLUSH_Msk (0x1UL << I3C_CFGR_RXFLUSH_Pos) /*!< 0x00000200 */ +#define I3C_CFGR_RXFLUSH I3C_CFGR_RXFLUSH_Msk /*!< RX FIFO Flush */ +#define I3C_CFGR_RXTHRES_Pos (10UL) +#define I3C_CFGR_RXTHRES_Msk (0x1UL << I3C_CFGR_RXTHRES_Pos) /*!< 0x00000400 */ +#define I3C_CFGR_RXTHRES I3C_CFGR_RXTHRES_Msk /*!< RX FIFO Threshold */ +#define I3C_CFGR_TXDMAEN_Pos (12UL) +#define I3C_CFGR_TXDMAEN_Msk (0x1UL << I3C_CFGR_TXDMAEN_Pos) /*!< 0x00001000 */ +#define I3C_CFGR_TXDMAEN I3C_CFGR_TXDMAEN_Msk /*!< TX FIFO DMA mode Enable */ +#define I3C_CFGR_TXFLUSH_Pos (13UL) +#define I3C_CFGR_TXFLUSH_Msk (0x1UL << I3C_CFGR_TXFLUSH_Pos) /*!< 0x00002000 */ +#define I3C_CFGR_TXFLUSH I3C_CFGR_TXFLUSH_Msk /*!< TX FIFO Flush */ +#define I3C_CFGR_TXTHRES_Pos (14UL) +#define I3C_CFGR_TXTHRES_Msk (0x1UL << I3C_CFGR_TXTHRES_Pos) /*!< 0x00004000 */ +#define I3C_CFGR_TXTHRES I3C_CFGR_TXTHRES_Msk /*!< TX FIFO Threshold */ +#define I3C_CFGR_SDMAEN_Pos (16UL) +#define I3C_CFGR_SDMAEN_Msk (0x1UL << I3C_CFGR_SDMAEN_Pos) /*!< 0x00010000 */ +#define I3C_CFGR_SDMAEN I3C_CFGR_SDMAEN_Msk /*!< Status FIFO DMA mode Enable */ +#define I3C_CFGR_SFLUSH_Pos (17UL) +#define I3C_CFGR_SFLUSH_Msk (0x1UL << I3C_CFGR_SFLUSH_Pos) /*!< 0x00020000 */ +#define I3C_CFGR_SFLUSH I3C_CFGR_SFLUSH_Msk /*!< Status FIFO Flush */ +#define I3C_CFGR_SMODE_Pos (18UL) +#define I3C_CFGR_SMODE_Msk (0x1UL << I3C_CFGR_SMODE_Pos) /*!< 0x00040000 */ +#define I3C_CFGR_SMODE I3C_CFGR_SMODE_Msk /*!< Status FIFO mode Enable */ +#define I3C_CFGR_TMODE_Pos (19UL) +#define I3C_CFGR_TMODE_Msk (0x1UL << I3C_CFGR_TMODE_Pos) /*!< 0x00080000 */ +#define I3C_CFGR_TMODE I3C_CFGR_TMODE_Msk /*!< Control FIFO mode Enable */ +#define I3C_CFGR_CDMAEN_Pos (20UL) +#define I3C_CFGR_CDMAEN_Msk (0x1UL << I3C_CFGR_CDMAEN_Pos) /*!< 0x00100000 */ +#define I3C_CFGR_CDMAEN I3C_CFGR_CDMAEN_Msk /*!< Control FIFO DMA mode Enable */ +#define I3C_CFGR_CFLUSH_Pos (21UL) +#define I3C_CFGR_CFLUSH_Msk (0x1UL << I3C_CFGR_CFLUSH_Pos) /*!< 0x00200000 */ +#define I3C_CFGR_CFLUSH I3C_CFGR_CFLUSH_Msk /*!< Control FIFO Flush */ +#define I3C_CFGR_FCFDIS_Pos (23UL) +#define I3C_CFGR_FCFDIS_Msk (0x1UL << I3C_CFGR_FCFDIS_Pos) /*!< 0x00800000 */ +#define I3C_CFGR_FCFDIS I3C_CFGR_FCFDIS_Msk /*!< FCF generation disable */ +#define I3C_CFGR_TRIGSEL_Pos (24UL) +#define I3C_CFGR_TRIGSEL_Msk (0xFUL << I3C_CFGR_TRIGSEL_Pos) /*!< 0x0F000000 */ +#define I3C_CFGR_TRIGSEL I3C_CFGR_TRIGSEL_Msk /*!< Trigger selection */ +#define I3C_CFGR_TRIGPOL_Pos (28UL) +#define I3C_CFGR_TRIGPOL_Msk (0x1UL << I3C_CFGR_TRIGPOL_Pos) /*!< 0x10000000 */ +#define I3C_CFGR_TRIGPOL I3C_CFGR_TRIGPOL_Msk /*!< Trigger polarity */ +#define I3C_CFGR_TRIGHWEN_Pos (29UL) +#define I3C_CFGR_TRIGHWEN_Msk (0x1UL << I3C_CFGR_TRIGHWEN_Pos) /*!< 0x20000000 */ +#define I3C_CFGR_TRIGHWEN I3C_CFGR_TRIGHWEN_Msk /*!< Trigger enable */ +#define I3C_CFGR_TSFSET_Pos (30UL) +#define I3C_CFGR_TSFSET_Msk (0x1UL << I3C_CFGR_TSFSET_Pos) /*!< 0x40000000 */ +#define I3C_CFGR_TSFSET I3C_CFGR_TSFSET_Msk /*!< Transfer Set */ + +/******************* Bit definition for I3C_RDR register ********************/ +#define I3C_RDR_RDB0_Pos (0UL) +#define I3C_RDR_RDB0_Msk (0xFFUL << I3C_RDR_RDB0_Pos) /*!< 0x000000FF */ +#define I3C_RDR_RDB0 I3C_RDR_RDB0_Msk /*!< Receive Data Byte */ + +/****************** Bit definition for I3C_RDWR register ********************/ +#define I3C_RDWR_RDBx_Pos (0UL) +#define I3C_RDWR_RDBx_Msk (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_RDWR_RDBx I3C_RDWR_RDBx_Msk /*!< Receive Data Byte, full double word */ +#define I3C_RDWR_RDB0_Pos (0UL) +#define I3C_RDWR_RDB0_Msk (0xFFUL << I3C_RDWR_RDB0_Pos) /*!< 0x000000FF */ +#define I3C_RDWR_RDB0 I3C_RDWR_RDB0_Msk /*!< Receive Data Byte 0 */ +#define I3C_RDWR_RDB1_Pos (8UL) +#define I3C_RDWR_RDB1_Msk (0xFFUL << I3C_RDWR_RDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_RDWR_RDB1 I3C_RDWR_RDB1_Msk /*!< Receive Data Byte 1 */ +#define I3C_RDWR_RDB2_Pos (16UL) +#define I3C_RDWR_RDB2_Msk (0xFFUL << I3C_RDWR_RDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_RDWR_RDB2 I3C_RDWR_RDB2_Msk /*!< Receive Data Byte 2 */ +#define I3C_RDWR_RDB3_Pos (24UL) +#define I3C_RDWR_RDB3_Msk (0xFFUL << I3C_RDWR_RDB3_Pos) /*!< 0xFF000000 */ +#define I3C_RDWR_RDB3 I3C_RDWR_RDB3_Msk /*!< Receive Data Byte 3 */ + +/******************* Bit definition for I3C_TDR register ********************/ +#define I3C_TDR_TDB0_Pos (0UL) +#define I3C_TDR_TDB0_Msk (0xFFUL << I3C_TDR_TDB0_Pos) /*!< 0x000000FF */ +#define I3C_TDR_TDB0 I3C_TDR_TDB0_Msk /*!< Transmit Data Byte */ + +/****************** Bit definition for I3C_TDWR register ********************/ +#define I3C_TDWR_TDBx_Pos (0UL) +#define I3C_TDWR_TDBx_Msk (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_TDWR_TDBx I3C_TDWR_TDBx_Msk /*!< Transmit Data Byte, full double word */ +#define I3C_TDWR_TDB0_Pos (0UL) +#define I3C_TDWR_TDB0_Msk (0xFFUL << I3C_TDWR_TDB0_Pos) /*!< 0x000000FF */ +#define I3C_TDWR_TDB0 I3C_TDWR_TDB0_Msk /*!< Transmit Data Byte 0 */ +#define I3C_TDWR_TDB1_Pos (8UL) +#define I3C_TDWR_TDB1_Msk (0xFFUL << I3C_TDWR_TDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_TDWR_TDB1 I3C_TDWR_TDB1_Msk /*!< Transmit Data Byte 1 */ +#define I3C_TDWR_TDB2_Pos (16UL) +#define I3C_TDWR_TDB2_Msk (0xFFUL << I3C_TDWR_TDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_TDWR_TDB2 I3C_TDWR_TDB2_Msk /*!< Transmit Data Byte 2 */ +#define I3C_TDWR_TDB3_Pos (24UL) +#define I3C_TDWR_TDB3_Msk (0xFFUL << I3C_TDWR_TDB3_Pos) /*!< 0xFF000000 */ +#define I3C_TDWR_TDB3 I3C_TDWR_TDB3_Msk /*!< Transmit Data Byte 3 */ + +/******************* Bit definition for I3C_IBIDR register ******************/ +#define I3C_IBIDR_IBIDBx_Pos (0UL) +#define I3C_IBIDR_IBIDBx_Msk (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_IBIDR_IBIDBx I3C_IBIDR_IBIDBx_Msk /*!< IBI Data Byte, full double word */ +#define I3C_IBIDR_IBIDB0_Pos (0UL) +#define I3C_IBIDR_IBIDB0_Msk (0xFFUL << I3C_IBIDR_IBIDB0_Pos) /*!< 0x000000FF */ +#define I3C_IBIDR_IBIDB0 I3C_IBIDR_IBIDB0_Msk /*!< IBI Data Byte 0 */ +#define I3C_IBIDR_IBIDB1_Pos (8UL) +#define I3C_IBIDR_IBIDB1_Msk (0xFFUL << I3C_IBIDR_IBIDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_IBIDR_IBIDB1 I3C_IBIDR_IBIDB1_Msk /*!< IBI Data Byte 1 */ +#define I3C_IBIDR_IBIDB2_Pos (16UL) +#define I3C_IBIDR_IBIDB2_Msk (0xFFUL << I3C_IBIDR_IBIDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_IBIDR_IBIDB2 I3C_IBIDR_IBIDB2_Msk /*!< IBI Data Byte 2 */ +#define I3C_IBIDR_IBIDB3_Pos (24UL) +#define I3C_IBIDR_IBIDB3_Msk (0xFFUL << I3C_IBIDR_IBIDB3_Pos) /*!< 0xFF000000 */ +#define I3C_IBIDR_IBIDB3 I3C_IBIDR_IBIDB3_Msk /*!< IBI Data Byte 3 */ + +/****************** Bit definition for I3C_TGTTDR register ******************/ +#define I3C_TGTTDR_TGTTDCNT_Pos (0UL) +#define I3C_TGTTDR_TGTTDCNT_Msk (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_TGTTDR_TGTTDCNT I3C_TGTTDR_TGTTDCNT_Msk /*!< Target Transmit Data Counter */ +#define I3C_TGTTDR_PRELOAD_Pos (16UL) +#define I3C_TGTTDR_PRELOAD_Msk (0x1UL << I3C_TGTTDR_PRELOAD_Pos) /*!< 0x00010000 */ +#define I3C_TGTTDR_PRELOAD I3C_TGTTDR_PRELOAD_Msk /*!< Transmit FIFO Preload Enable/Status */ + +/******************* Bit definition for I3C_SR register *********************/ +#define I3C_SR_XDCNT_Pos (0UL) +#define I3C_SR_XDCNT_Msk (0xFFFFUL << I3C_SR_XDCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_SR_XDCNT I3C_SR_XDCNT_Msk /*!< Transfer Data Byte Count status */ +#define I3C_SR_ABT_Pos (17UL) +#define I3C_SR_ABT_Msk (0x1UL << I3C_SR_ABT_Pos) /*!< 0x00020000 */ +#define I3C_SR_ABT I3C_SR_ABT_Msk /*!< Target Abort Indication */ +#define I3C_SR_DIR_Pos (18UL) +#define I3C_SR_DIR_Msk (0x1UL << I3C_SR_DIR_Pos) /*!< 0x00040000 */ +#define I3C_SR_DIR I3C_SR_DIR_Msk /*!< Message Direction */ +#define I3C_SR_MID_Pos (24UL) +#define I3C_SR_MID_Msk (0xFFUL << I3C_SR_MID_Pos) /*!< 0xFF000000 */ +#define I3C_SR_MID I3C_SR_MID_Msk /*!< Message Identifier */ + +/******************* Bit definition for I3C_SER register ********************/ +#define I3C_SER_CODERR_Pos (0UL) +#define I3C_SER_CODERR_Msk (0xFUL << I3C_SER_CODERR_Pos) /*!< 0x0000000F */ +#define I3C_SER_CODERR I3C_SER_CODERR_Msk /*!< Protocol Error Code */ +#define I3C_SER_CODERR_0 (0x1UL << I3C_SER_CODERR_Pos) /*!< 0x00000001 */ +#define I3C_SER_CODERR_1 (0x2UL << I3C_SER_CODERR_Pos) /*!< 0x00000002 */ +#define I3C_SER_CODERR_2 (0x4UL << I3C_SER_CODERR_Pos) /*!< 0x00000004 */ +#define I3C_SER_CODERR_3 (0x8UL << I3C_SER_CODERR_Pos) /*!< 0x00000008 */ +#define I3C_SER_PERR_Pos (4UL) +#define I3C_SER_PERR_Msk (0x1UL << I3C_SER_PERR_Pos) /*!< 0x00000010 */ +#define I3C_SER_PERR I3C_SER_PERR_Msk /*!< Protocol Error */ +#define I3C_SER_STALL_Pos (5UL) +#define I3C_SER_STALL_Msk (0x1UL << I3C_SER_STALL_Pos) /*!< 0x00000020 */ +#define I3C_SER_STALL I3C_SER_STALL_Msk /*!< SCL Stall Error */ +#define I3C_SER_DOVR_Pos (6UL) +#define I3C_SER_DOVR_Msk (0x1UL << I3C_SER_DOVR_Pos) /*!< 0x00000040 */ +#define I3C_SER_DOVR I3C_SER_DOVR_Msk /*!< RX/TX FIFO Overrun */ +#define I3C_SER_COVR_Pos (7UL) +#define I3C_SER_COVR_Msk (0x1UL << I3C_SER_COVR_Pos) /*!< 0x00000080 */ +#define I3C_SER_COVR I3C_SER_COVR_Msk /*!< Status/Control FIFO Overrun */ +#define I3C_SER_ANACK_Pos (8UL) +#define I3C_SER_ANACK_Msk (0x1UL << I3C_SER_ANACK_Pos) /*!< 0x00000100 */ +#define I3C_SER_ANACK I3C_SER_ANACK_Msk /*!< Address Not Acknowledged */ +#define I3C_SER_DNACK_Pos (9UL) +#define I3C_SER_DNACK_Msk (0x1UL << I3C_SER_DNACK_Pos) /*!< 0x00000200 */ +#define I3C_SER_DNACK I3C_SER_DNACK_Msk /*!< Data Not Acknowledged */ +#define I3C_SER_DERR_Pos (10UL) +#define I3C_SER_DERR_Msk (0x1UL << I3C_SER_DERR_Pos) /*!< 0x00000400 */ +#define I3C_SER_DERR I3C_SER_DERR_Msk /*!< Data Error during the controller-role hand-off procedure */ + +/******************* Bit definition for I3C_RMR register ********************/ +#define I3C_RMR_IBIRDCNT_Pos (0UL) +#define I3C_RMR_IBIRDCNT_Msk (0x7UL << I3C_RMR_IBIRDCNT_Pos) /*!< 0x00000007 */ +#define I3C_RMR_IBIRDCNT I3C_RMR_IBIRDCNT_Msk /*!< Data Count when reading IBI data */ +#define I3C_RMR_RCODE_Pos (8UL) +#define I3C_RMR_RCODE_Msk (0xFFUL << I3C_RMR_RCODE_Pos) /*!< 0x0000FF00 */ +#define I3C_RMR_RCODE I3C_RMR_RCODE_Msk /*!< CCC code of received command */ +#define I3C_RMR_RADD_Pos (17UL) +#define I3C_RMR_RADD_Msk (0x7FUL << I3C_RMR_RADD_Pos) /*!< 0x00FE0000 */ +#define I3C_RMR_RADD I3C_RMR_RADD_Msk /*!< Target Address Received during accepted IBI or Controller-role request */ + +/******************* Bit definition for I3C_EVR register ********************/ +#define I3C_EVR_CFEF_Pos (0UL) +#define I3C_EVR_CFEF_Msk (0x1UL << I3C_EVR_CFEF_Pos) /*!< 0x00000001 */ +#define I3C_EVR_CFEF I3C_EVR_CFEF_Msk /*!< Control FIFO Empty Flag */ +#define I3C_EVR_TXFEF_Pos (1UL) +#define I3C_EVR_TXFEF_Msk (0x1UL << I3C_EVR_TXFEF_Pos) /*!< 0x00000002 */ +#define I3C_EVR_TXFEF I3C_EVR_TXFEF_Msk /*!< TX FIFO Empty Flag */ +#define I3C_EVR_CFNFF_Pos (2UL) +#define I3C_EVR_CFNFF_Msk (0x1UL << I3C_EVR_CFNFF_Pos) /*!< 0x00000004 */ +#define I3C_EVR_CFNFF I3C_EVR_CFNFF_Msk /*!< Control FIFO Not Full Flag */ +#define I3C_EVR_SFNEF_Pos (3UL) +#define I3C_EVR_SFNEF_Msk (0x1UL << I3C_EVR_SFNEF_Pos) /*!< 0x00000008 */ +#define I3C_EVR_SFNEF I3C_EVR_SFNEF_Msk /*!< Status FIFO Not Empty Flag */ +#define I3C_EVR_TXFNFF_Pos (4UL) +#define I3C_EVR_TXFNFF_Msk (0x1UL << I3C_EVR_TXFNFF_Pos) /*!< 0x00000010 */ +#define I3C_EVR_TXFNFF I3C_EVR_TXFNFF_Msk /*!< TX FIFO Not Full Flag */ +#define I3C_EVR_RXFNEF_Pos (5UL) +#define I3C_EVR_RXFNEF_Msk (0x1UL << I3C_EVR_RXFNEF_Pos) /*!< 0x00000020 */ +#define I3C_EVR_RXFNEF I3C_EVR_RXFNEF_Msk /*!< RX FIFO Not Empty Flag */ +#define I3C_EVR_TXLASTF_Pos (6UL) +#define I3C_EVR_TXLASTF_Msk (0x1UL << I3C_EVR_TXLASTF_Pos) /*!< 0x00000040 */ +#define I3C_EVR_TXLASTF I3C_EVR_TXLASTF_Msk /*!< Last TX byte available in FIFO */ +#define I3C_EVR_RXLASTF_Pos (7UL) +#define I3C_EVR_RXLASTF_Msk (0x1UL << I3C_EVR_RXLASTF_Pos) /*!< 0x00000080 */ +#define I3C_EVR_RXLASTF I3C_EVR_RXLASTF_Msk /*!< Last RX byte read from FIFO */ +#define I3C_EVR_FCF_Pos (9UL) +#define I3C_EVR_FCF_Msk (0x1UL << I3C_EVR_FCF_Pos) /*!< 0x00000200 */ +#define I3C_EVR_FCF I3C_EVR_FCF_Msk /*!< Frame Complete Flag */ +#define I3C_EVR_RXTGTENDF_Pos (10UL) +#define I3C_EVR_RXTGTENDF_Msk (0x1UL << I3C_EVR_RXTGTENDF_Pos) /*!< 0x00000400 */ +#define I3C_EVR_RXTGTENDF I3C_EVR_RXTGTENDF_Msk /*!< Reception Target End Flag */ +#define I3C_EVR_ERRF_Pos (11UL) +#define I3C_EVR_ERRF_Msk (0x1UL << I3C_EVR_ERRF_Pos) /*!< 0x00000800 */ +#define I3C_EVR_ERRF I3C_EVR_ERRF_Msk /*!< Error Flag */ +#define I3C_EVR_IBIF_Pos (15UL) +#define I3C_EVR_IBIF_Msk (0x1UL << I3C_EVR_IBIF_Pos) /*!< 0x00008000 */ +#define I3C_EVR_IBIF I3C_EVR_IBIF_Msk /*!< IBI Flag */ +#define I3C_EVR_IBIENDF_Pos (16UL) +#define I3C_EVR_IBIENDF_Msk (0x1UL << I3C_EVR_IBIENDF_Pos) /*!< 0x00010000 */ +#define I3C_EVR_IBIENDF I3C_EVR_IBIENDF_Msk /*!< IBI End Flag */ +#define I3C_EVR_CRF_Pos (17UL) +#define I3C_EVR_CRF_Msk (0x1UL << I3C_EVR_CRF_Pos) /*!< 0x00020000 */ +#define I3C_EVR_CRF I3C_EVR_CRF_Msk /*!< Controller-role Request Flag */ +#define I3C_EVR_CRUPDF_Pos (18UL) +#define I3C_EVR_CRUPDF_Msk (0x1UL << I3C_EVR_CRUPDF_Pos) /*!< 0x00040000 */ +#define I3C_EVR_CRUPDF I3C_EVR_CRUPDF_Msk /*!< Controller-role Update Flag */ +#define I3C_EVR_HJF_Pos (19UL) +#define I3C_EVR_HJF_Msk (0x1UL << I3C_EVR_HJF_Pos) /*!< 0x00080000 */ +#define I3C_EVR_HJF I3C_EVR_HJF_Msk /*!< Hot Join Flag */ +#define I3C_EVR_WKPF_Pos (21UL) +#define I3C_EVR_WKPF_Msk (0x1UL << I3C_EVR_WKPF_Pos) /*!< 0x00200000 */ +#define I3C_EVR_WKPF I3C_EVR_WKPF_Msk /*!< Wake Up Flag */ +#define I3C_EVR_GETF_Pos (22UL) +#define I3C_EVR_GETF_Msk (0x1UL << I3C_EVR_GETF_Pos) /*!< 0x00400000 */ +#define I3C_EVR_GETF I3C_EVR_GETF_Msk /*!< Get type CCC received Flag */ +#define I3C_EVR_STAF_Pos (23UL) +#define I3C_EVR_STAF_Msk (0x1UL << I3C_EVR_STAF_Pos) /*!< 0x00800000 */ +#define I3C_EVR_STAF I3C_EVR_STAF_Msk /*!< Get Status Flag */ +#define I3C_EVR_DAUPDF_Pos (24UL) +#define I3C_EVR_DAUPDF_Msk (0x1UL << I3C_EVR_DAUPDF_Pos) /*!< 0x01000000 */ +#define I3C_EVR_DAUPDF I3C_EVR_DAUPDF_Msk /*!< Dynamic Address Update Flag */ +#define I3C_EVR_MWLUPDF_Pos (25UL) +#define I3C_EVR_MWLUPDF_Msk (0x1UL << I3C_EVR_MWLUPDF_Pos) /*!< 0x02000000 */ +#define I3C_EVR_MWLUPDF I3C_EVR_MWLUPDF_Msk /*!< Max Write Length Update Flag */ +#define I3C_EVR_MRLUPDF_Pos (26UL) +#define I3C_EVR_MRLUPDF_Msk (0x1UL << I3C_EVR_MRLUPDF_Pos) /*!< 0x04000000 */ +#define I3C_EVR_MRLUPDF I3C_EVR_MRLUPDF_Msk /*!< Max Read Length Update Flag */ +#define I3C_EVR_RSTF_Pos (27UL) +#define I3C_EVR_RSTF_Msk (0x1UL << I3C_EVR_RSTF_Pos) /*!< 0x08000000 */ +#define I3C_EVR_RSTF I3C_EVR_RSTF_Msk /*!< Reset Flag, due to Reset pattern received */ +#define I3C_EVR_ASUPDF_Pos (28UL) +#define I3C_EVR_ASUPDF_Msk (0x1UL << I3C_EVR_ASUPDF_Pos) /*!< 0x10000000 */ +#define I3C_EVR_ASUPDF I3C_EVR_ASUPDF_Msk /*!< Activity State Flag */ +#define I3C_EVR_INTUPDF_Pos (29UL) +#define I3C_EVR_INTUPDF_Msk (0x1UL << I3C_EVR_INTUPDF_Pos) /*!< 0x20000000 */ +#define I3C_EVR_INTUPDF I3C_EVR_INTUPDF_Msk /*!< Interrupt Update Flag */ +#define I3C_EVR_DEFF_Pos (30UL) +#define I3C_EVR_DEFF_Msk (0x1UL << I3C_EVR_DEFF_Pos) /*!< 0x40000000 */ +#define I3C_EVR_DEFF I3C_EVR_DEFF_Msk /*!< List of Targets Command Received Flag */ +#define I3C_EVR_GRPF_Pos (31UL) +#define I3C_EVR_GRPF_Msk (0x1UL << I3C_EVR_GRPF_Pos) /*!< 0x80000000 */ +#define I3C_EVR_GRPF I3C_EVR_GRPF_Msk /*!< List of Group Addresses Command Received Flag */ + +/******************* Bit definition for I3C_IER register ********************/ +#define I3C_IER_CFNFIE_Pos (2UL) +#define I3C_IER_CFNFIE_Msk (0x1UL << I3C_IER_CFNFIE_Pos) /*!< 0x00000004 */ +#define I3C_IER_CFNFIE I3C_IER_CFNFIE_Msk /*!< Control FIFO Not Full Interrupt Enable */ +#define I3C_IER_SFNEIE_Pos (3UL) +#define I3C_IER_SFNEIE_Msk (0x1UL << I3C_IER_SFNEIE_Pos) /*!< 0x00000008 */ +#define I3C_IER_SFNEIE I3C_IER_SFNEIE_Msk /*!< Status FIFO Not Empty Interrupt Enable */ +#define I3C_IER_TXFNFIE_Pos (4UL) +#define I3C_IER_TXFNFIE_Msk (0x1UL << I3C_IER_TXFNFIE_Pos) /*!< 0x00000010 */ +#define I3C_IER_TXFNFIE I3C_IER_TXFNFIE_Msk /*!< TX FIFO Not Full Interrupt Enable */ +#define I3C_IER_RXFNEIE_Pos (5UL) +#define I3C_IER_RXFNEIE_Msk (0x1UL << I3C_IER_RXFNEIE_Pos) /*!< 0x00000020 */ +#define I3C_IER_RXFNEIE I3C_IER_RXFNEIE_Msk /*!< RX FIFO Not Empty Interrupt Enable */ +#define I3C_IER_FCIE_Pos (9UL) +#define I3C_IER_FCIE_Msk (0x1UL << I3C_IER_FCIE_Pos) /*!< 0x00000200 */ +#define I3C_IER_FCIE I3C_IER_FCIE_Msk /*!< Frame Complete Interrupt Enable */ +#define I3C_IER_RXTGTENDIE_Pos (10UL) +#define I3C_IER_RXTGTENDIE_Msk (0x1UL << I3C_IER_RXTGTENDIE_Pos) /*!< 0x00000400 */ +#define I3C_IER_RXTGTENDIE I3C_IER_RXTGTENDIE_Msk /*!< Reception Target End Interrupt Enable */ +#define I3C_IER_ERRIE_Pos (11UL) +#define I3C_IER_ERRIE_Msk (0x1UL << I3C_IER_ERRIE_Pos) /*!< 0x00000800 */ +#define I3C_IER_ERRIE I3C_IER_ERRIE_Msk /*!< Error Interrupt Enable */ +#define I3C_IER_IBIIE_Pos (15UL) +#define I3C_IER_IBIIE_Msk (0x1UL << I3C_IER_IBIIE_Pos) /*!< 0x00008000 */ +#define I3C_IER_IBIIE I3C_IER_IBIIE_Msk /*!< IBI Interrupt Enable */ +#define I3C_IER_IBIENDIE_Pos (16UL) +#define I3C_IER_IBIENDIE_Msk (0x1UL << I3C_IER_IBIENDIE_Pos) /*!< 0x00010000 */ +#define I3C_IER_IBIENDIE I3C_IER_IBIENDIE_Msk /*!< IBI End Interrupt Enable */ +#define I3C_IER_CRIE_Pos (17UL) +#define I3C_IER_CRIE_Msk (0x1UL << I3C_IER_CRIE_Pos) /*!< 0x00020000 */ +#define I3C_IER_CRIE I3C_IER_CRIE_Msk /*!< Controller-role Interrupt Enable */ +#define I3C_IER_CRUPDIE_Pos (18UL) +#define I3C_IER_CRUPDIE_Msk (0x1UL << I3C_IER_CRUPDIE_Pos) /*!< 0x00040000 */ +#define I3C_IER_CRUPDIE I3C_IER_CRUPDIE_Msk /*!< Controller-role Update Interrupt Enable */ +#define I3C_IER_HJIE_Pos (19UL) +#define I3C_IER_HJIE_Msk (0x1UL << I3C_IER_HJIE_Pos) /*!< 0x00080000 */ +#define I3C_IER_HJIE I3C_IER_HJIE_Msk /*!< Hot Join Interrupt Enable */ +#define I3C_IER_WKPIE_Pos (21UL) +#define I3C_IER_WKPIE_Msk (0x1UL << I3C_IER_WKPIE_Pos) /*!< 0x00200000 */ +#define I3C_IER_WKPIE I3C_IER_WKPIE_Msk /*!< Wake Up Interrupt Enable */ +#define I3C_IER_GETIE_Pos (22UL) +#define I3C_IER_GETIE_Msk (0x1UL << I3C_IER_GETIE_Pos) /*!< 0x00400000 */ +#define I3C_IER_GETIE I3C_IER_GETIE_Msk /*!< Get type CCC received Interrupt Enable */ +#define I3C_IER_STAIE_Pos (23UL) +#define I3C_IER_STAIE_Msk (0x1UL << I3C_IER_STAIE_Pos) /*!< 0x00800000 */ +#define I3C_IER_STAIE I3C_IER_STAIE_Msk /*!< Get Status Interrupt Enable */ +#define I3C_IER_DAUPDIE_Pos (24UL) +#define I3C_IER_DAUPDIE_Msk (0x1UL << I3C_IER_DAUPDIE_Pos) /*!< 0x01000000 */ +#define I3C_IER_DAUPDIE I3C_IER_DAUPDIE_Msk /*!< Dynamic Address Update Interrupt Enable */ +#define I3C_IER_MWLUPDIE_Pos (25UL) +#define I3C_IER_MWLUPDIE_Msk (0x1UL << I3C_IER_MWLUPDIE_Pos) /*!< 0x02000000 */ +#define I3C_IER_MWLUPDIE I3C_IER_MWLUPDIE_Msk /*!< Max Write Length Update Interrupt Enable */ +#define I3C_IER_MRLUPDIE_Pos (26UL) +#define I3C_IER_MRLUPDIE_Msk (0x1UL << I3C_IER_MRLUPDIE_Pos) /*!< 0x04000000 */ +#define I3C_IER_MRLUPDIE I3C_IER_MRLUPDIE_Msk /*!< Max Read Length Update Interrupt Enable */ +#define I3C_IER_RSTIE_Pos (27UL) +#define I3C_IER_RSTIE_Msk (0x1UL << I3C_IER_RSTIE_Pos) /*!< 0x08000000 */ +#define I3C_IER_RSTIE I3C_IER_RSTIE_Msk /*!< Reset Interrupt Enabled, due to Reset pattern received */ +#define I3C_IER_ASUPDIE_Pos (28UL) +#define I3C_IER_ASUPDIE_Msk (0x1UL << I3C_IER_ASUPDIE_Pos) /*!< 0x10000000 */ +#define I3C_IER_ASUPDIE I3C_IER_ASUPDIE_Msk /*!< Activity State Interrupt Enable */ +#define I3C_IER_INTUPDIE_Pos (29UL) +#define I3C_IER_INTUPDIE_Msk (0x1UL << I3C_IER_INTUPDIE_Pos) /*!< 0x20000000 */ +#define I3C_IER_INTUPDIE I3C_IER_INTUPDIE_Msk /*!< Interrupt Update Interrupt Enable */ +#define I3C_IER_DEFIE_Pos (30UL) +#define I3C_IER_DEFIE_Msk (0x1UL << I3C_IER_DEFIE_Pos) /*!< 0x40000000 */ +#define I3C_IER_DEFIE I3C_IER_DEFIE_Msk /*!< List of Targets Command Received Interrupt Enable */ +#define I3C_IER_GRPIE_Pos (31UL) +#define I3C_IER_GRPIE_Msk (0x1UL << I3C_IER_GRPIE_Pos) /*!< 0x80000000 */ +#define I3C_IER_GRPIE I3C_IER_GRPIE_Msk /*!< List of Group Addresses Command Received Interrupt Enable */ + +/******************* Bit definition for I3C_CEVR register *******************/ +#define I3C_CEVR_CFCF_Pos (9UL) +#define I3C_CEVR_CFCF_Msk (0x1UL << I3C_CEVR_CFCF_Pos) /*!< 0x00000200 */ +#define I3C_CEVR_CFCF I3C_CEVR_CFCF_Msk /*!< Frame Complete Clear Flag */ +#define I3C_CEVR_CRXTGTENDF_Pos (10UL) +#define I3C_CEVR_CRXTGTENDF_Msk (0x1UL << I3C_CEVR_CRXTGTENDF_Pos) /*!< 0x00000400 */ +#define I3C_CEVR_CRXTGTENDF I3C_CEVR_CRXTGTENDF_Msk /*!< Reception Target End Clear Flag */ +#define I3C_CEVR_CERRF_Pos (11UL) +#define I3C_CEVR_CERRF_Msk (0x1UL << I3C_CEVR_CERRF_Pos) /*!< 0x00000800 */ +#define I3C_CEVR_CERRF I3C_CEVR_CERRF_Msk /*!< Error Clear Flag */ +#define I3C_CEVR_CIBIF_Pos (15UL) +#define I3C_CEVR_CIBIF_Msk (0x1UL << I3C_CEVR_CIBIF_Pos) /*!< 0x00008000 */ +#define I3C_CEVR_CIBIF I3C_CEVR_CIBIF_Msk /*!< IBI Clear Flag */ +#define I3C_CEVR_CIBIENDF_Pos (16UL) +#define I3C_CEVR_CIBIENDF_Msk (0x1UL << I3C_CEVR_CIBIENDF_Pos) /*!< 0x00010000 */ +#define I3C_CEVR_CIBIENDF I3C_CEVR_CIBIENDF_Msk /*!< IBI End Clear Flag */ +#define I3C_CEVR_CCRF_Pos (17UL) +#define I3C_CEVR_CCRF_Msk (0x1UL << I3C_CEVR_CCRF_Pos) /*!< 0x00020000 */ +#define I3C_CEVR_CCRF I3C_CEVR_CCRF_Msk /*!< Controller-role Clear Flag */ +#define I3C_CEVR_CCRUPDF_Pos (18UL) +#define I3C_CEVR_CCRUPDF_Msk (0x1UL << I3C_CEVR_CCRUPDF_Pos) /*!< 0x00040000 */ +#define I3C_CEVR_CCRUPDF I3C_CEVR_CCRUPDF_Msk /*!< Controller-role Update Clear Flag */ +#define I3C_CEVR_CHJF_Pos (19UL) +#define I3C_CEVR_CHJF_Msk (0x1UL << I3C_CEVR_CHJF_Pos) /*!< 0x00080000 */ +#define I3C_CEVR_CHJF I3C_CEVR_CHJF_Msk /*!< Hot Join Clear Flag */ +#define I3C_CEVR_CWKPF_Pos (21UL) +#define I3C_CEVR_CWKPF_Msk (0x1UL << I3C_CEVR_CWKPF_Pos) /*!< 0x00200000 */ +#define I3C_CEVR_CWKPF I3C_CEVR_CWKPF_Msk /*!< Wake Up Clear Flag */ +#define I3C_CEVR_CGETF_Pos (22UL) +#define I3C_CEVR_CGETF_Msk (0x1UL << I3C_CEVR_CGETF_Pos) /*!< 0x00400000 */ +#define I3C_CEVR_CGETF I3C_CEVR_CGETF_Msk /*!< Get type CCC received Clear Flag */ +#define I3C_CEVR_CSTAF_Pos (23UL) +#define I3C_CEVR_CSTAF_Msk (0x1UL << I3C_CEVR_CSTAF_Pos) /*!< 0x00800000 */ +#define I3C_CEVR_CSTAF I3C_CEVR_CSTAF_Msk /*!< Get Status Clear Flag */ +#define I3C_CEVR_CDAUPDF_Pos (24UL) +#define I3C_CEVR_CDAUPDF_Msk (0x1UL << I3C_CEVR_CDAUPDF_Pos) /*!< 0x01000000 */ +#define I3C_CEVR_CDAUPDF I3C_CEVR_CDAUPDF_Msk /*!< Dynamic Address Update Clear Flag */ +#define I3C_CEVR_CMWLUPDF_Pos (25UL) +#define I3C_CEVR_CMWLUPDF_Msk (0x1UL << I3C_CEVR_CMWLUPDF_Pos) /*!< 0x02000000 */ +#define I3C_CEVR_CMWLUPDF I3C_CEVR_CMWLUPDF_Msk /*!< Max Write Length Update Clear Flag */ +#define I3C_CEVR_CMRLUPDF_Pos (26UL) +#define I3C_CEVR_CMRLUPDF_Msk (0x1UL << I3C_CEVR_CMRLUPDF_Pos) /*!< 0x04000000 */ +#define I3C_CEVR_CMRLUPDF I3C_CEVR_CMRLUPDF_Msk /*!< Max Read Length Update Clear Flag */ +#define I3C_CEVR_CRSTF_Pos (27UL) +#define I3C_CEVR_CRSTF_Msk (0x1UL << I3C_CEVR_CRSTF_Pos) /*!< 0x08000000 */ +#define I3C_CEVR_CRSTF I3C_CEVR_CRSTF_Msk /*!< Reset Flag, due to Reset pattern received */ +#define I3C_CEVR_CASUPDF_Pos (28UL) +#define I3C_CEVR_CASUPDF_Msk (0x1UL << I3C_CEVR_CASUPDF_Pos) /*!< 0x10000000 */ +#define I3C_CEVR_CASUPDF I3C_CEVR_CASUPDF_Msk /*!< Activity State Clear Flag */ +#define I3C_CEVR_CINTUPDF_Pos (29UL) +#define I3C_CEVR_CINTUPDF_Msk (0x1UL << I3C_CEVR_CINTUPDF_Pos) /*!< 0x20000000 */ +#define I3C_CEVR_CINTUPDF I3C_CEVR_CINTUPDF_Msk /*!< Interrupt Update Clear Flag */ +#define I3C_CEVR_CDEFF_Pos (30UL) +#define I3C_CEVR_CDEFF_Msk (0x1UL << I3C_CEVR_CDEFF_Pos) /*!< 0x40000000 */ +#define I3C_CEVR_CDEFF I3C_CEVR_CDEFF_Msk /*!< List of Targets Command Received Clear Flag */ +#define I3C_CEVR_CGRPF_Pos (31UL) +#define I3C_CEVR_CGRPF_Msk (0x1UL << I3C_CEVR_CGRPF_Pos) /*!< 0x80000000 */ +#define I3C_CEVR_CGRPF I3C_CEVR_CGRPF_Msk /*!< List of Group Addresses Command Received Clear Flag */ + +/******************* Bit definition for I3C_MISR register *******************/ +#define I3C_MISR_CFNFMIS_Pos (2UL) +#define I3C_MISR_CFNFMIS_Msk (0x1UL << I3C_MISR_CFNFMIS_Pos) /*!< 0x00000004 */ +#define I3C_MISR_CFNFMIS I3C_MISR_CFNFMIS_Msk /*!< Control FIFO Not Full Mask Interrupt Status */ +#define I3C_MISR_SFNEMIS_Pos (3UL) +#define I3C_MISR_SFNEMIS_Msk (0x1UL << I3C_MISR_SFNEMIS_Pos) /*!< 0x00000008 */ +#define I3C_MISR_SFNEMIS I3C_MISR_SFNEMIS_Msk /*!< Status FIFO Not Empty Mask Interrupt Status */ +#define I3C_MISR_TXFNFMIS_Pos (4UL) +#define I3C_MISR_TXFNFMIS_Msk (0x1UL << I3C_MISR_TXFNFMIS_Pos) /*!< 0x00000010 */ +#define I3C_MISR_TXFNFMIS I3C_MISR_TXFNFMIS_Msk /*!< TX FIFO Not Full Mask Interrupt Status */ +#define I3C_MISR_RXFNEMIS_Pos (5UL) +#define I3C_MISR_RXFNEMIS_Msk (0x1UL << I3C_MISR_RXFNEMIS_Pos) /*!< 0x00000020 */ +#define I3C_MISR_RXFNEMIS I3C_MISR_RXFNEMIS_Msk /*!< RX FIFO Not Empty Mask Interrupt Status */ +#define I3C_MISR_FCMIS_Pos (9UL) +#define I3C_MISR_FCMIS_Msk (0x1UL << I3C_MISR_FCMIS_Pos) /*!< 0x00000200 */ +#define I3C_MISR_FCMIS I3C_MISR_FCMIS_Msk /*!< Frame Complete Mask Interrupt Status */ +#define I3C_MISR_RXTGTENDMIS_Pos (10UL) +#define I3C_MISR_RXTGTENDMIS_Msk (0x1UL << I3C_MISR_RXTGTENDMIS_Pos) /*!< 0x00000400 */ +#define I3C_MISR_RXTGTENDMIS I3C_MISR_RXTGTENDMIS_Msk /*!< Reception Target End Mask Interrupt Status */ +#define I3C_MISR_ERRMIS_Pos (11UL) +#define I3C_MISR_ERRMIS_Msk (0x1UL << I3C_MISR_ERRMIS_Pos) /*!< 0x00000800 */ +#define I3C_MISR_ERRMIS I3C_MISR_ERRMIS_Msk /*!< Error Mask Interrupt Status */ +#define I3C_MISR_IBIMIS_Pos (15UL) +#define I3C_MISR_IBIMIS_Msk (0x1UL << I3C_MISR_IBIMIS_Pos) /*!< 0x00008000 */ +#define I3C_MISR_IBIMIS I3C_MISR_IBIMIS_Msk /*!< IBI Mask Interrupt Status */ +#define I3C_MISR_IBIENDMIS_Pos (16UL) +#define I3C_MISR_IBIENDMIS_Msk (0x1UL << I3C_MISR_IBIENDMIS_Pos) /*!< 0x00010000 */ +#define I3C_MISR_IBIENDMIS I3C_MISR_IBIENDMIS_Msk /*!< IBI End Mask Interrupt Status */ +#define I3C_MISR_CRMIS_Pos (17UL) +#define I3C_MISR_CRMIS_Msk (0x1UL << I3C_MISR_CRMIS_Pos) /*!< 0x00020000 */ +#define I3C_MISR_CRMIS I3C_MISR_CRMIS_Msk /*!< Controller-role Mask Interrupt Status */ +#define I3C_MISR_CRUPDMIS_Pos (18UL) +#define I3C_MISR_CRUPDMIS_Msk (0x1UL << I3C_MISR_CRUPDMIS_Pos) /*!< 0x00040000 */ +#define I3C_MISR_CRUPDMIS I3C_MISR_CRUPDMIS_Msk /*!< Controller-role Update Mask Interrupt Status */ +#define I3C_MISR_HJMIS_Pos (19UL) +#define I3C_MISR_HJMIS_Msk (0x1UL << I3C_MISR_HJMIS_Pos) /*!< 0x00080000 */ +#define I3C_MISR_HJMIS I3C_MISR_HJMIS_Msk /*!< Hot Join Mask Interrupt Status */ +#define I3C_MISR_WKPMIS_Pos (21UL) +#define I3C_MISR_WKPMIS_Msk (0x1UL << I3C_MISR_WKPMIS_Pos) /*!< 0x00200000 */ +#define I3C_MISR_WKPMIS I3C_MISR_WKPMIS_Msk /*!< Wake Up Mask Interrupt Status */ +#define I3C_MISR_GETMIS_Pos (22UL) +#define I3C_MISR_GETMIS_Msk (0x1UL << I3C_MISR_GETMIS_Pos) /*!< 0x00400000 */ +#define I3C_MISR_GETMIS I3C_MISR_GETMIS_Msk /*!< Get type CCC received Mask Interrupt Status */ +#define I3C_MISR_STAMIS_Pos (23UL) +#define I3C_MISR_STAMIS_Msk (0x1UL << I3C_MISR_STAMIS_Pos) /*!< 0x00800000 */ +#define I3C_MISR_STAMIS I3C_MISR_STAMIS_Msk /*!< Get Status Mask Interrupt Status */ +#define I3C_MISR_DAUPDMIS_Pos (24UL) +#define I3C_MISR_DAUPDMIS_Msk (0x1UL << I3C_MISR_DAUPDMIS_Pos) /*!< 0x01000000 */ +#define I3C_MISR_DAUPDMIS I3C_MISR_DAUPDMIS_Msk /*!< Dynamic Address Update Mask Interrupt Status */ +#define I3C_MISR_MWLUPDMIS_Pos (25UL) +#define I3C_MISR_MWLUPDMIS_Msk (0x1UL << I3C_MISR_MWLUPDMIS_Pos) /*!< 0x02000000 */ +#define I3C_MISR_MWLUPDMIS I3C_MISR_MWLUPDMIS_Msk /*!< Max Write Length Update Mask Interrupt Status */ +#define I3C_MISR_MRLUPDMIS_Pos (26UL) +#define I3C_MISR_MRLUPDMIS_Msk (0x1UL << I3C_MISR_MRLUPDMIS_Pos) /*!< 0x04000000 */ +#define I3C_MISR_MRLUPDMIS I3C_MISR_MRLUPDMIS_Msk /*!< Max Read Length Update Mask Interrupt Status */ +#define I3C_MISR_RSTMIS_Pos (27UL) +#define I3C_MISR_RSTMIS_Msk (0x1UL << I3C_MISR_RSTMIS_Pos) /*!< 0x08000000 */ +#define I3C_MISR_RSTMIS I3C_MISR_RSTMIS_Msk /*!< Reset Mask Interrupt Status, due to Reset pattern received */ +#define I3C_MISR_ASUPDMIS_Pos (28UL) +#define I3C_MISR_ASUPDMIS_Msk (0x1UL << I3C_MISR_ASUPDMIS_Pos) /*!< 0x10000000 */ +#define I3C_MISR_ASUPDMIS I3C_MISR_ASUPDMIS_Msk /*!< Activity State Mask Interrupt Status */ +#define I3C_MISR_INTUPDMIS_Pos (29UL) +#define I3C_MISR_INTUPDMIS_Msk (0x1UL << I3C_MISR_INTUPDMIS_Pos) /*!< 0x20000000 */ +#define I3C_MISR_INTUPDMIS I3C_MISR_INTUPDMIS_Msk /*!< Interrupt Update Mask Interrupt Status */ +#define I3C_MISR_DEFMIS_Pos (30UL) +#define I3C_MISR_DEFMIS_Msk (0x1UL << I3C_MISR_DEFMIS_Pos) /*!< 0x40000000 */ +#define I3C_MISR_DEFMIS I3C_MISR_DEFMIS_Msk /*!< List of Targets Command Received Mask Interrupt Status */ +#define I3C_MISR_GRPMIS_Pos (31UL) +#define I3C_MISR_GRPMIS_Msk (0x1UL << I3C_MISR_GRPMIS_Pos) /*!< 0x80000000 */ +#define I3C_MISR_GRPMIS I3C_MISR_GRPMIS_Msk /*!< List of Group Addresses Command Received Mask Interrupt Status */ + +/****************** Bit definition for I3C_DEVR0 register *******************/ +#define I3C_DEVR0_DAVAL_Pos (0UL) +#define I3C_DEVR0_DAVAL_Msk (0x1UL << I3C_DEVR0_DAVAL_Pos) /*!< 0x00000001 */ +#define I3C_DEVR0_DAVAL I3C_DEVR0_DAVAL_Msk /*!< Dynamic Address Validity */ +#define I3C_DEVR0_DA_Pos (1UL) +#define I3C_DEVR0_DA_Msk (0x7FUL << I3C_DEVR0_DA_Pos) /*!< 0x000000FE */ +#define I3C_DEVR0_DA I3C_DEVR0_DA_Msk /*!< Own Target Device Address */ +#define I3C_DEVR0_IBIEN_Pos (16UL) +#define I3C_DEVR0_IBIEN_Msk (0x1UL << I3C_DEVR0_IBIEN_Pos) /*!< 0x00010000 */ +#define I3C_DEVR0_IBIEN I3C_DEVR0_IBIEN_Msk /*!< IBI Enable */ +#define I3C_DEVR0_CREN_Pos (17UL) +#define I3C_DEVR0_CREN_Msk (0x1UL << I3C_DEVR0_CREN_Pos) /*!< 0x00020000 */ +#define I3C_DEVR0_CREN I3C_DEVR0_CREN_Msk /*!< Controller-role Enable */ +#define I3C_DEVR0_HJEN_Pos (19UL) +#define I3C_DEVR0_HJEN_Msk (0x1UL << I3C_DEVR0_HJEN_Pos) /*!< 0x00080000 */ +#define I3C_DEVR0_HJEN I3C_DEVR0_HJEN_Msk /*!< Hot Join Enable */ +#define I3C_DEVR0_AS_Pos (20UL) +#define I3C_DEVR0_AS_Msk (0x3UL << I3C_DEVR0_AS_Pos) /*!< 0x00300000 */ +#define I3C_DEVR0_AS I3C_DEVR0_AS_Msk /*!< Activity State value update after ENTAx received */ +#define I3C_DEVR0_AS_0 (0x1UL << I3C_DEVR0_AS_Pos) /*!< 0x00100000 */ +#define I3C_DEVR0_AS_1 (0x2UL << I3C_DEVR0_AS_Pos) /*!< 0x00200000 */ +#define I3C_DEVR0_RSTACT_Pos (22UL) +#define I3C_DEVR0_RSTACT_Msk (0x3UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00C000000 */ +#define I3C_DEVR0_RSTACT I3C_DEVR0_RSTACT_Msk /*!< Reset Action value update after RSTACT received */ +#define I3C_DEVR0_RSTACT_0 (0x1UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00400000 */ +#define I3C_DEVR0_RSTACT_1 (0x2UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00800000 */ +#define I3C_DEVR0_RSTVAL_Pos (24UL) +#define I3C_DEVR0_RSTVAL_Msk (0x1UL << I3C_DEVR0_RSTVAL_Pos) /*!< 0x01000000 */ +#define I3C_DEVR0_RSTVAL I3C_DEVR0_RSTVAL_Msk /*!< Reset Action Valid */ + +/****************** Bit definition for I3C_DEVRX register *******************/ +#define I3C_DEVRX_DA_Pos (1UL) +#define I3C_DEVRX_DA_Msk (0x7FUL << I3C_DEVRX_DA_Pos) /*!< 0x000000FE */ +#define I3C_DEVRX_DA I3C_DEVRX_DA_Msk /*!< Dynamic Address Target x */ +#define I3C_DEVRX_IBIACK_Pos (16UL) +#define I3C_DEVRX_IBIACK_Msk (0x1UL << I3C_DEVRX_IBIACK_Pos) /*!< 0x00010000 */ +#define I3C_DEVRX_IBIACK I3C_DEVRX_IBIACK_Msk /*!< IBI Acknowledge from Target x */ +#define I3C_DEVRX_CRACK_Pos (17UL) +#define I3C_DEVRX_CRACK_Msk (0x1UL << I3C_DEVRX_CRACK_Pos) /*!< 0x00020000 */ +#define I3C_DEVRX_CRACK I3C_DEVRX_CRACK_Msk /*!< Controller-role Acknowledge from Target x */ +#define I3C_DEVRX_IBIDEN_Pos (18UL) +#define I3C_DEVRX_IBIDEN_Msk (0x1UL << I3C_DEVRX_IBIDEN_Pos) /*!< 0x00040000 */ +#define I3C_DEVRX_IBIDEN I3C_DEVRX_IBIDEN_Msk /*!< IBI Additional Data Enable */ +#define I3C_DEVRX_SUSP_Pos (19UL) +#define I3C_DEVRX_SUSP_Msk (0x1UL << I3C_DEVRX_SUSP_Pos) /*!< 0x00080000 */ +#define I3C_DEVRX_SUSP I3C_DEVRX_SUSP_Msk /*!< Suspended Transfer */ +#define I3C_DEVRX_DIS_Pos (31UL) +#define I3C_DEVRX_DIS_Msk (0x1UL << I3C_DEVRX_DIS_Pos) /*!< 0x80000000 */ +#define I3C_DEVRX_DIS I3C_DEVRX_DIS_Msk /*!< Disable Register access */ + +/****************** Bit definition for I3C_MAXRLR register ******************/ +#define I3C_MAXRLR_MRL_Pos (0UL) +#define I3C_MAXRLR_MRL_Msk (0xFFFFUL << I3C_MAXRLR_MRL_Pos) /*!< 0x0000FFFF */ +#define I3C_MAXRLR_MRL I3C_MAXRLR_MRL_Msk /*!< Maximum Read Length */ +#define I3C_MAXRLR_IBIP_Pos (16UL) +#define I3C_MAXRLR_IBIP_Msk (0x7UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00070000 */ +#define I3C_MAXRLR_IBIP I3C_MAXRLR_IBIP_Msk /*!< IBI Payload size */ +#define I3C_MAXRLR_IBIP_0 (0x1UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00010000 */ +#define I3C_MAXRLR_IBIP_1 (0x2UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00020000 */ +#define I3C_MAXRLR_IBIP_2 (0x4UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00040000 */ + +/****************** Bit definition for I3C_MAXWLR register ******************/ +#define I3C_MAXWLR_MWL_Pos (0UL) +#define I3C_MAXWLR_MWL_Msk (0xFFFFUL << I3C_MAXWLR_MWL_Pos) /*!< 0x0000FFFF */ +#define I3C_MAXWLR_MWL I3C_MAXWLR_MWL_Msk /*!< Maximum Write Length */ + +/**************** Bit definition for I3C_TIMINGR0 register ******************/ +#define I3C_TIMINGR0_SCLL_PP_Pos (0UL) +#define I3C_TIMINGR0_SCLL_PP_Msk (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos) /*!< 0x000000FF */ +#define I3C_TIMINGR0_SCLL_PP I3C_TIMINGR0_SCLL_PP_Msk /*!< SCL Low duration during I3C Push-Pull phases */ +#define I3C_TIMINGR0_SCLH_I3C_Pos (8UL) +#define I3C_TIMINGR0_SCLH_I3C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos) /*!< 0x0000FF00 */ +#define I3C_TIMINGR0_SCLH_I3C I3C_TIMINGR0_SCLH_I3C_Msk /*!< SCL High duration during I3C Open-drain and Push-Pull phases */ +#define I3C_TIMINGR0_SCLL_OD_Pos (16UL) +#define I3C_TIMINGR0_SCLL_OD_Msk (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos) /*!< 0x00FF0000 */ +#define I3C_TIMINGR0_SCLL_OD I3C_TIMINGR0_SCLL_OD_Msk /*!< SCL Low duration during I3C Open-drain phases and I2C transfer */ +#define I3C_TIMINGR0_SCLH_I2C_Pos (24UL) +#define I3C_TIMINGR0_SCLH_I2C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos) /*!< 0xFF000000 */ +#define I3C_TIMINGR0_SCLH_I2C I3C_TIMINGR0_SCLH_I2C_Msk /*!< SCL High duration during I2C transfer */ + +/**************** Bit definition for I3C_TIMINGR1 register ******************/ +#define I3C_TIMINGR1_AVAL_Pos (0UL) +#define I3C_TIMINGR1_AVAL_Msk (0xFFUL << I3C_TIMINGR1_AVAL_Pos) /*!< 0x000000FF */ +#define I3C_TIMINGR1_AVAL I3C_TIMINGR1_AVAL_Msk /*!< Timing for I3C Bus Idle or Available condition */ +#define I3C_TIMINGR1_ASNCR_Pos (8UL) +#define I3C_TIMINGR1_ASNCR_Msk (0x3UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000300 */ +#define I3C_TIMINGR1_ASNCR I3C_TIMINGR1_ASNCR_Msk /*!< Activity State of the New Controller */ +#define I3C_TIMINGR1_ASNCR_0 (0x1UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000100 */ +#define I3C_TIMINGR1_ASNCR_1 (0x2UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000200 */ +#define I3C_TIMINGR1_FREE_Pos (16UL) +#define I3C_TIMINGR1_FREE_Msk (0x7FUL << I3C_TIMINGR1_FREE_Pos) /*!< 0x007F0000 */ +#define I3C_TIMINGR1_FREE I3C_TIMINGR1_FREE_Msk /*!< Timing for I3C Bus Free condition */ +#define I3C_TIMINGR1_SDA_HD_Pos (28UL) +#define I3C_TIMINGR1_SDA_HD_Msk (0x3UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x30000000 */ +#define I3C_TIMINGR1_SDA_HD I3C_TIMINGR1_SDA_HD_Msk /*!< SDA Hold Duration */ +#define I3C_TIMINGR1_SDA_HD_0 (0x1UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x10000000 */ +#define I3C_TIMINGR1_SDA_HD_1 (0x2UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for I3C_TIMINGR2 register ******************/ +#define I3C_TIMINGR2_STALLT_Pos (0UL) +#define I3C_TIMINGR2_STALLT_Msk (0x1UL << I3C_TIMINGR2_STALLT_Pos) /*!< 0x00000001 */ +#define I3C_TIMINGR2_STALLT I3C_TIMINGR2_STALLT_Msk /*!< Stall on T bit */ +#define I3C_TIMINGR2_STALLD_Pos (1UL) +#define I3C_TIMINGR2_STALLD_Msk (0x1UL << I3C_TIMINGR2_STALLD_Pos) /*!< 0x00000002 */ +#define I3C_TIMINGR2_STALLD I3C_TIMINGR2_STALLD_Msk /*!< Stall on PAR bit of data bytes */ +#define I3C_TIMINGR2_STALLC_Pos (2UL) +#define I3C_TIMINGR2_STALLC_Msk (0x1UL << I3C_TIMINGR2_STALLC_Pos) /*!< 0x00000004 */ +#define I3C_TIMINGR2_STALLC I3C_TIMINGR2_STALLC_Msk /*!< Stall on PAR bit of CCC byte */ +#define I3C_TIMINGR2_STALLA_Pos (3UL) +#define I3C_TIMINGR2_STALLA_Msk (0x1UL << I3C_TIMINGR2_STALLA_Pos) /*!< 0x00000008 */ +#define I3C_TIMINGR2_STALLA I3C_TIMINGR2_STALLA_Msk /*!< Stall on ACK bit */ +#define I3C_TIMINGR2_STALLR_Pos (4UL) +#define I3C_TIMINGR2_STALLR_Msk (0x1UL << I3C_TIMINGR2_STALLR_Pos) /*!< 0x00000010 */ +#define I3C_TIMINGR2_STALLR I3C_TIMINGR2_STALLR_Msk /*!< Stall on I2C Read ACK bit */ +#define I3C_TIMINGR2_STALLS_Pos (5UL) +#define I3C_TIMINGR2_STALLS_Msk (0x1UL << I3C_TIMINGR2_STALLS_Pos) /*!< 0x00000020 */ +#define I3C_TIMINGR2_STALLS I3C_TIMINGR2_STALLS_Msk /*!< Stall on I2C Write ACK bit */ +#define I3C_TIMINGR2_STALLL_Pos (6UL) +#define I3C_TIMINGR2_STALLL_Msk (0x1UL << I3C_TIMINGR2_STALLL_Pos) /*!< 0x00000040 */ +#define I3C_TIMINGR2_STALLL I3C_TIMINGR2_STALLL_Msk /*!< Stall on I2C Address ACK bit */ +#define I3C_TIMINGR2_STALL_Pos (8UL) +#define I3C_TIMINGR2_STALL_Msk (0xFFUL << I3C_TIMINGR2_STALL_Pos) /*!< 0x0000FF00 */ +#define I3C_TIMINGR2_STALL I3C_TIMINGR2_STALL_Msk /*!< Controller Stall duration */ + +/******************* Bit definition for I3C_BCR register ********************/ +#define I3C_BCR_BCR_Pos (0UL) +#define I3C_BCR_BCR_Msk (0xFFUL << I3C_BCR_BCR_Pos) /*!< 0x000000FF */ +#define I3C_BCR_BCR I3C_BCR_BCR_Msk /*!< Bus Characteristics */ +#define I3C_BCR_BCR0_Pos (0UL) +#define I3C_BCR_BCR0_Msk (0x1UL << I3C_BCR_BCR0_Pos) /*!< 0x00000001 */ +#define I3C_BCR_BCR0 I3C_BCR_BCR0_Msk /*!< Max Data Speed Limitation */ +#define I3C_BCR_BCR1_Pos (1UL) +#define I3C_BCR_BCR1_Msk (0x1UL << I3C_BCR_BCR1_Pos) /*!< 0x00000002 */ +#define I3C_BCR_BCR1 I3C_BCR_BCR1_Msk /*!< IBI Request capable */ +#define I3C_BCR_BCR2_Pos (2UL) +#define I3C_BCR_BCR2_Msk (0x1UL << I3C_BCR_BCR2_Pos) /*!< 0x00000004 */ +#define I3C_BCR_BCR2 I3C_BCR_BCR2_Msk /*!< IBI Payload additional Mandatory Data Byte */ +#define I3C_BCR_BCR3_Pos (3UL) +#define I3C_BCR_BCR3_Msk (0x1UL << I3C_BCR_BCR3_Pos) /*!< 0x00000008 */ +#define I3C_BCR_BCR3 I3C_BCR_BCR3_Msk /*!< Offline capable */ +#define I3C_BCR_BCR4_Pos (4UL) +#define I3C_BCR_BCR4_Msk (0x1UL << I3C_BCR_BCR4_Pos) /*!< 0x00000010 */ +#define I3C_BCR_BCR4 I3C_BCR_BCR4_Msk /*!< Virtual target support */ +#define I3C_BCR_BCR5_Pos (5UL) +#define I3C_BCR_BCR5_Msk (0x1UL << I3C_BCR_BCR5_Pos) /*!< 0x00000020 */ +#define I3C_BCR_BCR5 I3C_BCR_BCR5_Msk /*!< Advanced capabilities */ +#define I3C_BCR_BCR6_Pos (6UL) +#define I3C_BCR_BCR6_Msk (0x1UL << I3C_BCR_BCR6_Pos) /*!< 0x00000040 */ +#define I3C_BCR_BCR6 I3C_BCR_BCR6_Msk /*!< Device Role shared during Dynamic Address Assignment */ + +/******************* Bit definition for I3C_DCR register ********************/ +#define I3C_DCR_DCR_Pos (0UL) +#define I3C_DCR_DCR_Msk (0xFFUL << I3C_DCR_DCR_Pos) /*!< 0x000000FF */ +#define I3C_DCR_DCR I3C_DCR_DCR_Msk /*!< Devices Characteristics */ + +/***************** Bit definition for I3C_GETCAPR register ******************/ +#define I3C_GETCAPR_CAPPEND_Pos (14UL) +#define I3C_GETCAPR_CAPPEND_Msk (0x1UL << I3C_GETCAPR_CAPPEND_Pos) /*!< 0x00004000 */ +#define I3C_GETCAPR_CAPPEND I3C_GETCAPR_CAPPEND_Msk /*!< IBI Request with Mandatory Data Byte */ + +/***************** Bit definition for I3C_CRCAPR register *******************/ +#define I3C_CRCAPR_CAPDHOFF_Pos (3UL) +#define I3C_CRCAPR_CAPDHOFF_Msk (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos) /*!< 0x00000008 */ +#define I3C_CRCAPR_CAPDHOFF I3C_CRCAPR_CAPDHOFF_Msk /*!< Controller-role handoff needed */ +#define I3C_CRCAPR_CAPGRP_Pos (9UL) +#define I3C_CRCAPR_CAPGRP_Msk (0x1UL << I3C_CRCAPR_CAPGRP_Pos) /*!< 0x00000200 */ +#define I3C_CRCAPR_CAPGRP I3C_CRCAPR_CAPGRP_Msk /*!< Group Address handoff supported */ + +/**************** Bit definition for I3C_GETMXDSR register ******************/ +#define I3C_GETMXDSR_HOFFAS_Pos (0UL) +#define I3C_GETMXDSR_HOFFAS_Msk (0x3UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000003 */ +#define I3C_GETMXDSR_HOFFAS I3C_GETMXDSR_HOFFAS_Msk /*!< Handoff Activity State */ +#define I3C_GETMXDSR_HOFFAS_0 (0x1UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000001 */ +#define I3C_GETMXDSR_HOFFAS_1 (0x2UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000002 */ +#define I3C_GETMXDSR_FMT_Pos (8UL) +#define I3C_GETMXDSR_FMT_Msk (0x3UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000300 */ +#define I3C_GETMXDSR_FMT I3C_GETMXDSR_FMT_Msk /*!< Get Max Data Speed response in format 2 */ +#define I3C_GETMXDSR_FMT_0 (0x1UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000100 */ +#define I3C_GETMXDSR_FMT_1 (0x2UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000200 */ +#define I3C_GETMXDSR_RDTURN_Pos (16UL) +#define I3C_GETMXDSR_RDTURN_Msk (0xFFUL << I3C_GETMXDSR_RDTURN_Pos) /*!< 0x00FF0000 */ +#define I3C_GETMXDSR_RDTURN I3C_GETMXDSR_RDTURN_Msk /*!< Max Read Turnaround Middle Byte */ +#define I3C_GETMXDSR_TSCO_Pos (24UL) +#define I3C_GETMXDSR_TSCO_Msk (0x1UL << I3C_GETMXDSR_TSCO_Pos) /*!< 0x01000000 */ +#define I3C_GETMXDSR_TSCO I3C_GETMXDSR_TSCO_Msk /*!< Clock-to-data Turnaround time */ + +/****************** Bit definition for I3C_EPIDR register *******************/ +#define I3C_EPIDR_MIPIID_Pos (12UL) +#define I3C_EPIDR_MIPIID_Msk (0xFUL << I3C_EPIDR_MIPIID_Pos) /*!< 0x0000F000 */ +#define I3C_EPIDR_MIPIID I3C_EPIDR_MIPIID_Msk /*!< MIPI Instance ID */ +#define I3C_EPIDR_IDTSEL_Pos (16UL) +#define I3C_EPIDR_IDTSEL_Msk (0x1UL << I3C_EPIDR_IDTSEL_Pos) /*!< 0x00010000 */ +#define I3C_EPIDR_IDTSEL I3C_EPIDR_IDTSEL_Msk /*!< ID Type Selector */ +#define I3C_EPIDR_MIPIMID_Pos (17UL) +#define I3C_EPIDR_MIPIMID_Msk (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos) /*!< 0xFFFE0000 */ +#define I3C_EPIDR_MIPIMID I3C_EPIDR_MIPIMID_Msk /*!< MIPI Manufacturer ID */ + +/******************************************************************************/ +/* */ +/* ICACHE */ +/* */ +/******************************************************************************/ +/****************** Bit definition for ICACHE_CR register *******************/ +#define ICACHE_CR_EN_Pos (0UL) +#define ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) /*!< 0x00000001 */ +#define ICACHE_CR_EN ICACHE_CR_EN_Msk /*!< Enable */ +#define ICACHE_CR_CACHEINV_Pos (1UL) +#define ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ +#define ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk /*!< Cache invalidation */ +#define ICACHE_CR_WAYSEL_Pos (2UL) +#define ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) /*!< 0x00000004 */ +#define ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk /*!< Ways selection */ +#define ICACHE_CR_HITMEN_Pos (16UL) +#define ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) /*!< 0x00010000 */ +#define ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk /*!< Hit monitor enable */ +#define ICACHE_CR_MISSMEN_Pos (17UL) +#define ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) /*!< 0x00020000 */ +#define ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk /*!< Miss monitor enable */ +#define ICACHE_CR_HITMRST_Pos (18UL) +#define ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) /*!< 0x00040000 */ +#define ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk /*!< Hit monitor reset */ +#define ICACHE_CR_MISSMRST_Pos (19UL) +#define ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) /*!< 0x00080000 */ +#define ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk /*!< Miss monitor reset */ + +/****************** Bit definition for ICACHE_SR register *******************/ +#define ICACHE_SR_BUSYF_Pos (0UL) +#define ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk /*!< Busy flag */ +#define ICACHE_SR_BSYENDF_Pos (1UL) +#define ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk /*!< Busy end flag */ +#define ICACHE_SR_ERRF_Pos (2UL) +#define ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk /*!< Cache error flag */ + +/****************** Bit definition for ICACHE_IER register ******************/ +#define ICACHE_IER_BSYENDIE_Pos (1UL) +#define ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */ +#define ICACHE_IER_ERRIE_Pos (2UL) +#define ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk /*!< Cache error interrupt enable */ + +/****************** Bit definition for ICACHE_FCR register ******************/ +#define ICACHE_FCR_CBSYENDF_Pos (1UL) +#define ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk /*!< Busy end flag clear */ +#define ICACHE_FCR_CERRF_Pos (2UL) +#define ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_FCR_CERRF ICACHE_FCR_CERRF_Msk /*!< Cache error flag clear */ + +/****************** Bit definition for ICACHE_HMONR register ****************/ +#define ICACHE_HMONR_HITMON_Pos (0UL) +#define ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */ +#define ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk /*!< Cache hit monitor register */ + +/****************** Bit definition for ICACHE_MMONR register ****************/ +#define ICACHE_MMONR_MISSMON_Pos (0UL) +#define ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */ +#define ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk /*!< Cache miss monitor register */ + +/****************** Bit definition for ICACHE_CRRx register *****************/ +#define ICACHE_CRRx_BASEADDR_Pos (0UL) +#define ICACHE_CRRx_BASEADDR_Msk (0xFFUL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x000000FF */ +#define ICACHE_CRRx_BASEADDR ICACHE_CRRx_BASEADDR_Msk /*!< Base address of region X to remap */ +#define ICACHE_CRRx_RSIZE_Pos (9UL) +#define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00 */ +#define ICACHE_CRRx_RSIZE ICACHE_CRRx_RSIZE_Msk /*!< Region X size */ +#define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200 */ +#define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400 */ +#define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800 */ +#define ICACHE_CRRx_REN_Pos (15UL) +#define ICACHE_CRRx_REN_Msk (0x1UL << ICACHE_CRRx_REN_Pos) /*!< 0x00008000 */ +#define ICACHE_CRRx_REN ICACHE_CRRx_REN_Msk /*!< Region X enable */ +#define ICACHE_CRRx_REMAPADDR_Pos (16UL) +#define ICACHE_CRRx_REMAPADDR_Msk (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x07FF0000 */ +#define ICACHE_CRRx_REMAPADDR ICACHE_CRRx_REMAPADDR_Msk /*!< Remap address of Region X to be remapped */ +#define ICACHE_CRRx_MSTSEL_Pos (28UL) +#define ICACHE_CRRx_MSTSEL_Msk (0x1UL << ICACHE_CRRx_MSTSEL_Pos) /*!< 0x10000000 */ +#define ICACHE_CRRx_MSTSEL ICACHE_CRRx_MSTSEL_Msk /*!< Region X AHB cache master selection */ +#define ICACHE_CRRx_HBURST_Pos (31UL) +#define ICACHE_CRRx_HBURST_Msk (0x1UL << ICACHE_CRRx_HBURST_Pos) /*!< 0x80000000 */ +#define ICACHE_CRRx_HBURST ICACHE_CRRx_HBURST_Msk /*!< Region X output burst type */ + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG */ +/* */ +/******************************************************************************/ +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY_Pos (0UL) +#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ +#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0UL) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4UL) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7UL) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8UL) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12UL) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15UL) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16UL) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20UL) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22UL) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23UL) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24UL) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28UL) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30UL) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31UL) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0UL) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24UL) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31UL) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0UL) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4UL) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7UL) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8UL) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12UL) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15UL) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16UL) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20UL) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22UL) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23UL) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24UL) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28UL) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30UL) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31UL) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0UL) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0UL) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1UL) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2UL) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3UL) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4UL) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5UL) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6UL) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0UL) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1UL) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2UL) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3UL) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4UL) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5UL) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6UL) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0UL) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1UL) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2UL) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3UL) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4UL) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5UL) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6UL) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0UL) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1UL) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2UL) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3UL) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4UL) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5UL) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6UL) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_TAMPTSCR register ******************/ +#define RTC_TAMPTSCR_TAMP1TS_Pos (0UL) +#define RTC_TAMPTSCR_TAMP1TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP1TS_Pos) /*!< 0x00000001 */ +#define RTC_TAMPTSCR_TAMP1TS RTC_TAMPTSCR_TAMP1TS_Msk +#define RTC_TAMPTSCR_TAMP2TS_Pos (1UL) +#define RTC_TAMPTSCR_TAMP2TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP2TS_Pos) /*!< 0x00000002 */ +#define RTC_TAMPTSCR_TAMP2TS RTC_TAMPTSCR_TAMP2TS_Msk +#define RTC_TAMPTSCR_TAMP3TS_Pos (2UL) +#define RTC_TAMPTSCR_TAMP3TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP3TS_Pos) /*!< 0x00000004 */ +#define RTC_TAMPTSCR_TAMP3TS RTC_TAMPTSCR_TAMP3TS_Msk +#define RTC_TAMPTSCR_TAMP4TS_Pos (3UL) +#define RTC_TAMPTSCR_TAMP4TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP4TS_Pos) /*!< 0x00000008 */ +#define RTC_TAMPTSCR_TAMP4TS RTC_TAMPTSCR_TAMP4TS_Msk +#define RTC_TAMPTSCR_TAMP5TS_Pos (4UL) +#define RTC_TAMPTSCR_TAMP5TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP5TS_Pos) /*!< 0x00000010 */ +#define RTC_TAMPTSCR_TAMP5TS RTC_TAMPTSCR_TAMP5TS_Msk +#define RTC_TAMPTSCR_ITAMPTS_Pos (16UL) +#define RTC_TAMPTSCR_ITAMPTS_Msk (0x1UL << RTC_TAMPTSCR_ITAMPTS_Pos) /*!< 0x00010000 */ +#define RTC_TAMPTSCR_ITAMPTS RTC_TAMPTSCR_ITAMPTS_Msk + +/******************** Bits definition for RTC_TSIDR register ******************/ +#define RTC_TSIDR_TSID_Pos (0UL) +#define RTC_TSIDR_TSID_Msk (0x3FUL << RTC_TSIDR_TSID_Pos) /*!< 0x0000003F */ +#define RTC_TSIDR_TSID RTC_TSIDR_TSID_Msk +#define RTC_TSIDR_TSID_0 (0x1UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000001 */ +#define RTC_TSIDR_TSID_1 (0x2UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000002 */ +#define RTC_TSIDR_TSID_2 (0x4UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000004 */ +#define RTC_TSIDR_TSID_3 (0x8UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000008 */ +#define RTC_TSIDR_TSID_4 (0x10UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000010 */ +#define RTC_TSIDR_TSID_5 (0x20UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000020 */ + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0UL) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0UL) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Serial Audio Interface */ +/* */ +/******************************************************************************/ +/******************* Bit definition for SAI_xCR1 register *******************/ +#define SAI_xCR1_MODE_Pos (0UL) +#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ +#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/******************************************************************************/ +/* */ +/* VREFBUF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for VREFBUF_CSR register ****************/ +#define VREFBUF_CSR_ENVR_Pos (0UL) +#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ +#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p4 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32u3xx.h" /*!< STM32U3xx System */ + + +/* ================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================================================== */ +/** @addtogroup STM32U3xx_peripherals + * @{ + */ + +/** + * @brief ADC Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC channel preselection register, Address offset: 0x1C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + __IO uint32_t OFCFGR1; /*!< ADC offset configuration register 1, Address offset: 0x50 */ + __IO uint32_t OFCFGR2; /*!< ADC offset configuration register 2, Address offset: 0x54 */ + __IO uint32_t OFCFGR3; /*!< ADC offset configuration register 3, Address offset: 0x58 */ + __IO uint32_t OFCFGR4; /*!< ADC offset configuration register 4, Address offset: 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ + uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x90 */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + __IO uint32_t AWD1LTR; /*!< ADC analog watchdog 1 low threshold register, Address offset: 0xA8 */ + __IO uint32_t AWD1HTR; /*!< ADC analog watchdog 1 high threshold register, Address offset: 0xAC */ + __IO uint32_t AWD2LTR; /*!< ADC analog watchdog 2 low threshold register, Address offset: 0xB0 */ + __IO uint32_t AWD2HTR; /*!< ADC analog watchdog 2 high threshold register, Address offset: 0xB4 */ + __IO uint32_t AWD3LTR; /*!< ADC analog watchdog 3 low threshold register, Address offset: 0xB8 */ + __IO uint32_t AWD3HTR; /*!< ADC analog watchdog 3 high threshold register, Address offset: 0xBC */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xC4 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0xC8 */ + __IO uint32_t OR; /*!< ADC option register, Address offset: 0xD0 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for dual mode 32-bit, Address offset: 0x310 */ +} ADC_Common_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168]; /*!< Reserved, 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief Coupling and chaining bridge (CCB) + */ +typedef struct +{ + __IO uint32_t CR; /*!< CCB ccontrol register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CCB status register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t REFTAGR[4]; /*!< CCB reference tag register, Address offset: 0x10 */ +} CCB_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control/status register , Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1LFZR; /*!< Debug MCU APB1L freeze register, Address offset: 0x08 */ + __IO uint32_t APB1HFZR; /*!< Debug MCU APB1H freeze register, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x18 - 0x20 */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2[54]; /*!< Reserved, 0x24 - 0xFC */ + __IO uint32_t SR; /*!< Debug MCU status register, Address offset: 0xFC */ + __IO uint32_t DGB_AUTH_HOST; /*!< Debug MCU debug host authentication register, Address offset: 0x100 */ + __IO uint32_t DGB_AUTH_DEVICE; /*!< Debug MCU debug device authentication register, Address offset: 0x104 */ + uint32_t RESERVED3[946]; /*!< Reserved, 0x108 - 0xFD0 */ + __IO uint32_t PIDR4; /*!< Debug MCU CoreSight peripheral identity register 4, Address offset: 0xFD0 */ + __IO uint32_t PIDR0; /*!< Debug MCU CoreSight peripheral identity register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU CoreSight peripheral identity register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU CoreSight peripheral identity register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU CoreSight peripheral identity register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU CoreSight component identity register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU CoreSight component identity register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU CoreSight component identity register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU CoreSight component identity register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @ brief Delay Block + */ +typedef struct +{ + __IO uint32_t CR; /*!< Delay Block Control Register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< Delay Block Configuration Register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128]; /*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58]; /*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t PDKEY1R; /*!< FLASH bank 1 power-down key register, Address offset: 0x18 */ + __IO uint32_t PDKEY2R; /*!< FLASH bank 2 power-down key register, Address offset: 0x1C */ + __IO uint32_t SR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t CR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCCR; /*!< FLASH ECC correction register, Address offset: 0x30 */ + __IO uint32_t ECCDR; /*!< FLASH ECC detection register, Address offset: 0x34 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x38 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t BOOT0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t BOOT1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SBOOT0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ + __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ + __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ + __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ + __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ + __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x70-0x7C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ + __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0x84 */ + __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0x88 */ + __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0x8C */ + uint32_t RESERVED5[4]; /*!< Reserved, Address offset: 0x90-0x9C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ + __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0xA4 */ + __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0xA8 */ + __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0xAC */ + uint32_t RESERVED6[4]; /*!< Reserved, Address offset: 0xB0-0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + __IO uint32_t SECHDPEXTR; /*!< FLASH HDP extension register, Address offset: 0xC8 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0xCC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ + __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xD4 */ + __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xD8 */ + __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xDC */ + uint32_t RESERVED8[4]; /*!< Reserved, Address offset: 0xE0-0xEC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ + __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0xF4 */ + __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0xF8 */ + __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0xFC */ + uint32_t RESERVED9[4]; /*!< Reserved, Address offset: 0x100-0x10C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x110 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x114 */ + __IO uint32_t OEM1KEYR3; /*!< FLASH OEM1 key register 3, Address offset: 0x118 */ + __IO uint32_t OEM1KEYR4; /*!< FLASH OEM1 key register 4, Address offset: 0x11C */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x120 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x124 */ + __IO uint32_t OEM2KEYR3; /*!< FLASH OEM2 key register 3, Address offset: 0x128 */ + __IO uint32_t OEM2KEYR4; /*!< FLASH OEM2 key register 4, Address offset: 0x12C */ + __IO uint32_t OEMKEYSR; /*!< FLASH OEM key status register, Address offset: 0x130 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[12]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x12C */ + uint32_t RESERVED3[52]; /*!< Reserved3, Address offset: 0x130-0x200 */ + __IO uint32_t PRIVCFGR[12]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x22C */ +} GTZC_MPCBB_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ +} GTZC_TZSC_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + __IO uint32_t SHA3CFGR; /*!< HASH SHA-3 configuration register, Address offset: 0x28 */ + uint32_t RESERVED[51]; /*!< Reserved, 0x2C-0xF4 */ + __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[50]; /*!< HASH digest registers, Address offset: 0x310-0x3D4 */ +} HASH_DIGEST_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; /*!< I2C Autonomous mode control register, Address offset: 0x2C */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + __IO uint32_t MISR; /*!< I3C Masked Interrupt Status register, Address offset: 0x5C */ + __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief LCD + */ +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief MDF/ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED0[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t TRGISELR; /*!< MDF Trigger Input Selection Register, Address offset: 0x20 */ +} MDF_TypeDef; + +/** + * @brief MDF/ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x94-0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + uint32_t RESERVED1[1]; /*!< Reserved, 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED3[10]; /*!< Reserved, 0xC8-0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t BDCR; /*!< Power backup domain control register, Address offset: 0x24 */ + __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ + __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ + __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ + __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ + __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ + __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ + __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ + __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ + __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ + __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ + __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */ + __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ + __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ + __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ + uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x90 -> 0xAC */ + __IO uint32_t I3CPUCR1; /*!< Power I3C pull-up control register 1, Address offset: 0xB0 */ + __IO uint32_t I3CPUCR2; /*!< Power I3C pull-up control register 2, Address offset: 0xB4 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt status register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t PEAR; /*!< Parity error address register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt clear register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< Write protection register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< Write protection register 2, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t PARKEYR; /*!< Parity key register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< Erase key register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC Clock Control Register Address offset: 0x000 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x004 */ + __IO uint32_t ICSCR1; /*!< RCC Internal Clock Sources Calibration Register 1 Address offset: 0x008 */ + __IO uint32_t ICSCR2; /*!< RCC Internal Clock Sources Calibration Register 2 Address offset: 0x00C */ + __IO uint32_t ICSCR3; /*!< RCC Internal Clock Sources Calibration Register 3 Address offset: 0x010 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x014 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x018 */ + __IO uint32_t CFGR1; /*!< RCC Clock Configuration Register 1 Address offset: 0x01C */ + __IO uint32_t CFGR2; /*!< RCC Clock Configuration Register 2 Address offset: 0x020 */ + __IO uint32_t CFGR3; /*!< RCC Clock Configuration Register 3 Address offset: 0x024 */ + __IO uint32_t CFGR4; /*!< RCC Clock Configuration Register 4 Address offset: 0x028 */ + uint32_t RESERVED2[9]; /*!< Reserved Address offset: 0x02C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x050 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x054 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x058 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x05C */ + __IO uint32_t AHB1RSTR1; /*!< AHB1 Peripherals Reset Register 1 Address offset: 0x060 */ + __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x064 */ + __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x068 */ + uint32_t RESERVED4[2]; /*!< Reserved Address offset: 0x06C */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x074 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x078 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x07C */ + __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x080 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x084 */ + __IO uint32_t AHB1ENR1; /*!< AHB1 Peripherals Clock Enable Register 1 Address offset: 0x088 */ + __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x08C */ + __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x090 */ + __IO uint32_t AHB1ENR2; /*!< AHB1 Peripherals Clock Enable Register 2 Address offset: 0x094 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x098 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x09C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0x0A0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0x0A4 */ + __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0x0A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x0AC */ + __IO uint32_t AHB1SLPENR1; /*!< AHB1 Peripherals Clock Enable in Sleep Mode Register 1 Address offset: 0x0B0 */ + __IO uint32_t AHB2SLPENR1; /*!< AHB2 Peripherals Clock Enable in Sleep Mode Register 1 Address offset: 0x0B4 */ + __IO uint32_t AHB2SLPENR2; /*!< AHB2 Peripherals Clock Enable in Sleep Mode Register 2 Address offset: 0x0B8 */ + __IO uint32_t AHB1SLPENR2; /*!< AHB1 Peripherals Clock Enable in Sleep Mode Register 2 Address offset: 0x0BC */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x0C0 */ + __IO uint32_t APB1SLPENR1; /*!< APB1 Peripherals Clock Enable in Sleep Mode Register 1 Address offset: 0x0C4 */ + __IO uint32_t APB1SLPENR2; /*!< APB1 Peripherals Clock Enable in Sleep Mode Register 2 Address offset: 0x0C8 */ + __IO uint32_t APB2SLPENR; /*!< APB2 Peripherals Clock Enable in Sleep Mode Register Address offset: 0x0CC */ + __IO uint32_t APB3SLPENR; /*!< APB3 Peripherals Clock Enable in Sleep Mode Register Address offset: 0x0D0 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0x0D4 */ + __IO uint32_t AHB1STPENR1; /*!< AHB1 Peripherals Clock Enable in Stop Mode Register 1 Address offset: 0x0D8 */ + __IO uint32_t AHB2STPENR1; /*!< AHB2 Peripherals Clock Enable in Stop Mode Register 1 Address offset: 0x0DC */ + uint32_t RESERVED10[3]; /*!< Reserved Address offset: 0x0E0 */ + __IO uint32_t APB1STPENR1; /*!< APB1 Peripherals Clock Enable in Stop Mode Register 1 Address offset: 0x0EC */ + __IO uint32_t APB1STPENR2; /*!< APB1 Peripherals Clock Enable in Stop Mode Register 2 Address offset: 0x0F0 */ + __IO uint32_t APB2STPENR; /*!< APB2 Peripherals Clock Enable in Stop Mode Register Address offset: 0x0F4 */ + __IO uint32_t APB3STPENR; /*!< APB3 Peripherals Clock Enable in Stop Mode Register Address offset: 0x0F8 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0FC */ + __IO uint32_t CCIPR1; /*!< Peripherals Independent Clocks Configuration Register 1 Address offset: 0x100 */ + __IO uint32_t CCIPR2; /*!< Peripherals Independent Clocks Configuration Register 2 Address offset: 0x104 */ + __IO uint32_t CCIPR3; /*!< Peripherals Independent Clocks Configuration Register 3 Address offset: 0x108 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x10C */ + __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0x110 */ + __IO uint32_t CSR; /*!< Control & Status Register Address offset: 0x114 */ + uint32_t RESERVED13[6]; /*!< Reserved Address offset: 0x118 */ + __IO uint32_t SECCFGR; /*!< RCC Secure Configuration Register Address offset: 0x130 */ + __IO uint32_t PRIVCFGR; /*!< RCC Privilege Configuration Register Address offset: 0x134 */ +} RCC_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x60 */ + __IO uint32_t TAMPTSCR; /*!< RTC timestamp on tamper control register, Address offset: 0x64 */ + __IO uint32_t TSIDR; /*!< RTC timestamp status register, Address offset: 0x68 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + uint32_t RESERVED[17]; /*!< Reserved, Address offset: 0x00 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED2; /*!< RESERVED2, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ +} SYSCFG_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + uint32_t RESERVED1[4]; /*!< Reserved, 0x10 -- 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x44 -- 0x50 */ + __IO uint32_t RPCFGR; /*!< TAMP resources protection configuration register, Address offset: 0x54 */ + uint32_t RESERVED3[42]; /*!< Reserved, 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Touch Sensing Controller (TSC) + */ +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, 0x34-0x4C */ +} TSC_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220]; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + __IO uint32_t RESERVED0[8]; /*!< Reserved, */ + __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IO uint32_t TXBD; /*!= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* ================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* ================================================================================================================== */ +/** @addtogroup STM32U3xx_Peripheral_peripheralAddr + * @{ + */ + +/*!< Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS 0x08000000UL /*!< FLASH non-secure base address */ +#define SYSTEM_FLASH_BASE_NS 0x0BF80000UL /*!< System FLASH non-secure base address */ +#define SRAM1_BASE_NS 0x20000000UL /*!< SRAM1 non-secure base address */ +#define SRAM2_BASE_NS 0x20018000UL /*!< SRAM2 non-secure base address */ +#define SRAM3_BASE_NS 0x20028000UL /*!< SRAM3 non-secure base address */ +#define SRAM4_BASE_NS 0x20068000UL /*!< SRAM4 non-secure base address */ + +#define PERIPH_BASE_NS 0x40000000UL /*!< Peripheral non-secure base address */ +#define EXTRAM_BASE_NS 0x90000000UL /*!< External RAM base address */ +#define EPPB_BASE 0xE0040000UL /*!< External Private Peripheral Bus */ + +/*!< OTP, Engineering bytes, Option bytes defines */ +#define FLASH_OTP_BASE (SYSTEM_FLASH_BASE_NS + 0x00020000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE 0x00000200U /*!< 512 bytes OTP (one-time programmable) */ +#define FLASH_ENGY_BASE (SYSTEM_FLASH_BASE_NS + 0x00020500UL) +#define PACKAGE_BASE (FLASH_ENGY_BASE) /*!< Package data register base address */ +#define UID_BASE (FLASH_ENGY_BASE + 0x00000200UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (FLASH_ENGY_BASE + 0x000002A0UL) /*!< Flash size data register base address */ +#define UID64_BASE (FLASH_ENGY_BASE + 0x00000500UL) /*!< 64-bit Unique device Identification */ + +/*!< Memory sizes */ +/* Internal Flash size */ +#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? 0x180000U : \ + ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? 0x180000U : \ + (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U))) + +/*!< Internal SRAMs size */ +#define SRAM1_SIZE 0x00018000UL /*!< SRAM1=96k */ +#define SRAM2_SIZE 0x00010000UL /*!< SRAM2=64k */ +#define SRAM3_SIZE 0x00040000UL /*!< SRAM3=256k */ +#define SRAM4_SIZE 0x00010000UL /*!< SRAM4=64k */ + +/*!< Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00040000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x00000000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x00000400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x00000800UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x00001000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x00001400UL) +#define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x00002000UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x00002C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x00003000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x00003800UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x00004400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x00004800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x00004C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x00005000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x00005400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x00005800UL) +#define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x00005C00UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x00006000UL) +#define OPAMP1_BASE_NS (APB1PERIPH_BASE_NS + 0x00007000UL) +#define OPAMP2_BASE_NS (OPAMP1_BASE_NS + 0x0000010UL) +#define VREFBUF_BASE_NS (APB1PERIPH_BASE_NS + 0x00007400UL) +#define RTC_BASE_NS (APB1PERIPH_BASE_NS + 0x00007800UL) +#define TAMP_BASE_NS (APB1PERIPH_BASE_NS + 0x00007C00UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x00009400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0x0000A400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0x0000A500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0x0000AC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x00002C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x00003000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x00003400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x00003800UL) +#define TIM12_BASE_NS (APB2PERIPH_BASE_NS + 0x00003C00UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x00004000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x00004400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x00004800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x00005400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x0000004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x0000024UL) +#define USB_DRD_BASE_NS (APB2PERIPH_BASE_NS + 0x00006000UL) +#define USB_DRD_PMAADDR_NS (APB2PERIPH_BASE_NS + 0x00006400UL) +#define I3C2_BASE_NS (APB2PERIPH_BASE_NS + 0x00006C00UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x00000050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x000000D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x00000150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x000001D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x00000250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x000002D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x00000350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x000003D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x00000450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x000004D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x00000550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x000005D0UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x00002000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x00003000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x00004000UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x00006000UL) +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x00000040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x00000080UL) +#define HSP1_BASE_NS (AHB1PERIPH_BASE_NS + 0x0000C000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x00010400UL) +#define PWR_BASE_NS (AHB1PERIPH_BASE_NS + 0x00010800UL) +#define RCC_BASE_NS (AHB1PERIPH_BASE_NS + 0x00010C00UL) +#define EXTI_BASE_NS (AHB1PERIPH_BASE_NS + 0x00012000UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x00012400UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x00012C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x00013000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x00013400UL) +#define GTZC_MPCBB4_BASE_NS (AHB1PERIPH_BASE_NS + 0x00013800UL) +#define ADF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x00014000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x00000080UL) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x00000400UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x00002400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x00002800UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x00004400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x00004800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x00004C00UL) +#define COMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x00005400UL) +#define COMP2_BASE_NS (COMP1_BASE_NS + 0x00000004UL) +#define LCD_BASE_NS (APB3PERIPH_BASE_NS + 0x00008000UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x00001000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x00001400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x00001800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x00001C00UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008300UL) +#define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008400UL) +#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0800UL) +#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0C00UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A2400UL) +#define CCB_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A7C00UL) +#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A8000UL) +#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A8400UL) +#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0x000AF000UL) +#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0x000B1400UL) + +#if defined(CPU_IN_SECURE_STATE) +/*!< Flash, Peripheral and internal SRAMs base addresses - secure */ +#define FLASH_BASE_S 0x0C000000UL /*!< FLASH secure base address */ +#define SYSTEM_FLASH_BASE_S 0x0FF80000UL /*!< System FLASH secure base address */ +#define SRAM1_BASE_S 0x30000000UL /*!< SRAM1 secure base address */ +#define SRAM2_BASE_S 0x30018000UL /*!< SRAM2 secure base address */ +#define SRAM3_BASE_S 0x30028000UL /*!< SRAM3 secure base address */ +#define SRAM4_BASE_S 0x30068000UL /*!< SRAM4 secure base address */ +#define PERIPH_BASE_S 0x50000000UL /*!< Peripheral secure base address */ + +/*!< Peripheral memory map - secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x00040000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) + +/*!< APB1 secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x00000000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x00000400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x00000800UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x00001000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x00001400UL) +#define SPI3_BASE_S (APB1PERIPH_BASE_S + 0x00002000UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x00002C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x00003000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x00003800UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x00004400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x00004800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x00004C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x00005000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x00005400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x00005800UL) +#define I3C1_BASE_S (APB1PERIPH_BASE_S + 0x00005C00UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x00006000UL) +#define OPAMP1_BASE_S (APB1PERIPH_BASE_S + 0x00007000UL) +#define OPAMP2_BASE_S (OPAMP1_BASE_S + 0x0000010UL) +#define VREFBUF_BASE_S (APB1PERIPH_BASE_S + 0x00007400UL) +#define RTC_BASE_S (APB1PERIPH_BASE_S + 0x00007800UL) +#define TAMP_BASE_S (APB1PERIPH_BASE_S + 0x00007C00UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x00009400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0x0000A400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0x0000A500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0x0000AC00UL) + +/*!< APB2 secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x00002C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x00003000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x00003400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x00003800UL) +#define TIM12_BASE_S (APB2PERIPH_BASE_S + 0x00003C00UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x00004000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x00004400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x00004800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x00005400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x0000004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x0000024UL) +#define USB_DRD_BASE_S (APB2PERIPH_BASE_S + 0x00006000UL) +#define USB_DRD_PMAADDR_S (APB2PERIPH_BASE_S + 0x00006400UL) +#define I3C2_BASE_S (APB2PERIPH_BASE_S + 0x00006C00UL) + +/*!< AHB1 secure peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x00000050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x000000D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x00000150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x000001D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x00000250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x000002D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x00000350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x000003D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x00000450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x000004D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x00000550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x000005D0UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x00002000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x00003000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x00004000UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x00006000UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x00000040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x00000080UL) +#define HSP1_BASE_S (AHB1PERIPH_BASE_S + 0x0000C000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x00010400UL) +#define PWR_BASE_S (AHB1PERIPH_BASE_S + 0x00010800UL) +#define RCC_BASE_S (AHB1PERIPH_BASE_S + 0x00010C00UL) +#define EXTI_BASE_S (AHB1PERIPH_BASE_S + 0x00012000UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x00012400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x00012800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x00012C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x00013000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x00013400UL) +#define GTZC_MPCBB4_BASE_S (AHB1PERIPH_BASE_S + 0x00013800UL) +#define ADF1_BASE_S (AHB1PERIPH_BASE_S + 0x00014000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x00000080UL) + +/*!< APB3 secure peripherals */ +#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x00000400UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x00002400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x00002800UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x00004400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x00004800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x00004C00UL) +#define COMP1_BASE_S (APB3PERIPH_BASE_S + 0x00005400UL) +#define COMP2_BASE_S (COMP1_BASE_S + 0x00000004UL) +#define LCD_BASE_S (APB3PERIPH_BASE_S + 0x00008000UL) + +/*!< AHB2 secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00000400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00000800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00000C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x00001000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x00001400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x00001800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x00001C00UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x00008000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x00008100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x00008300UL) +#define DAC1_BASE_S (AHB2PERIPH_BASE_S + 0x00008400UL) +#define AES_BASE_S (AHB2PERIPH_BASE_S + 0x000A0000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0x000A0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0x000A0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0x000A0800UL) +#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0x000A0C00UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0x000A2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0x000A2400UL) +#define CCB_BASE_S (AHB2PERIPH_BASE_S + 0x000A7C00UL) +#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0x000A8000UL) +#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0x000A8400UL) +#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0x000AF000UL) +#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0x000B1400UL) +#endif /* CPU_IN_SECURE_STATE */ + +/*!< External memories base addresses - Not aliased */ +#define OCTOSPI1_BASE EXTRAM_BASE_NS + +/*!< DBGMCU base addresses - Not aliased */ +#define DBGMCU_BASE (EPPB_BASE + 0x00004000UL) + +/*!< USB PMA SIZE */ +#define USB_DRD_PMA_SIZE (2048U) /*!< USB PMA Size 2Kbyte */ + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START 0x0BF99040UL +#define RSSLIB_SYS_FLASH_NS_PFUNC_END 0x0BF990FFUL + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR 0xF5F5F5F5UL +#define RSSLIB_SUCCESS 0xEAEAEAEAUL + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos 0UL +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos 0UL +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos 1UL +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) +#define RSSLIB_HDPEXT_CLOSE_BOUNDARY_OPEN 0xC9C9C9C9UL /* Access to HDPx extension area and HDPx area denied but HDPx_EXT (in FLASH_HDPEXTR) increment allowed at any time */ +#define RSSLIB_HDPEXT_CLOSE_BOUNDARY_LOCK 0xD6D6D6D6UL /* Access to HDPx extension area and HDPx area denied. Update of HDPx_EXT size is not possible anymore */ + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param VectorTableAddr pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + +/** + * @brief Prototype of RSSLIB Close and exit HDP extension Function + * @detail This function close the requested hdp extension area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpExtArea notifies which hdp extension area to close, can be a combination of + * hdp extension area 1 and hdp extension area 2 + * @param VectorTableAddr pointer on the vector table containing the reset handler the function + * jumps to. + * @param CloseBound notifies if the HDP extension area should be closed with + * HDPx_EXT increment allowed or not + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDPExt_TypeDef)( uint32_t HdpExtArea, uint32_t VectorTableAddr, uint32_t CloseBound ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ + __IM RSSLIB_S_CloseExitHDPExt_TypeDef CloseExitHDPExt; /*!< RSSLIB Bootloader Close and exit HDP extension Address offset: 0x2C */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/* + * Certificate address description + */ +#define CERT_CHIP_PACK1_ADDR (0x0BF9FE00U) +#define CERT_CHIP_PACK1_SIZE (0x200U) +#define CERT_CHIP_PACK2_ADDR (0x0BF9FC00U) +#define CERT_CHIP_PACK2_SIZE (0x200U) + +#define CERT_CHIP_PACK_ADDR (CERT_CHIP_PACK2_ADDR) +#define CERT_CHIP_PACK_SIZE (CERT_CHIP_PACK1_SIZE + CERT_CHIP_PACK2_SIZE) + +#define CERT_ST_DUA_USER_FU_PUB_KEY_OFFSET (12U) +#define CERT_ST_DUA_USER_FU_PUB_KEY_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_FU_PUB_KEY_OFFSET) +#define CERT_ST_DUA_USER_FU_SIGN_OFFSET (76U) +#define CERT_ST_DUA_USER_FU_SIGN_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_FU_SIGN_OFFSET) +#define CERT_ST_DUA_USER_FU_SERIAL_OFFSET (140U) +#define CERT_ST_DUA_USER_FU_SERIAL_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_FU_SERIAL_OFFSET) + +#define CERT_ST_DUA_USER_LU_PUB_KEY_OFFSET (162U) +#define CERT_ST_DUA_USER_LU_PUB_KEY_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_LU_PUB_KEY_OFFSET) +#define CERT_ST_DUA_USER_LU_SIGN_OFFSET (226U) +#define CERT_ST_DUA_USER_LU_SIGN_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_LU_SIGN_OFFSET) +#define CERT_ST_DUA_USER_LU_SERIAL_OFFSET (290U) +#define CERT_ST_DUA_USER_LU_SERIAL_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_LU_SERIAL_OFFSET) +/** @} */ /* End of group STM32U3xx_Peripheral_peripheralAddr */ + + +/* ================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================================================== */ +/** @addtogroup STM32U3xx_Peripheral_declaration + * @{ + */ +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) +#define AES_NS ((AES_TypeDef *) AES_BASE_NS) +#define CCB_NS ((CCB_TypeDef *) CCB_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define I3C1_NS ((I3C_TypeDef *) I3C1_BASE_NS) +#define I3C2_NS ((I3C_TypeDef *) I3C2_BASE_NS) +#define HSP1_NS ((HSP_TypeDef *) HSP1_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define LCD_NS ((LCD_TypeDef *) LCD_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) +#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define TIM12_NS ((TIM_TypeDef *) TIM12_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define USB_DRD_FS_NS ((USB_DRD_TypeDef *) USB_DRD_BASE_NS) +#define USB_DRD_PMA_BUFF_NS ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) + +/*!< DBGMCU peripheral */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#if defined (CPU_IN_SECURE_STATE) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) +#define AES_S ((AES_TypeDef *) AES_BASE_S) +#define CCB_S ((CCB_TypeDef *) CCB_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define I3C1_S ((I3C_TypeDef *) I3C1_BASE_S) +#define I3C2_S ((I3C_TypeDef *) I3C2_BASE_S) +#define HSP1_S ((HSP_TypeDef *) HSP1_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define LCD_S ((LCD_TypeDef *) LCD_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) +#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define SAES_S ((AES_TypeDef *) SAES_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define TIM12_S ((TIM_TypeDef *) TIM12_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define USB_DRD_FS_S ((USB_DRD_TypeDef *) USB_DRD_BASE_S) +#define USB_DRD_PMA_BUFF_S ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define SRAM4_BASE SRAM4_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S +#define AES AES_S +#define AES_BASE AES_BASE_S +#define CCB CCB_S +#define CCB_BASE CCB_BASE_S +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S +#define COMP2 COMP2_S +#define COMP2_BASE COMP2_BASE_S +#define COMP12_COMMON COMP12_COMMON_S +#define COMP12_COMMON_BASE COMP12_BASE_S +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S +#define GTZC_MPCBB4 GTZC_MPCBB4_S +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S +#define I3C1 I3C1_S +#define I3C1_BASE I3C1_BASE_S +#define I3C2 I3C2_S +#define I3C2_BASE I3C2_BASE_S +#define HSP1 HSP1_S +#define HSP1_BASE HSP1_BASE_S +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S +#define LCD LCD_S +#define LCD_BASE LCD_BASE_S +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S +#define OPAMP1 OPAMP1_S +#define OPAMP1_BASE OPAMP1_BASE_S +#define OPAMP2 OPAMP2_S +#define OPAMP2_BASE OPAMP2_BASE_S +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S +#define TIM12 TIM12_S +#define TIM12_BASE TIM12_BASE_S +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S +#define USB_DRD_FS USB_DRD_FS_S +#define USB_DRD_BASE USB_DRD_BASE_S +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_S +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_S +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#else /* CPU_IN_SECURE_STATE */ +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM3_BASE SRAM3_BASE_NS +#define SRAM4_BASE SRAM4_BASE_NS + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS +#define AES AES_NS +#define AES_BASE AES_BASE_NS +#define CCB CCB_NS +#define CCB_BASE CCB_BASE_NS +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS +#define COMP12_COMMON COMP12_COMMON_NS +#define COMP12_COMMON_BASE COMP12_BASE_NS +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS +#define GTZC_MPCBB4 GTZC_MPCBB4_NS +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS +#define I3C1 I3C1_NS +#define I3C1_BASE I3C1_BASE_NS +#define I3C2 I3C2_NS +#define I3C2_BASE I3C2_BASE_NS +#define HSP1 HSP1_NS +#define HSP1_BASE HSP1_BASE_NS +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS +#define LCD LCD_NS +#define LCD_BASE LCD_BASE_NS +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS +#define OPAMP1 OPAMP1_NS +#define OPAMP1_BASE OPAMP1_BASE_NS +#define OPAMP2 OPAMP2_NS +#define OPAMP2_BASE OPAMP2_BASE_NS +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS +#define TIM12 TIM12_NS +#define TIM12_BASE TIM12_BASE_NS +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS +#define USB_DRD_FS USB_DRD_FS_NS +#define USB_DRD_BASE USB_DRD_BASE_NS +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_NS +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_NS +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS +#endif /* CPU_IN_SECURE_STATE */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 16000U /*!< LSI Maximum startup time in us : 4 cycles @ 250 Hz = 16 ms */ +/** + * @} + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ + +/* Specific device feature definitions */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0UL) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1UL) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2UL) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3UL) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4UL) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5UL) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6UL) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7UL) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8UL) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9UL) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10UL) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ +#define ADC_ISR_LDORDY_Pos (12UL) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC internal voltage regulator output ready flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0UL) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1UL) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2UL) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3UL) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4UL) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5UL) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6UL) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7UL) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8UL) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9UL) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10UL) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ +#define ADC_IER_LDORDYIE_Pos (12UL) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC internal voltage regulator interrupt*/ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0UL) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1UL) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2UL) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3UL) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4UL) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5UL) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28UL) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC internal voltage regulator */ +#define ADC_CR_DEEPPWD_Pos (29UL) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCAL_Pos (31UL) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register ******************/ +#define ADC_CFGR1_DMNGT_Pos (0UL) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC data management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2UL) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC_CFGR1_EXTSEL_Pos (5UL) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10UL) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12UL) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13UL) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_AUTDLY_Pos (14UL) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC low power auto wait */ + +#define ADC_CFGR1_DISCEN_Pos (16UL) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR1_DISCNUM_Pos (17UL) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20UL) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ + +#define ADC_CFGR1_JQM_Pos (21UL) +#define ADC_CFGR1_JQM_Msk (0x1UL << ADC_CFGR1_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_JQM ADC_CFGR1_JQM_Msk /*!< ADC group injected contexts queue mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22UL) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23UL) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR1_JAWD1EN_Pos (24UL) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR1_JAUTO_Pos (25UL) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26UL) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR1_JQDIS_Pos (31UL) +#define ADC_CFGR1_JQDIS_Msk (0x1UL << ADC_CFGR1_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR1_JQDIS ADC_CFGR1_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0UL) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1UL) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSS_Pos (5UL) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9UL) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10UL) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_BULB_Pos (13UL) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14UL) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15UL) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC sampling time control trigger mode */ + +#define ADC_CFGR2_OVSR_Pos (16UL) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_LFTRIG_Pos (27UL) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low-frequency trigge */ + +#define ADC_CFGR2_LSHIFT_Pos (28UL) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0UL) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3UL) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6UL) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9UL) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12UL) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15UL) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18UL) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21UL) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24UL) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27UL) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0UL) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3UL) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6UL) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9UL) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12UL) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15UL) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18UL) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21UL) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24UL) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27UL) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register *****************/ +#define ADC_PCSEL_PCSEL_Pos (0UL) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC channel preselection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0UL) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6UL) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12UL) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18UL) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24UL) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0UL) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6UL) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12UL) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18UL) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24UL) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0UL) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6UL) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12UL) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18UL) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24UL) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0UL) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6UL) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0UL) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_RDATA_0 (0x00000001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x00000002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x00000004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x00000008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x00000010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x00000020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x00000040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x00000080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x00000100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x00000200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x00000400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x00000800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x00001000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x00002000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x00004000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x00008000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_16 (0x00010000UL << ADC_DR_RDATA_Pos) /*!< 0x00010000 */ +#define ADC_DR_RDATA_17 (0x00020000UL << ADC_DR_RDATA_Pos) /*!< 0x00020000 */ +#define ADC_DR_RDATA_18 (0x00040000UL << ADC_DR_RDATA_Pos) /*!< 0x00040000 */ +#define ADC_DR_RDATA_19 (0x00080000UL << ADC_DR_RDATA_Pos) /*!< 0x00080000 */ +#define ADC_DR_RDATA_20 (0x00100000UL << ADC_DR_RDATA_Pos) /*!< 0x00100000 */ +#define ADC_DR_RDATA_21 (0x00200000UL << ADC_DR_RDATA_Pos) /*!< 0x00200000 */ +#define ADC_DR_RDATA_22 (0x00400000UL << ADC_DR_RDATA_Pos) /*!< 0x00400000 */ +#define ADC_DR_RDATA_23 (0x00800000UL << ADC_DR_RDATA_Pos) /*!< 0x00800000 */ +#define ADC_DR_RDATA_24 (0x01000000UL << ADC_DR_RDATA_Pos) /*!< 0x01000000 */ +#define ADC_DR_RDATA_25 (0x02000000UL << ADC_DR_RDATA_Pos) /*!< 0x02000000 */ +#define ADC_DR_RDATA_26 (0x04000000UL << ADC_DR_RDATA_Pos) /*!< 0x04000000 */ +#define ADC_DR_RDATA_27 (0x08000000UL << ADC_DR_RDATA_Pos) /*!< 0x08000000 */ +#define ADC_DR_RDATA_28 (0x10000000UL << ADC_DR_RDATA_Pos) /*!< 0x10000000 */ +#define ADC_DR_RDATA_29 (0x20000000UL << ADC_DR_RDATA_Pos) /*!< 0x20000000 */ +#define ADC_DR_RDATA_30 (0x40000000UL << ADC_DR_RDATA_Pos) /*!< 0x40000000 */ +#define ADC_DR_RDATA_31 (0x80000000UL << ADC_DR_RDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0UL) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2UL) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7UL) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9UL) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15UL) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21UL) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27UL) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR1 register ***************/ +#define ADC_OFCFGR1_POSOFF_Pos (24UL) +#define ADC_OFCFGR1_POSOFF_Msk (0x01UL << ADC_OFCFGR1_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR1_POSOFF ADC_OFCFGR1_POSOFF_Msk /*!< ADC offset instance 1 positive offset enable */ + +#define ADC_OFCFGR1_USAT_Pos (25UL) +#define ADC_OFCFGR1_USAT_Msk (0x01UL << ADC_OFCFGR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR1_USAT ADC_OFCFGR1_USAT_Msk /*!< ADC offset instance 1 unsigned saturation value */ + +#define ADC_OFCFGR1_SSAT_Pos (26UL) +#define ADC_OFCFGR1_SSAT_Msk (0x01UL << ADC_OFCFGR1_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR1_SSAT ADC_OFCFGR1_SSAT_Msk /*!< ADC offset instance 1 signed satuaration enable */ + +#define ADC_OFCFGR1_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR1_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR1_OFFSET_CH ADC_OFCFGR1_OFFSET_CH_Msk /*!< ADC offset instance 1 channel selection */ +#define ADC_OFCFGR1_OFFSET_CH_0 (0x01UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR1_OFFSET_CH_1 (0x02UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR1_OFFSET_CH_2 (0x03UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR1_OFFSET_CH_3 (0x04UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR1_OFFSET_CH_4 (0x05UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR2 register ***************/ +#define ADC_OFCFGR2_POSOFF_Pos (24UL) +#define ADC_OFCFGR2_POSOFF_Msk (0x01UL << ADC_OFCFGR2_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR2_POSOFF ADC_OFCFGR2_POSOFF_Msk /*!< ADC offset instance 2 positive offset enable */ + +#define ADC_OFCFGR2_USAT_Pos (25UL) +#define ADC_OFCFGR2_USAT_Msk (0x01UL << ADC_OFCFGR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR2_USAT ADC_OFCFGR2_USAT_Msk /*!< ADC offset instance 2 unsigned saturation value */ + +#define ADC_OFCFGR2_SSAT_Pos (26UL) +#define ADC_OFCFGR2_SSAT_Msk (0x01UL << ADC_OFCFGR2_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR2_SSAT ADC_OFCFGR2_SSAT_Msk /*!< ADC offset instance 2 signed satuaration enable */ + +#define ADC_OFCFGR2_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR2_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR2_OFFSET_CH ADC_OFCFGR2_OFFSET_CH_Msk /*!< ADC offset instance 2 channel selection */ +#define ADC_OFCFGR2_OFFSET_CH_0 (0x01UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR2_OFFSET_CH_1 (0x02UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR2_OFFSET_CH_2 (0x03UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR2_OFFSET_CH_3 (0x04UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR2_OFFSET_CH_4 (0x05UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR3 register ***************/ +#define ADC_OFCFGR3_POSOFF_Pos (24UL) +#define ADC_OFCFGR3_POSOFF_Msk (0x01UL << ADC_OFCFGR3_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR3_POSOFF ADC_OFCFGR3_POSOFF_Msk /*!< ADC offset instance 3 positive offset enable */ + +#define ADC_OFCFGR3_USAT_Pos (25UL) +#define ADC_OFCFGR3_USAT_Msk (0x01UL << ADC_OFCFGR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR3_USAT ADC_OFCFGR3_USAT_Msk /*!< ADC offset instance 3 unsigned saturation value */ + +#define ADC_OFCFGR3_SSAT_Pos (26UL) +#define ADC_OFCFGR3_SSAT_Msk (0x01UL << ADC_OFCFGR3_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR3_SSAT ADC_OFCFGR3_SSAT_Msk /*!< ADC offset instance 3 signed satuaration enable */ + +#define ADC_OFCFGR3_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR3_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR3_OFFSET_CH ADC_OFCFGR3_OFFSET_CH_Msk /*!< ADC offset instance 3 channel selection for the data offset */ +#define ADC_OFCFGR3_OFFSET_CH_0 (0x01UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR3_OFFSET_CH_1 (0x02UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR3_OFFSET_CH_2 (0x03UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR3_OFFSET_CH_3 (0x04UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR3_OFFSET_CH_4 (0x05UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR4 register ***************/ +#define ADC_OFCFGR4_POSOFF_Pos (24UL) +#define ADC_OFCFGR4_POSOFF_Msk (0x01UL << ADC_OFCFGR4_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR4_POSOFF ADC_OFCFGR4_POSOFF_Msk /*!< ADC offset instance 4 positive offset enable */ + +#define ADC_OFCFGR4_USAT_Pos (25UL) +#define ADC_OFCFGR4_USAT_Msk (0x01UL << ADC_OFCFGR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR4_USAT ADC_OFCFGR4_USAT_Msk /*!< ADC offset instance 4 unsigned saturation value */ + +#define ADC_OFCFGR4_SSAT_Pos (26UL) +#define ADC_OFCFGR4_SSAT_Msk (0x01UL << ADC_OFCFGR4_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR4_SSAT ADC_OFCFGR4_SSAT_Msk /*!< ADC offset instance 4 signed satuaration enable */ + +#define ADC_OFCFGR4_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR4_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR4_OFFSET_CH ADC_OFCFGR4_OFFSET_CH_Msk /*!< ADC offset instance 4 channel selection for the data offset */ +#define ADC_OFCFGR4_OFFSET_CH_0 (0x01UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR4_OFFSET_CH_1 (0x02UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR4_OFFSET_CH_2 (0x03UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR4_OFFSET_CH_3 (0x04UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR4_OFFSET_CH_4 (0x05UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET_Pos (0UL) +#define ADC_OFR1_OFFSET_Msk (0x03FFFFFUL << ADC_OFR1_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR1_OFFSET ADC_OFR1_OFFSET_Msk /*!< ADC offset instance 1 offset level */ +#define ADC_OFR1_OFFSET_0 (0x0000001UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET_1 (0x0000002UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET_2 (0x0000004UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET_3 (0x0000008UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET_4 (0x0000010UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET_5 (0x0000020UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET_6 (0x0000040UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET_7 (0x0000080UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET_8 (0x0000100UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET_9 (0x0000200UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET_10 (0x0000400UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET_11 (0x0000800UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET_12 (0x0001000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET_13 (0x0002000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET_14 (0x0004000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET_15 (0x0008000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET_16 (0x0010000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET_17 (0x0020000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET_18 (0x0040000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET_19 (0x0080000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET_20 (0x0100000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET_21 (0x0200000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET_Pos (0UL) +#define ADC_OFR2_OFFSET_Msk (0x03FFFFFUL << ADC_OFR2_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR2_OFFSET ADC_OFR2_OFFSET_Msk /*!< ADC offset instance 2 offset level */ +#define ADC_OFR2_OFFSET_0 (0x0000001UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET_1 (0x0000002UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET_2 (0x0000004UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET_3 (0x0000008UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET_4 (0x0000010UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET_5 (0x0000020UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET_6 (0x0000040UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET_7 (0x0000080UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET_8 (0x0000100UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET_9 (0x0000200UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET_10 (0x0000400UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET_11 (0x0000800UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET_12 (0x0001000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET_13 (0x0002000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET_14 (0x0004000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET_15 (0x0008000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET_16 (0x0010000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET_17 (0x0020000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET_18 (0x0040000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET_19 (0x0080000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET_20 (0x0100000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET_21 (0x0200000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET_Pos (0UL) +#define ADC_OFR3_OFFSET_Msk (0x03FFFFFUL << ADC_OFR3_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR3_OFFSET ADC_OFR3_OFFSET_Msk /*!< ADC offset instance 3 offset level */ +#define ADC_OFR3_OFFSET_0 (0x0000001UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET_1 (0x0000002UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET_2 (0x0000004UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET_3 (0x0000008UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET_4 (0x0000010UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET_5 (0x0000020UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET_6 (0x0000040UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET_7 (0x0000080UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET_8 (0x0000100UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET_9 (0x0000200UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET_10 (0x0000400UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET_11 (0x0000800UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET_12 (0x0001000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET_13 (0x0002000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET_14 (0x0004000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET_15 (0x0008000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET_16 (0x0010000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET_17 (0x0020000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET_18 (0x0040000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET_19 (0x0080000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET_20 (0x0100000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET_21 (0x0200000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET_Pos (0UL) +#define ADC_OFR4_OFFSET_Msk (0x03FFFFFUL << ADC_OFR4_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR4_OFFSET ADC_OFR4_OFFSET_Msk /*!< ADC offset instance 4 offset level */ +#define ADC_OFR4_OFFSET_0 (0x0000001UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET_1 (0x0000002UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET_2 (0x0000004UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET_3 (0x0000008UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET_4 (0x0000010UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET_5 (0x0000020UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET_6 (0x0000040UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET_7 (0x0000080UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET_8 (0x0000100UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET_9 (0x0000200UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET_10 (0x0000400UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET_11 (0x0000800UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET_12 (0x0001000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET_13 (0x0002000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET_14 (0x0004000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET_15 (0x0008000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET_16 (0x0010000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET_17 (0x0020000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET_18 (0x0040000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET_19 (0x0080000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET_20 (0x0100000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET_21 (0x0200000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_GCOMP register *****************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< Gain compensation coefficient */ +#define ADC_GCOMP_GCOMPCOEFF_0 (0x0001UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000001 */ +#define ADC_GCOMP_GCOMPCOEFF_1 (0x0002UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000002 */ +#define ADC_GCOMP_GCOMPCOEFF_2 (0x0004UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000004 */ +#define ADC_GCOMP_GCOMPCOEFF_3 (0x0008UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000008 */ +#define ADC_GCOMP_GCOMPCOEFF_4 (0x0010UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000010 */ +#define ADC_GCOMP_GCOMPCOEFF_5 (0x0020UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000020 */ +#define ADC_GCOMP_GCOMPCOEFF_6 (0x0040UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000040 */ +#define ADC_GCOMP_GCOMPCOEFF_7 (0x0080UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000080 */ +#define ADC_GCOMP_GCOMPCOEFF_8 (0x0100UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000100 */ +#define ADC_GCOMP_GCOMPCOEFF_9 (0x0200UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000200 */ +#define ADC_GCOMP_GCOMPCOEFF_10 (0x0400UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000400 */ +#define ADC_GCOMP_GCOMPCOEFF_11 (0x0800UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000800 */ +#define ADC_GCOMP_GCOMPCOEFF_12 (0x1000UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00001000 */ +#define ADC_GCOMP_GCOMPCOEFF_13 (0x2000UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00002000 */ + +#define ADC_GCOMP_GCOMP_Pos (31UL) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x80000000 */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< Gain compensation mode */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0UL) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0UL) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0UL) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0UL) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0UL) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0UL) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD1TR_LT register *************/ +#define ADC_AWD1LTR_LTR_Pos (0UL) +#define ADC_AWD1LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD1LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1LTR_LTR ADC_AWD1LTR_LTR_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1LTR_LTR_0 (0x000001UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1LTR_LTR_1 (0x000002UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1LTR_LTR_2 (0x000004UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1LTR_LTR_3 (0x000008UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1LTR_LTR_4 (0x000010UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1LTR_LTR_5 (0x000020UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1LTR_LTR_6 (0x000040UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1LTR_LTR_7 (0x000080UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1LTR_LTR_8 (0x000100UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1LTR_LTR_9 (0x000200UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1LTR_LTR_10 (0x000400UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1LTR_LTR_11 (0x000800UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1LTR_LTR_12 (0x001000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1LTR_LTR_13 (0x002000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1LTR_LTR_14 (0x004000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1LTR_LTR_15 (0x008000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1LTR_LTR_16 (0x010000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1LTR_LTR_17 (0x020000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1LTR_LTR_18 (0x040000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1LTR_LTR_19 (0x080000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1LTR_LTR_20 (0x100000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1LTR_LTR_21 (0x200000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1LTR_LTR_22 (0x400000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD1TR_HT register *******************/ +#define ADC_AWD1HTR_HTR_Pos (0UL) +#define ADC_AWD1HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD1HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1HTR_HTR ADC_AWD1HTR_HTR_Msk /*!< ADC analog watchdog 1 threshold high */ +#define ADC_AWD1HTR_HTR_0 (0x000001UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_HTR_1 (0x000002UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_HTR_2 (0x000004UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1HTR_HTR_3 (0x000008UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1HTR_HTR_4 (0x000010UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1HTR_HTR_5 (0x000020UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1HTR_HTR_6 (0x000040UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1HTR_HTR_7 (0x000080UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1HTR_HTR_8 (0x000100UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1HTR_HTR_9 (0x000200UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1HTR_HTR_10 (0x000400UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1HTR_HTR_11 (0x000800UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1HTR_HTR_12 (0x001000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1HTR_HTR_13 (0x002000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1HTR_HTR_14 (0x004000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1HTR_HTR_15 (0x008000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1HTR_HTR_16 (0x010000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1HTR_HTR_17 (0x020000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1HTR_HTR_18 (0x040000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1HTR_HTR_19 (0x080000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1HTR_HTR_20 (0x100000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1HTR_HTR_21 (0x200000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1HTR_HTR_22 (0x400000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00400000 */ + +#define ADC_AWD1HTR_AWDFILT_Pos (29UL) +#define ADC_AWD1HTR_AWDFILT_Msk (0x7UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000007 */ +#define ADC_AWD1HTR_AWDFILT ADC_AWD1HTR_AWDFILT_Msk /*!< ADC analog watchdog 1 filtering */ +#define ADC_AWD1HTR_AWDFILT_0 (0x000001UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_AWDFILT_1 (0x000002UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_AWDFILT_2 (0x000004UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000004 */ + +/******************** Bit definition for ADC_AWD2TR_LT register *******************/ +#define ADC_AWD2LTR_LTR_Pos (0UL) +#define ADC_AWD2LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD2LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2LTR_LTR ADC_AWD2LTR_LTR_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2LTR_LTR_0 (0x000001UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2LTR_LTR_1 (0x000002UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2LTR_LTR_2 (0x000004UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2LTR_LTR_3 (0x000008UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2LTR_LTR_4 (0x000010UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2LTR_LTR_5 (0x000020UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2LTR_LTR_6 (0x000040UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2LTR_LTR_7 (0x000080UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2LTR_LTR_8 (0x000100UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2LTR_LTR_9 (0x000200UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2LTR_LTR_10 (0x000400UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2LTR_LTR_11 (0x000800UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2LTR_LTR_12 (0x001000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2LTR_LTR_13 (0x002000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2LTR_LTR_14 (0x004000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2LTR_LTR_15 (0x008000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2LTR_LTR_16 (0x010000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2LTR_LTR_17 (0x020000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2LTR_LTR_18 (0x040000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2LTR_LTR_19 (0x080000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2LTR_LTR_20 (0x100000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2LTR_LTR_21 (0x200000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2LTR_LTR_22 (0x400000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD2TR_HT register *******************/ +#define ADC_AWD2HTR_HTR_Pos (0UL) +#define ADC_AWD2HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD2HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2HTR_HTR ADC_AWD2HTR_HTR_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2HTR_HTR_0 (0x000001UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2HTR_HTR_1 (0x000002UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2HTR_HTR_2 (0x000004UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2HTR_HTR_3 (0x000008UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2HTR_HTR_4 (0x000010UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2HTR_HTR_5 (0x000020UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2HTR_HTR_6 (0x000040UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2HTR_HTR_7 (0x000080UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2HTR_HTR_8 (0x000100UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2HTR_HTR_9 (0x000200UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2HTR_HTR_10 (0x000400UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2HTR_HTR_11 (0x000800UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2HTR_HTR_12 (0x001000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2HTR_HTR_13 (0x002000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2HTR_HTR_14 (0x004000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2HTR_HTR_15 (0x008000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2HTR_HTR_16 (0x010000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2HTR_HTR_17 (0x020000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2HTR_HTR_18 (0x040000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2HTR_HTR_19 (0x080000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2HTR_HTR_20 (0x100000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2HTR_HTR_21 (0x200000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2HTR_HTR_22 (0x400000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD3TR_LT register *******************/ +#define ADC_AWD3LTR_LTR_Pos (0UL) +#define ADC_AWD3LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD3LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3LTR_LTR ADC_AWD3LTR_LTR_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3LTR_LTR_0 (0x000001UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3LTR_LTR_1 (0x000002UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3LTR_LTR_2 (0x000004UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3LTR_LTR_3 (0x000008UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3LTR_LTR_4 (0x000010UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3LTR_LTR_5 (0x000020UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3LTR_LTR_6 (0x000040UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3LTR_LTR_7 (0x000080UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3LTR_LTR_8 (0x000100UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3LTR_LTR_9 (0x000200UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3LTR_LTR_10 (0x000400UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3LTR_LTR_11 (0x000800UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3LTR_LTR_12 (0x001000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3LTR_LTR_13 (0x002000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3LTR_LTR_14 (0x004000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3LTR_LTR_15 (0x008000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3LTR_LTR_16 (0x010000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3LTR_LTR_17 (0x020000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3LTR_LTR_18 (0x040000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3LTR_LTR_19 (0x080000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3LTR_LTR_20 (0x100000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3LTR_LTR_21 (0x200000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3LTR_LTR_22 (0x400000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD3TR_HT register *******************/ +#define ADC_AWD3HTR_HTR_Pos (0UL) +#define ADC_AWD3HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD3HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3HTR_HTR ADC_AWD3HTR_HTR_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3HTR_HTR_0 (0x000001UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3HTR_HTR_1 (0x000002UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3HTR_HTR_2 (0x000004UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3HTR_HTR_3 (0x000008UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3HTR_HTR_4 (0x000010UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3HTR_HTR_5 (0x000020UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3HTR_HTR_6 (0x000040UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3HTR_HTR_7 (0x000080UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3HTR_HTR_8 (0x000100UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3HTR_HTR_9 (0x000200UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3HTR_HTR_10 (0x000400UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3HTR_HTR_11 (0x000800UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3HTR_HTR_12 (0x001000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3HTR_HTR_13 (0x002000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3HTR_HTR_14 (0x004000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3HTR_HTR_15 (0x008000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3HTR_HTR_16 (0x010000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3HTR_HTR_17 (0x020000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3HTR_HTR_18 (0x040000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3HTR_HTR_19 (0x080000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3HTR_HTR_20 (0x100000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3HTR_HTR_21 (0x200000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3HTR_HTR_22 (0x400000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ + +#define ADC_CALFACT_CALFACT_Pos (0UL) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_7 (0x80UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT_CALFACT_8 (0x100UL<< ADC_CALFACT_CALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_CALFACT_9 (0x200UL<< ADC_CALFACT_CALFACT_Pos) /*!< 0x00000200 */ + + +/******************** Bit definition for ADC_OR option register ***************/ +#define ADC_OR_VDDCOREEN_Pos (0UL) +#define ADC_OR_VDDCOREEN_Msk (0x1UL << ADC_OR_VDDCOREEN_Pos) /*!< 0x00000004 */ +#define ADC_OR_VDDCOREEN ADC_OR_VDDCOREEN_Msk /*!< ADC internal path to VDDCORE */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0UL) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1UL) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2UL) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3UL) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4UL) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5UL) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6UL) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7UL) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8UL) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9UL) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10UL) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ +#define ADC_CSR_LDORDY_MST_Pos (12UL) +#define ADC_CSR_LDORDY_MST_Msk (0x1UL << ADC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADC_CSR_LDORDY_MST ADC_CSR_LDORDY_MST_Msk /*!< ADC multimode master internal voltage regulator output ready flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16UL) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17UL) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18UL) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19UL) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20UL) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21UL) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22UL) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23UL) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24UL) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25UL) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26UL) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ +#define ADC_CSR_LDORDY_SLV_Pos (28UL) +#define ADC_CSR_LDORDY_SLV_Msk (0x1UL << ADC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CSR_LDORDY_SLV ADC_CSR_LDORDY_SLV_Msk /*!< ADC multimode slave internal voltage regulator output ready flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0UL) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8UL) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DAMDF_Pos (14UL) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< ADC multimode data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_PRESC_Pos (18UL) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22UL) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ + +#define ADC_CCR_TSEN_Pos (23UL) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to Temperature sensor voltage enable */ + +#define ADC_CCR_VBATEN_Pos (24UL) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0UL) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16UL) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0UL) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< ADC multimode master or slave (alternated) group regular conversion data */ + +/******************************************************************************/ +/* */ +/* Advanced Encryption Standard (AES) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AES_CR register *********************/ +#define AES_CR_EN_Pos (0UL) +#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ +#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ +#define AES_CR_DATATYPE_Pos (1UL) +#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ +#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ +#define AES_CR_MODE_Pos (3UL) +#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ +#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ +#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ +#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ +#define AES_CR_CHMOD_Pos (5UL) +#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ +#define AES_CR_DMAINEN_Pos (11UL) +#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define AES_CR_DMAOUTEN_Pos (12UL) +#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ +#define AES_CR_GCMPH_Pos (13UL) +#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ +#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ +#define AES_CR_KEYSIZE_Pos (18UL) +#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ +#define AES_CR_KEYPROT_Pos (19UL) +#define AES_CR_KEYPROT_Msk (0x1UL << AES_CR_KEYPROT_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYPROT AES_CR_KEYPROT_Msk /*!< Key protection */ +#define AES_CR_NPBLB_Pos (20UL) +#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */ +#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ +#define AES_CR_KMOD_Pos (24UL) +#define AES_CR_KMOD_Msk (0x3UL << AES_CR_KMOD_Pos) /*!< 0x03000000 */ +#define AES_CR_KMOD AES_CR_KMOD_Msk /*!< Key mode selection */ +#define AES_CR_KMOD_0 (0x1UL << AES_CR_KMOD_Pos) /*!< 0x01000000 */ +#define AES_CR_KMOD_1 (0x2UL << AES_CR_KMOD_Pos) /*!< 0x02000000 */ +#define AES_CR_KSHAREID_Pos (26UL) +#define AES_CR_KSHAREID_Msk (0x3UL << AES_CR_KSHAREID_Pos) /*!< 0x0C000000 */ +#define AES_CR_KSHAREID AES_CR_KSHAREID_Msk /*!< Key Shared ID */ +#define AES_CR_KEYSEL_Pos (28UL) +#define AES_CR_KEYSEL_Msk (0x7UL << AES_CR_KEYSEL_Pos) /*!< 0x70000000 */ +#define AES_CR_KEYSEL AES_CR_KEYSEL_Msk /*!< Key Selection */ +#define AES_CR_KEYSEL_0 (0x1UL << AES_CR_KEYSEL_Pos) /*!< 0x10000000 */ +#define AES_CR_KEYSEL_1 (0x2UL << AES_CR_KEYSEL_Pos) /*!< 0x20000000 */ +#define AES_CR_KEYSEL_2 (0x4UL << AES_CR_KEYSEL_Pos) /*!< 0x40000000 */ +#define AES_CR_IPRST_Pos (31UL) +#define AES_CR_IPRST_Msk (0x1UL << AES_CR_IPRST_Pos) /*!< 0x80000000 */ +#define AES_CR_IPRST AES_CR_IPRST_Msk /*!< AES IP software reset */ + +/******************* Bit definition for AES_SR register *********************/ +#define AES_SR_CCF_Pos (0UL) +#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ +#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define AES_SR_RDERR_Pos (1UL) +#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ +#define AES_SR_WRERR_Pos (2UL) +#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ +#define AES_SR_BUSY_Pos (3UL) +#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ +#define AES_SR_KEYVALID_Pos (7UL) +#define AES_SR_KEYVALID_Msk (0x1UL << AES_SR_KEYVALID_Pos) /*!< 0x00000080 */ +#define AES_SR_KEYVALID AES_SR_KEYVALID_Msk /*!< KEYVALID Flag */ + +/******************* Bit definition for AES_DINR register *******************/ +#define AES_DINR_Pos (0UL) +#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ + +/******************* Bit definition for AES_DOUTR register ******************/ +#define AES_DOUTR_Pos (0UL) +#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ + +/******************* Bit definition for AES_KEYR0 register ******************/ +#define AES_KEYR0_Pos (0UL) +#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ + +/******************* Bit definition for AES_KEYR1 register ******************/ +#define AES_KEYR1_Pos (0UL) +#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ + +/******************* Bit definition for AES_KEYR2 register ******************/ +#define AES_KEYR2_Pos (0UL) +#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ + +/******************* Bit definition for AES_KEYR3 register ******************/ +#define AES_KEYR3_Pos (0UL) +#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ + +/******************* Bit definition for AES_KEYR4 register ******************/ +#define AES_KEYR4_Pos (0UL) +#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ + +/******************* Bit definition for AES_KEYR5 register ******************/ +#define AES_KEYR5_Pos (0UL) +#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ + +/******************* Bit definition for AES_KEYR6 register ******************/ +#define AES_KEYR6_Pos (0UL) +#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ + +/******************* Bit definition for AES_KEYR7 register ******************/ +#define AES_KEYR7_Pos (0UL) +#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ + +/******************* Bit definition for AES_IVR0 register ******************/ +#define AES_IVR0_Pos (0UL) +#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ + +/******************* Bit definition for AES_IVR1 register ******************/ +#define AES_IVR1_Pos (0UL) +#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ + +/******************* Bit definition for AES_IVR2 register ******************/ +#define AES_IVR2_Pos (0UL) +#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ + +/******************* Bit definition for AES_IVR3 register ******************/ +#define AES_IVR3_Pos (0UL) +#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ + +/******************* Bit definition for AES_SUSP0R register ******************/ +#define AES_SUSP0R_Pos (0UL) +#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ + +/******************* Bit definition for AES_SUSP1R register ******************/ +#define AES_SUSP1R_Pos (0UL) +#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ + +/******************* Bit definition for AES_SUSP2R register ******************/ +#define AES_SUSP2R_Pos (0UL) +#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ + +/******************* Bit definition for AES_SUSP3R register ******************/ +#define AES_SUSP3R_Pos (0UL) +#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ + +/******************* Bit definition for AES_SUSP4R register ******************/ +#define AES_SUSP4R_Pos (0UL) +#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ + +/******************* Bit definition for AES_SUSP5R register ******************/ +#define AES_SUSP5R_Pos (0UL) +#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for AES_SUSP6R register ******************/ +#define AES_SUSP6R_Pos (0UL) +#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ + +/******************* Bit definition for AES_SUSP7R register ******************/ +#define AES_SUSP7R_Pos (0UL) +#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ + +/******************* Bit definition for AES_IER register ******************/ +#define AES_IER_CCFIE_Pos (0UL) +#define AES_IER_CCFIE_Msk (0x1UL << AES_IER_CCFIE_Pos) /*!< 0x00000001 */ +#define AES_IER_CCFIE AES_IER_CCFIE_Msk /*!< Computation complete flag interrupt enable */ +#define AES_IER_RWEIE_Pos (1UL) +#define AES_IER_RWEIE_Msk (0x1UL << AES_IER_RWEIE_Pos) /*!< 0x00000002 */ +#define AES_IER_RWEIE AES_IER_RWEIE_Msk /*!< Read or write error Interrupt Enable */ +#define AES_IER_KEIE_Pos (2UL) +#define AES_IER_KEIE_Msk (0x1UL << AES_IER_KEIE_Pos) /*!< 0x00000004 */ +#define AES_IER_KEIE AES_IER_KEIE_Msk /*!< Key error interrupt enable */ +#define AES_IER_RNGEIE_Pos (3UL) +#define AES_IER_RNGEIE_Msk (0x1UL << AES_IER_RNGEIE_Pos) /*!< 0x00000008 */ +#define AES_IER_RNGEIE AES_IER_RNGEIE_Msk /*!< Rng error interrupt enable */ + +/******************* Bit definition for AES_ISR register ******************/ +#define AES_ISR_CCF_Pos (0UL) +#define AES_ISR_CCF_Msk (0x1UL << AES_ISR_CCF_Pos) /*!< 0x00000001 */ +#define AES_ISR_CCF AES_ISR_CCF_Msk /*!< Computation complete flag */ +#define AES_ISR_RWEIF_Pos (1UL) +#define AES_ISR_RWEIF_Msk (0x1UL << AES_ISR_RWEIF_Pos) /*!< 0x00000002 */ +#define AES_ISR_RWEIF AES_ISR_RWEIF_Msk /*!< Read or write error Interrupt flag */ +#define AES_ISR_KEIF_Pos (2UL) +#define AES_ISR_KEIF_Msk (0x1UL << AES_ISR_KEIF_Pos) /*!< 0x00000004 */ +#define AES_ISR_KEIF AES_ISR_KEIF_Msk /*!< Key error interrupt flag */ +#define AES_ISR_RNGEIF_Pos (3UL) +#define AES_ISR_RNGEIF_Msk (0x1UL << AES_ISR_RNGEIF_Pos) /*!< 0x00000008 */ +#define AES_ISR_RNGEIF AES_ISR_RNGEIF_Msk /*!< Rng error interrupt flag */ + +/******************* Bit definition for AES_ICR register ******************/ +#define AES_ICR_CCF_Pos (0UL) +#define AES_ICR_CCF_Msk (0x1UL << AES_ICR_CCF_Pos) /*!< 0x00000001 */ +#define AES_ICR_CCF AES_ICR_CCF_Msk /*!< Computation complete flag clear */ +#define AES_ICR_RWEIF_Pos (1UL) +#define AES_ICR_RWEIF_Msk (0x1UL << AES_ICR_RWEIF_Pos) /*!< 0x00000002 */ +#define AES_ICR_RWEIF AES_ICR_RWEIF_Msk /*!< Read or write error Interrupt flag clear */ +#define AES_ICR_KEIF_Pos (2UL) +#define AES_ICR_KEIF_Msk (0x1UL << AES_ICR_KEIF_Pos) /*!< 0x00000004 */ +#define AES_ICR_KEIF AES_ICR_KEIF_Msk /*!< Key error interrupt flag clear */ +#define AES_ICR_RNGEIF_Pos (3UL) +#define AES_ICR_RNGEIF_Msk (0x1UL << AES_ICR_RNGEIF_Pos) /*!< 0x00000008 */ +#define AES_ICR_RNGEIF AES_ICR_RNGEIF_Msk /*!< Rng error interrupt flag clear */ + +/******************************************************************************/ +/* */ +/* Coupling and chaining bridge (CCB) */ +/* */ +/******************************************************************************/ + +/* Specific device feature definitions */ +#define SW_SANITY_CHECK_SUPPORT /*!< CCB feature available only on specific devices: SW Sanity check is available on U3 1M devices */ + +/******************* Bit definition for CCB_CR register ******************/ +#define CCB_CR_CCOP_Pos (0UL) +#define CCB_CR_CCOP_Msk (0xFFUL << CCB_CR_CCOP_Pos) /*!< 0x000000FF */ +#define CCB_CR_CCOP CCB_CR_CCOP_Msk /*!< Coupling and chaining operation */ +#define CCB_CR_IPRST_Pos (31UL) +#define CCB_CR_IPRST_Msk (0x1UL << CCB_CR_IPRST_Pos) /*!< 0x80000000 */ +#define CCB_CR_IPRST CCB_CR_IPRST_Msk /*!< CCB reset */ + +/******************* Bit definition for CCB_SR register ******************/ +#define CCB_SR_OPSTEP_Pos (0UL) +#define CCB_SR_OPSTEP_Msk (0x1FUL << CCB_SR_OPSTEP_Pos) /*!< 0x0000001F */ +#define CCB_SR_OPSTEP CCB_SR_OPSTEP_Msk /*!< Operation step */ +#define CCB_SR_OPERR_Pos (8UL) +#define CCB_SR_OPERR_Msk (0x1FUL << CCB_SR_OPERR_Pos) /*!< 0x00001F00 */ +#define CCB_SR_OPERR CCB_SR_OPERR_Msk /*!< Operation error */ +#define CCB_SR_BUSY_Pos (16UL) +#define CCB_SR_BUSY_Msk (0x1UL << CCB_SR_BUSY_Pos) /*!< 0x00010000 */ +#define CCB_SR_BUSY CCB_SR_BUSY_Msk /*!< CCB busy */ +#define CCB_SR_TAMP_EVT0_Pos (24UL) +#define CCB_SR_TAMP_EVT0_Msk (0x1UL << CCB_SR_TAMP_EVT0_Pos) /*!< 0x01000000 */ +#define CCB_SR_TAMP_EVT0 CCB_SR_TAMP_EVT0_Msk /*!< Tamper event 0 flag */ +#define CCB_SR_TAMP_EVT1_Pos (25UL) +#define CCB_SR_TAMP_EVT1_Msk (0x1UL << CCB_SR_TAMP_EVT1_Pos) /*!< 0x02000000 */ +#define CCB_SR_TAMP_EVT1 CCB_SR_TAMP_EVT1_Msk /*!< Tamper event 1 flag */ +#define CCB_SR_TAMP_EVT2_Pos (26UL) +#define CCB_SR_TAMP_EVT2_Msk (0x1UL << CCB_SR_TAMP_EVT2_Pos) /*!< 0x04000000 */ +#define CCB_SR_TAMP_EVT2 CCB_SR_TAMP_EVT2_Msk /*!< Tamper event 2 flag */ +#define CCB_SR_TAMP_EVT3_Pos (27UL) +#define CCB_SR_TAMP_EVT3_Msk (0x1UL << CCB_SR_TAMP_EVT3_Pos) /*!< 0x08000000 */ +#define CCB_SR_TAMP_EVT3 CCB_SR_TAMP_EVT3_Msk /*!< Tamper event 3 flag */ +#define CCB_SR_TAMP_EVT4_Pos (28UL) +#define CCB_SR_TAMP_EVT4_Msk (0x1UL << CCB_SR_TAMP_EVT4_Pos) /*!< 0x10000000 */ +#define CCB_SR_TAMP_EVT4 CCB_SR_TAMP_EVT4_Msk /*!< Tamper event 4 flag */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0UL) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0UL) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0UL) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3UL) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5UL) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7UL) +#define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ +#define CRC_CR_RTYPE_IN_Pos (9UL) +#define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ +#define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< RTYPE_IN Reverse Type Input bit */ +#define CRC_CR_RTYPE_OUT_Pos (10UL) +#define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ +#define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< RTYPE_OUT Reverse Type Output bit */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0UL) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0UL) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0UL) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1UL) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2UL) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3UL) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5UL) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6UL) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7UL) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8UL) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0UL) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16UL) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24UL) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28UL) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31UL) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0UL) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1UL) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2UL) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3UL) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8UL) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9UL) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10UL) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15UL) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16UL) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0UL) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1UL) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2UL) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3UL) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ +/*!< ****************** Bit definition for COMPx_CSR register ********************/ +#define COMP_CSR_EN_Pos (0UL) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< COMPx enable bit */ +#define COMP_CSR_INMSEL_Pos (4UL) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00070000 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< COMPx input minus selection bit */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00010000 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00020000 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00040000 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00080000 */ +#define COMP_CSR_INPSEL_Pos (8UL) +#define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00100000 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< COMPx input plus selection bit */ +#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) +#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) +#define COMP_CSR_WINMODE_Pos (11UL) +#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000010 */ +#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< COMPx Windows mode selection bit */ +#define COMP_CSR_WINOUT_Pos (14UL) +#define COMP_CSR_WINOUT_Msk (0x1UL << COMP_CSR_WINOUT_Pos) /*!< 0x00000008 */ +#define COMP_CSR_WINOUT COMP_CSR_WINOUT_Msk /*!< COMPx polarity selection bit */ +#define COMP_CSR_POLARITY_Pos (15UL) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00000008 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< COMPx polarity selection bit */ +#define COMP_CSR_HYST_Pos (16UL) +#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00000300 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< COMPx hysteresis selection bits */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00000100 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00000200 */ +#define COMP_CSR_PWRMODE_Pos (18UL) +#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00003000 */ +#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< COMPx Power Mode of the comparator */ +#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00001000 */ +#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00002000 */ +#define COMP_CSR_BLANKSEL_Pos (20UL) +#define COMP_CSR_BLANKSEL_Msk (0x1FUL << COMP_CSR_BLANKSEL_Pos) /*!< 0x0F000000 */ +#define COMP_CSR_BLANKSEL COMP_CSR_BLANKSEL_Msk /*!< COMPx blanking source selection bits */ +#define COMP_CSR_BLANKSEL_0 (0x1UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ +#define COMP_CSR_BLANKSEL_1 (0x2UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x02000000 */ +#define COMP_CSR_BLANKSEL_2 (0x4UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x04000000 */ +#define COMP_CSR_BLANKSEL_3 (0x8UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x08000000 */ +#define COMP_CSR_BLANKSEL_4 (0x10UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ +#define COMP2_CSR_BLANKSEL_2 COMP_CSR_BLANKSEL_2 /*!< COMP2 blanking source selection bit 2 */ +#define COMP_CSR_VALUE_Pos (30UL) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x00000001 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< COMPx enable bit */ +#define COMP_CSR_LOCK_Pos (31UL) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< COMPx Lock Bit */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0UL) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14UL) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16UL) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30UL) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!(1)) */ + +#define HSP_ITFENR_TRGOEN_Pos (12UL) +#define HSP_ITFENR_TRGOEN_Msk (0x1UL << HSP_ITFENR_TRGOEN_Pos) /*!< 0x00001000 */ +#define HSP_ITFENR_TRGOEN HSP_ITFENR_TRGOEN_Msk /*!< TRGOEN (TRGO enable bit (1)) */ + +#define HSP_ITFENR_TRGI0EN_Pos (16UL) +#define HSP_ITFENR_TRGI0EN_Msk (0x1UL << HSP_ITFENR_TRGI0EN_Pos) /*!< 0x00010000 */ +#define HSP_ITFENR_TRGI0EN HSP_ITFENR_TRGI0EN_Msk /*!< TRGI0EN (TRGIN0 enable bit (1)) */ + +#define HSP_ITFENR_TRGI1EN_Pos (17UL) +#define HSP_ITFENR_TRGI1EN_Msk (0x1UL << HSP_ITFENR_TRGI1EN_Pos) /*!< 0x00020000 */ +#define HSP_ITFENR_TRGI1EN HSP_ITFENR_TRGI1EN_Msk /*!< TRGI1EN (TRGIN1 enable bit (1)) */ + +#define HSP_ITFENR_TRGI2EN_Pos (18UL) +#define HSP_ITFENR_TRGI2EN_Msk (0x1UL << HSP_ITFENR_TRGI2EN_Pos) /*!< 0x00040000 */ +#define HSP_ITFENR_TRGI2EN HSP_ITFENR_TRGI2EN_Msk /*!< TRGI2EN (TRGIN2 enable bit (1)) */ + +#define HSP_ITFENR_TRGI3EN_Pos (19UL) +#define HSP_ITFENR_TRGI3EN_Msk (0x1UL << HSP_ITFENR_TRGI3EN_Pos) /*!< 0x00080000 */ +#define HSP_ITFENR_TRGI3EN HSP_ITFENR_TRGI3EN_Msk /*!< TRGI3EN (TRGIN3 enable bit (1)) */ + +#define HSP_ITFENR_TRGI4EN_Pos (20UL) +#define HSP_ITFENR_TRGI4EN_Msk (0x1UL << HSP_ITFENR_TRGI4EN_Pos) /*!< 0x00100000 */ +#define HSP_ITFENR_TRGI4EN HSP_ITFENR_TRGI4EN_Msk /*!< TRGI4EN (TRGIN4 enable bit (1)) */ + +#define HSP_ITFENR_TRGI5EN_Pos (21UL) +#define HSP_ITFENR_TRGI5EN_Msk (0x1UL << HSP_ITFENR_TRGI5EN_Pos) /*!< 0x00200000 */ +#define HSP_ITFENR_TRGI5EN HSP_ITFENR_TRGI5EN_Msk /*!< TRGI5EN (TRGIN5 enable bit (1)) */ + +#define HSP_ITFENR_TRGI6EN_Pos (22UL) +#define HSP_ITFENR_TRGI6EN_Msk (0x1UL << HSP_ITFENR_TRGI6EN_Pos) /*!< 0x00400000 */ +#define HSP_ITFENR_TRGI6EN HSP_ITFENR_TRGI6EN_Msk /*!< TRGI6EN (TRGIN6 enable bit (1)) */ + +#define HSP_ITFENR_TRGI7EN_Pos (23UL) +#define HSP_ITFENR_TRGI7EN_Msk (0x1UL << HSP_ITFENR_TRGI7EN_Pos) /*!< 0x00800000 */ +#define HSP_ITFENR_TRGI7EN HSP_ITFENR_TRGI7EN_Msk /*!< TRGI7EN (TRGIN7 enable bit (1)) */ + +#define HSP_ITFENR_TRGI8EN_Pos (24UL) +#define HSP_ITFENR_TRGI8EN_Msk (0x1UL << HSP_ITFENR_TRGI8EN_Pos) /*!< 0x01000000 */ +#define HSP_ITFENR_TRGI8EN HSP_ITFENR_TRGI8EN_Msk /*!< TRGI8EN (TRGIN8 enable bit (1)) */ + +#define HSP_ITFENR_TRGI9EN_Pos (25UL) +#define HSP_ITFENR_TRGI9EN_Msk (0x1UL << HSP_ITFENR_TRGI9EN_Pos) /*!< 0x02000000 */ +#define HSP_ITFENR_TRGI9EN HSP_ITFENR_TRGI9EN_Msk /*!< TRGI9EN (TRGIN9 enable bit (1)) */ + +#define HSP_ITFENR_DCMDDIS_Pos (27UL) +#define HSP_ITFENR_DCMDDIS_Msk (0x1UL << HSP_ITFENR_DCMDDIS_Pos) /*!< 0x08000000 */ +#define HSP_ITFENR_DCMDDIS HSP_ITFENR_DCMDDIS_Msk /*!< DCMDDIS (Direct command interface disable bit ) */ + +#define HSP_ITFENR_CSEGEN_Pos (28UL) +#define HSP_ITFENR_CSEGEN_Msk (0x1UL << HSP_ITFENR_CSEGEN_Pos) /*!< 0x10000000 */ +#define HSP_ITFENR_CSEGEN HSP_ITFENR_CSEGEN_Msk /*!< CSEGEN (CSEG interface enable bit (1)) */ + +#define HSP_ITFENR_CDEGEN_Pos (29UL) +#define HSP_ITFENR_CDEGEN_Msk (0x1UL << HSP_ITFENR_CDEGEN_Pos) /*!< 0x20000000 */ +#define HSP_ITFENR_CDEGEN HSP_ITFENR_CDEGEN_Msk /*!< CDEGEN (CDEG interface enable bit ) */ + +#define HSP_ITFENR_HSEGEN_Pos (30UL) +#define HSP_ITFENR_HSEGEN_Msk (0x1UL << HSP_ITFENR_HSEGEN_Pos) /*!< 0x40000000 */ +#define HSP_ITFENR_HSEGEN HSP_ITFENR_HSEGEN_Msk /*!< HSEGEN (HSEG interface enable bit ) */ + +#define HSP_ITFENR_HDEGEN_Pos (31UL) +#define HSP_ITFENR_HDEGEN_Msk (0x1UL << HSP_ITFENR_HDEGEN_Pos) /*!< 0x80000000 */ +#define HSP_ITFENR_HDEGEN HSP_ITFENR_HDEGEN_Msk /*!< HDEGEN (HDEG interface enable bit ) */ + +/******************** Bit definition for HSP_EVTSRC0R register ********************/ +#define HSP_EVTSRC0R_EVT1SRC_Pos (0UL) +#define HSP_EVTSRC0R_EVT1SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT1SRC_Pos) /*!< 0x00000007 */ +#define HSP_EVTSRC0R_EVT1SRC HSP_EVTSRC0R_EVT1SRC_Msk /*!< EVT1SRC[2:0] bits (Event source selection for priority encoder input 1) */ +#define HSP_EVTSRC0R_EVT1SRC_0 (0x1UL << HSP_EVTSRC0R_EVT1SRC_Pos) /*!< 0x00000001 */ +#define HSP_EVTSRC0R_EVT1SRC_1 (0x2UL << HSP_EVTSRC0R_EVT1SRC_Pos) /*!< 0x00000002 */ +#define HSP_EVTSRC0R_EVT1SRC_2 (0x4UL << HSP_EVTSRC0R_EVT1SRC_Pos) /*!< 0x00000004 */ + +#define HSP_EVTSRC0R_EVT2SRC_Pos (4UL) +#define HSP_EVTSRC0R_EVT2SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT2SRC_Pos) /*!< 0x00000070 */ +#define HSP_EVTSRC0R_EVT2SRC HSP_EVTSRC0R_EVT2SRC_Msk /*!< EVT2SRC[2:0] bits (Event source selection for priority encoder input 2) */ +#define HSP_EVTSRC0R_EVT2SRC_0 (0x1UL << HSP_EVTSRC0R_EVT2SRC_Pos) /*!< 0x00000010 */ +#define HSP_EVTSRC0R_EVT2SRC_1 (0x2UL << HSP_EVTSRC0R_EVT2SRC_Pos) /*!< 0x00000020 */ +#define HSP_EVTSRC0R_EVT2SRC_2 (0x4UL << HSP_EVTSRC0R_EVT2SRC_Pos) /*!< 0x00000040 */ + +#define HSP_EVTSRC0R_EVT3SRC_Pos (8UL) +#define HSP_EVTSRC0R_EVT3SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT3SRC_Pos) /*!< 0x00000700 */ +#define HSP_EVTSRC0R_EVT3SRC HSP_EVTSRC0R_EVT3SRC_Msk /*!< EVT3SRC[2:0] bits (Event source selection for priority encoder input 3) */ +#define HSP_EVTSRC0R_EVT3SRC_0 (0x1UL << HSP_EVTSRC0R_EVT3SRC_Pos) /*!< 0x00000100 */ +#define HSP_EVTSRC0R_EVT3SRC_1 (0x2UL << HSP_EVTSRC0R_EVT3SRC_Pos) /*!< 0x00000200 */ +#define HSP_EVTSRC0R_EVT3SRC_2 (0x4UL << HSP_EVTSRC0R_EVT3SRC_Pos) /*!< 0x00000400 */ + +#define HSP_EVTSRC0R_EVT4SRC_Pos (12UL) +#define HSP_EVTSRC0R_EVT4SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT4SRC_Pos) /*!< 0x00007000 */ +#define HSP_EVTSRC0R_EVT4SRC HSP_EVTSRC0R_EVT4SRC_Msk /*!< EVT4SRC[2:0] bits (Event source selection for priority encoder input 4) */ +#define HSP_EVTSRC0R_EVT4SRC_0 (0x1UL << HSP_EVTSRC0R_EVT4SRC_Pos) /*!< 0x00001000 */ +#define HSP_EVTSRC0R_EVT4SRC_1 (0x2UL << HSP_EVTSRC0R_EVT4SRC_Pos) /*!< 0x00002000 */ +#define HSP_EVTSRC0R_EVT4SRC_2 (0x4UL << HSP_EVTSRC0R_EVT4SRC_Pos) /*!< 0x00004000 */ + +#define HSP_EVTSRC0R_EVT5SRC_Pos (16UL) +#define HSP_EVTSRC0R_EVT5SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT5SRC_Pos) /*!< 0x00070000 */ +#define HSP_EVTSRC0R_EVT5SRC HSP_EVTSRC0R_EVT5SRC_Msk /*!< EVT5SRC[2:0] bits (Event source selection for priority encoder input 5) */ +#define HSP_EVTSRC0R_EVT5SRC_0 (0x1UL << HSP_EVTSRC0R_EVT5SRC_Pos) /*!< 0x00010000 */ +#define HSP_EVTSRC0R_EVT5SRC_1 (0x2UL << HSP_EVTSRC0R_EVT5SRC_Pos) /*!< 0x00020000 */ +#define HSP_EVTSRC0R_EVT5SRC_2 (0x4UL << HSP_EVTSRC0R_EVT5SRC_Pos) /*!< 0x00040000 */ + +#define HSP_EVTSRC0R_EVT6SRC_Pos (20UL) +#define HSP_EVTSRC0R_EVT6SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT6SRC_Pos) /*!< 0x00700000 */ +#define HSP_EVTSRC0R_EVT6SRC HSP_EVTSRC0R_EVT6SRC_Msk /*!< EVT6SRC[2:0] bits (Event source selection for priority encoder input 6) */ +#define HSP_EVTSRC0R_EVT6SRC_0 (0x1UL << HSP_EVTSRC0R_EVT6SRC_Pos) /*!< 0x00100000 */ +#define HSP_EVTSRC0R_EVT6SRC_1 (0x2UL << HSP_EVTSRC0R_EVT6SRC_Pos) /*!< 0x00200000 */ +#define HSP_EVTSRC0R_EVT6SRC_2 (0x4UL << HSP_EVTSRC0R_EVT6SRC_Pos) /*!< 0x00400000 */ + +#define HSP_EVTSRC0R_EVT7SRC_Pos (24UL) +#define HSP_EVTSRC0R_EVT7SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT7SRC_Pos) /*!< 0x07000000 */ +#define HSP_EVTSRC0R_EVT7SRC HSP_EVTSRC0R_EVT7SRC_Msk /*!< EVT7SRC[2:0] bits (Event source selection for priority encoder input 7) */ +#define HSP_EVTSRC0R_EVT7SRC_0 (0x1UL << HSP_EVTSRC0R_EVT7SRC_Pos) /*!< 0x01000000 */ +#define HSP_EVTSRC0R_EVT7SRC_1 (0x2UL << HSP_EVTSRC0R_EVT7SRC_Pos) /*!< 0x02000000 */ +#define HSP_EVTSRC0R_EVT7SRC_2 (0x4UL << HSP_EVTSRC0R_EVT7SRC_Pos) /*!< 0x04000000 */ + +#define HSP_EVTSRC0R_EVT8SRC_Pos (28UL) +#define HSP_EVTSRC0R_EVT8SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT8SRC_Pos) /*!< 0x70000000 */ +#define HSP_EVTSRC0R_EVT8SRC HSP_EVTSRC0R_EVT8SRC_Msk /*!< EVT8SRC[2:0] bits (Event source selection for priority encoder input 8) */ +#define HSP_EVTSRC0R_EVT8SRC_0 (0x1UL << HSP_EVTSRC0R_EVT8SRC_Pos) /*!< 0x10000000 */ +#define HSP_EVTSRC0R_EVT8SRC_1 (0x2UL << HSP_EVTSRC0R_EVT8SRC_Pos) /*!< 0x20000000 */ +#define HSP_EVTSRC0R_EVT8SRC_2 (0x4UL << HSP_EVTSRC0R_EVT8SRC_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for HSP_EVTSRC1R register ********************/ +#define HSP_EVTSRC1R_EVT9SRC_Pos (0UL) +#define HSP_EVTSRC1R_EVT9SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT9SRC_Pos) /*!< 0x00000007 */ +#define HSP_EVTSRC1R_EVT9SRC HSP_EVTSRC1R_EVT9SRC_Msk /*!< EVT9SRC[2:0] bits (Event source selection for priority encoder input 9) */ +#define HSP_EVTSRC1R_EVT9SRC_0 (0x1UL << HSP_EVTSRC1R_EVT9SRC_Pos) /*!< 0x00000001 */ +#define HSP_EVTSRC1R_EVT9SRC_1 (0x2UL << HSP_EVTSRC1R_EVT9SRC_Pos) /*!< 0x00000002 */ +#define HSP_EVTSRC1R_EVT9SRC_2 (0x4UL << HSP_EVTSRC1R_EVT9SRC_Pos) /*!< 0x00000004 */ + +#define HSP_EVTSRC1R_EVT10SRC_Pos (4UL) +#define HSP_EVTSRC1R_EVT10SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT10SRC_Pos) /*!< 0x00000070 */ +#define HSP_EVTSRC1R_EVT10SRC HSP_EVTSRC1R_EVT10SRC_Msk /*!< EVT10SRC[2:0] bits (Event source selection for priority encoder input 10) */ +#define HSP_EVTSRC1R_EVT10SRC_0 (0x1UL << HSP_EVTSRC1R_EVT10SRC_Pos) /*!< 0x00000010 */ +#define HSP_EVTSRC1R_EVT10SRC_1 (0x2UL << HSP_EVTSRC1R_EVT10SRC_Pos) /*!< 0x00000020 */ +#define HSP_EVTSRC1R_EVT10SRC_2 (0x4UL << HSP_EVTSRC1R_EVT10SRC_Pos) /*!< 0x00000040 */ + +#define HSP_EVTSRC1R_EVT11SRC_Pos (8UL) +#define HSP_EVTSRC1R_EVT11SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT11SRC_Pos) /*!< 0x00000700 */ +#define HSP_EVTSRC1R_EVT11SRC HSP_EVTSRC1R_EVT11SRC_Msk /*!< EVT11SRC[2:0] bits (Event source selection for priority encoder input 11) */ +#define HSP_EVTSRC1R_EVT11SRC_0 (0x1UL << HSP_EVTSRC1R_EVT11SRC_Pos) /*!< 0x00000100 */ +#define HSP_EVTSRC1R_EVT11SRC_1 (0x2UL << HSP_EVTSRC1R_EVT11SRC_Pos) /*!< 0x00000200 */ +#define HSP_EVTSRC1R_EVT11SRC_2 (0x4UL << HSP_EVTSRC1R_EVT11SRC_Pos) /*!< 0x00000400 */ + +#define HSP_EVTSRC1R_EVT12SRC_Pos (12UL) +#define HSP_EVTSRC1R_EVT12SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT12SRC_Pos) /*!< 0x00007000 */ +#define HSP_EVTSRC1R_EVT12SRC HSP_EVTSRC1R_EVT12SRC_Msk /*!< EVT12SRC[2:0] bits (Event source selection for priority encoder input 12) */ +#define HSP_EVTSRC1R_EVT12SRC_0 (0x1UL << HSP_EVTSRC1R_EVT12SRC_Pos) /*!< 0x00001000 */ +#define HSP_EVTSRC1R_EVT12SRC_1 (0x2UL << HSP_EVTSRC1R_EVT12SRC_Pos) /*!< 0x00002000 */ +#define HSP_EVTSRC1R_EVT12SRC_2 (0x4UL << HSP_EVTSRC1R_EVT12SRC_Pos) /*!< 0x00004000 */ + +#define HSP_EVTSRC1R_EVT13SRC_Pos (16UL) +#define HSP_EVTSRC1R_EVT13SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT13SRC_Pos) /*!< 0x00070000 */ +#define HSP_EVTSRC1R_EVT13SRC HSP_EVTSRC1R_EVT13SRC_Msk /*!< EVT13SRC[2:0] bits (Event source selection for priority encoder input 13) */ +#define HSP_EVTSRC1R_EVT13SRC_0 (0x1UL << HSP_EVTSRC1R_EVT13SRC_Pos) /*!< 0x00010000 */ +#define HSP_EVTSRC1R_EVT13SRC_1 (0x2UL << HSP_EVTSRC1R_EVT13SRC_Pos) /*!< 0x00020000 */ +#define HSP_EVTSRC1R_EVT13SRC_2 (0x4UL << HSP_EVTSRC1R_EVT13SRC_Pos) /*!< 0x00040000 */ + +#define HSP_EVTSRC1R_EVT14SRC_Pos (20UL) +#define HSP_EVTSRC1R_EVT14SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT14SRC_Pos) /*!< 0x00700000 */ +#define HSP_EVTSRC1R_EVT14SRC HSP_EVTSRC1R_EVT14SRC_Msk /*!< EVT14SRC[2:0] bits (Event source selection for priority encoder input 14) */ +#define HSP_EVTSRC1R_EVT14SRC_0 (0x1UL << HSP_EVTSRC1R_EVT14SRC_Pos) /*!< 0x00100000 */ +#define HSP_EVTSRC1R_EVT14SRC_1 (0x2UL << HSP_EVTSRC1R_EVT14SRC_Pos) /*!< 0x00200000 */ +#define HSP_EVTSRC1R_EVT14SRC_2 (0x4UL << HSP_EVTSRC1R_EVT14SRC_Pos) /*!< 0x00400000 */ + +#define HSP_EVTSRC1R_EVT15SRC_Pos (24UL) +#define HSP_EVTSRC1R_EVT15SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT15SRC_Pos) /*!< 0x07000000 */ +#define HSP_EVTSRC1R_EVT15SRC HSP_EVTSRC1R_EVT15SRC_Msk /*!< EVT15SRC[2:0] bits (Event source selection for priority encoder input 15) */ +#define HSP_EVTSRC1R_EVT15SRC_0 (0x1UL << HSP_EVTSRC1R_EVT15SRC_Pos) /*!< 0x01000000 */ +#define HSP_EVTSRC1R_EVT15SRC_1 (0x2UL << HSP_EVTSRC1R_EVT15SRC_Pos) /*!< 0x02000000 */ +#define HSP_EVTSRC1R_EVT15SRC_2 (0x4UL << HSP_EVTSRC1R_EVT15SRC_Pos) /*!< 0x04000000 */ + +#define HSP_EVTSRC1R_EVT16SRC_Pos (28UL) +#define HSP_EVTSRC1R_EVT16SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT16SRC_Pos) /*!< 0x70000000 */ +#define HSP_EVTSRC1R_EVT16SRC HSP_EVTSRC1R_EVT16SRC_Msk /*!< EVT16SRC[2:0] bits (Event source selection for priority encoder input 16) */ +#define HSP_EVTSRC1R_EVT16SRC_0 (0x1UL << HSP_EVTSRC1R_EVT16SRC_Pos) /*!< 0x10000000 */ +#define HSP_EVTSRC1R_EVT16SRC_1 (0x2UL << HSP_EVTSRC1R_EVT16SRC_Pos) /*!< 0x20000000 */ +#define HSP_EVTSRC1R_EVT16SRC_2 (0x4UL << HSP_EVTSRC1R_EVT16SRC_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for HSP_EVTSRC2R register ********************/ +#define HSP_EVTSRC2R_EVT17SRC_Pos (0UL) +#define HSP_EVTSRC2R_EVT17SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT17SRC_Pos) /*!< 0x00000007 */ +#define HSP_EVTSRC2R_EVT17SRC HSP_EVTSRC2R_EVT17SRC_Msk /*!< EVT17SRC[2:0] bits (Event source selection for priority encoder input 17) */ +#define HSP_EVTSRC2R_EVT17SRC_0 (0x1UL << HSP_EVTSRC2R_EVT17SRC_Pos) /*!< 0x00000001 */ +#define HSP_EVTSRC2R_EVT17SRC_1 (0x2UL << HSP_EVTSRC2R_EVT17SRC_Pos) /*!< 0x00000002 */ +#define HSP_EVTSRC2R_EVT17SRC_2 (0x4UL << HSP_EVTSRC2R_EVT17SRC_Pos) /*!< 0x00000004 */ + +#define HSP_EVTSRC2R_EVT18SRC_Pos (4UL) +#define HSP_EVTSRC2R_EVT18SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT18SRC_Pos) /*!< 0x00000070 */ +#define HSP_EVTSRC2R_EVT18SRC HSP_EVTSRC2R_EVT18SRC_Msk /*!< EVT18SRC[2:0] bits (Event source selection for priority encoder input 18) */ +#define HSP_EVTSRC2R_EVT18SRC_0 (0x1UL << HSP_EVTSRC2R_EVT18SRC_Pos) /*!< 0x00000010 */ +#define HSP_EVTSRC2R_EVT18SRC_1 (0x2UL << HSP_EVTSRC2R_EVT18SRC_Pos) /*!< 0x00000020 */ +#define HSP_EVTSRC2R_EVT18SRC_2 (0x4UL << HSP_EVTSRC2R_EVT18SRC_Pos) /*!< 0x00000040 */ + +#define HSP_EVTSRC2R_EVT19SRC_Pos (8UL) +#define HSP_EVTSRC2R_EVT19SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT19SRC_Pos) /*!< 0x00000700 */ +#define HSP_EVTSRC2R_EVT19SRC HSP_EVTSRC2R_EVT19SRC_Msk /*!< EVT19SRC[2:0] bits (Event source selection for priority encoder input 19) */ +#define HSP_EVTSRC2R_EVT19SRC_0 (0x1UL << HSP_EVTSRC2R_EVT19SRC_Pos) /*!< 0x00000100 */ +#define HSP_EVTSRC2R_EVT19SRC_1 (0x2UL << HSP_EVTSRC2R_EVT19SRC_Pos) /*!< 0x00000200 */ +#define HSP_EVTSRC2R_EVT19SRC_2 (0x4UL << HSP_EVTSRC2R_EVT19SRC_Pos) /*!< 0x00000400 */ + +#define HSP_EVTSRC2R_EVT20SRC_Pos (12UL) +#define HSP_EVTSRC2R_EVT20SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT20SRC_Pos) /*!< 0x00007000 */ +#define HSP_EVTSRC2R_EVT20SRC HSP_EVTSRC2R_EVT20SRC_Msk /*!< EVT20SRC[2:0] bits (Event source selection for priority encoder input 20) */ +#define HSP_EVTSRC2R_EVT20SRC_0 (0x1UL << HSP_EVTSRC2R_EVT20SRC_Pos) /*!< 0x00001000 */ +#define HSP_EVTSRC2R_EVT20SRC_1 (0x2UL << HSP_EVTSRC2R_EVT20SRC_Pos) /*!< 0x00002000 */ +#define HSP_EVTSRC2R_EVT20SRC_2 (0x4UL << HSP_EVTSRC2R_EVT20SRC_Pos) /*!< 0x00004000 */ + +#define HSP_EVTSRC2R_EVT21SRC_Pos (16UL) +#define HSP_EVTSRC2R_EVT21SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT21SRC_Pos) /*!< 0x00070000 */ +#define HSP_EVTSRC2R_EVT21SRC HSP_EVTSRC2R_EVT21SRC_Msk /*!< EVT21SRC[2:0] bits (Event source selection for priority encoder input 21) */ +#define HSP_EVTSRC2R_EVT21SRC_0 (0x1UL << HSP_EVTSRC2R_EVT21SRC_Pos) /*!< 0x00010000 */ +#define HSP_EVTSRC2R_EVT21SRC_1 (0x2UL << HSP_EVTSRC2R_EVT21SRC_Pos) /*!< 0x00020000 */ +#define HSP_EVTSRC2R_EVT21SRC_2 (0x4UL << HSP_EVTSRC2R_EVT21SRC_Pos) /*!< 0x00040000 */ + +#define HSP_EVTSRC2R_EVT22SRC_Pos (20UL) +#define HSP_EVTSRC2R_EVT22SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT22SRC_Pos) /*!< 0x00700000 */ +#define HSP_EVTSRC2R_EVT22SRC HSP_EVTSRC2R_EVT22SRC_Msk /*!< EVT22SRC[2:0] bits (Event source selection for priority encoder input 22) */ +#define HSP_EVTSRC2R_EVT22SRC_0 (0x1UL << HSP_EVTSRC2R_EVT22SRC_Pos) /*!< 0x00100000 */ +#define HSP_EVTSRC2R_EVT22SRC_1 (0x2UL << HSP_EVTSRC2R_EVT22SRC_Pos) /*!< 0x00200000 */ +#define HSP_EVTSRC2R_EVT22SRC_2 (0x4UL << HSP_EVTSRC2R_EVT22SRC_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for HSP_BUFFCFGR register ********************/ +#define HSP_BUFFCFGR_BUFF0DIR_Pos (0UL) +#define HSP_BUFFCFGR_BUFF0DIR_Msk (0x1UL << HSP_BUFFCFGR_BUFF0DIR_Pos) /*!< 0x00000001 */ +#define HSP_BUFFCFGR_BUFF0DIR HSP_BUFFCFGR_BUFF0DIR_Msk /*!< BUFF0DIR (Direction selection of BUFF0 (1)) */ + +#define HSP_BUFFCFGR_BUFF1DIR_Pos (1UL) +#define HSP_BUFFCFGR_BUFF1DIR_Msk (0x1UL << HSP_BUFFCFGR_BUFF1DIR_Pos) /*!< 0x00000002 */ +#define HSP_BUFFCFGR_BUFF1DIR HSP_BUFFCFGR_BUFF1DIR_Msk /*!< BUFF1DIR (Direction selection of BUFF1 (1)) */ + +#define HSP_BUFFCFGR_BUFF2DIR_Pos (2UL) +#define HSP_BUFFCFGR_BUFF2DIR_Msk (0x1UL << HSP_BUFFCFGR_BUFF2DIR_Pos) /*!< 0x00000004 */ +#define HSP_BUFFCFGR_BUFF2DIR HSP_BUFFCFGR_BUFF2DIR_Msk /*!< BUFF2DIR (Direction selection of BUFF2 (1)) */ + +#define HSP_BUFFCFGR_BUFF3DIR_Pos (3UL) +#define HSP_BUFFCFGR_BUFF3DIR_Msk (0x1UL << HSP_BUFFCFGR_BUFF3DIR_Pos) /*!< 0x00000008 */ +#define HSP_BUFFCFGR_BUFF3DIR HSP_BUFFCFGR_BUFF3DIR_Msk /*!< BUFF3DIR (Direction selection of BUFF3 (1)) */ + +#define HSP_BUFFCFGR_I2FEN_Pos (8UL) +#define HSP_BUFFCFGR_I2FEN_Msk (0x1UL << HSP_BUFFCFGR_I2FEN_Pos) /*!< 0x00000100 */ +#define HSP_BUFFCFGR_I2FEN HSP_BUFFCFGR_I2FEN_Msk /*!< I2FEN (integer to float32 conversion (1)) */ + +#define HSP_BUFFCFGR_COMB0_Pos (16UL) +#define HSP_BUFFCFGR_COMB0_Msk (0x1UL << HSP_BUFFCFGR_COMB0_Pos) /*!< 0x00010000 */ +#define HSP_BUFFCFGR_COMB0 HSP_BUFFCFGR_COMB0_Msk /*!< COMB0 (BUFCMB control for buff_evt[0] (1)) */ + +#define HSP_BUFFCFGR_COMB1_Pos (17UL) +#define HSP_BUFFCFGR_COMB1_Msk (0x1UL << HSP_BUFFCFGR_COMB1_Pos) /*!< 0x00020000 */ +#define HSP_BUFFCFGR_COMB1 HSP_BUFFCFGR_COMB1_Msk /*!< COMB1 (BUFCMB control for buff_evt[1] (1)) */ + +#define HSP_BUFFCFGR_COMB2_Pos (18UL) +#define HSP_BUFFCFGR_COMB2_Msk (0x1UL << HSP_BUFFCFGR_COMB2_Pos) /*!< 0x00040000 */ +#define HSP_BUFFCFGR_COMB2 HSP_BUFFCFGR_COMB2_Msk /*!< COMB2 (BUFCMB control for buff_evt[2] ) */ + +/******************** Bit definition for HSP_BUFFxDR register ********************/ +#define HSP_BUFFDR_BUFFDAT_Pos (0UL) +#define HSP_BUFFDR_BUFFDAT_Msk (0xFFFFFFFFUL << HSP_BUFFDR_BUFFDAT_Pos) /*!< 0xFFFFFFFF */ +#define HSP_BUFFDR_BUFFDAT HSP_BUFFDR_BUFFDAT_Msk /*!< BUFFDAT[31:0] bits (Data buffer) */ + +/******************** Bit definition for HSP_TRGINCFGR register ********************/ +#define HSP_TRGINCFGR_TRG0POL_Pos (0UL) +#define HSP_TRGINCFGR_TRG0POL_Msk (0x1UL << HSP_TRGINCFGR_TRG0POL_Pos) /*!< 0x00000001 */ +#define HSP_TRGINCFGR_TRG0POL HSP_TRGINCFGR_TRG0POL_Msk /*!< TRG0POL (Polarity selection for TRGIN0) */ + +#define HSP_TRGINCFGR_TRG1POL_Pos (1UL) +#define HSP_TRGINCFGR_TRG1POL_Msk (0x1UL << HSP_TRGINCFGR_TRG1POL_Pos) /*!< 0x00000002 */ +#define HSP_TRGINCFGR_TRG1POL HSP_TRGINCFGR_TRG1POL_Msk /*!< TRG1POL (Polarity selection for TRGIN1) */ + +#define HSP_TRGINCFGR_TRG2POL_Pos (2UL) +#define HSP_TRGINCFGR_TRG2POL_Msk (0x1UL << HSP_TRGINCFGR_TRG2POL_Pos) /*!< 0x00000004 */ +#define HSP_TRGINCFGR_TRG2POL HSP_TRGINCFGR_TRG2POL_Msk /*!< TRG2POL (Polarity selection for TRGIN2) */ + +#define HSP_TRGINCFGR_TRG3POL_Pos (3UL) +#define HSP_TRGINCFGR_TRG3POL_Msk (0x1UL << HSP_TRGINCFGR_TRG3POL_Pos) /*!< 0x00000008 */ +#define HSP_TRGINCFGR_TRG3POL HSP_TRGINCFGR_TRG3POL_Msk /*!< TRG3POL (Polarity selection for TRGIN3) */ + +#define HSP_TRGINCFGR_TRG4POL_Pos (4UL) +#define HSP_TRGINCFGR_TRG4POL_Msk (0x1UL << HSP_TRGINCFGR_TRG4POL_Pos) /*!< 0x00000010 */ +#define HSP_TRGINCFGR_TRG4POL HSP_TRGINCFGR_TRG4POL_Msk /*!< TRG4POL (Polarity selection for TRGIN4) */ + +#define HSP_TRGINCFGR_TRG5POL_Pos (5UL) +#define HSP_TRGINCFGR_TRG5POL_Msk (0x1UL << HSP_TRGINCFGR_TRG5POL_Pos) /*!< 0x00000020 */ +#define HSP_TRGINCFGR_TRG5POL HSP_TRGINCFGR_TRG5POL_Msk /*!< TRG5POL (Polarity selection for TRGIN5) */ + +#define HSP_TRGINCFGR_TRG6POL_Pos (6UL) +#define HSP_TRGINCFGR_TRG6POL_Msk (0x1UL << HSP_TRGINCFGR_TRG6POL_Pos) /*!< 0x00000040 */ +#define HSP_TRGINCFGR_TRG6POL HSP_TRGINCFGR_TRG6POL_Msk /*!< TRG6POL (Polarity selection for TRGIN6) */ + +#define HSP_TRGINCFGR_TRG7POL_Pos (7UL) +#define HSP_TRGINCFGR_TRG7POL_Msk (0x1UL << HSP_TRGINCFGR_TRG7POL_Pos) /*!< 0x00000080 */ +#define HSP_TRGINCFGR_TRG7POL HSP_TRGINCFGR_TRG7POL_Msk /*!< TRG7POL (Polarity selection for TRGIN7) */ + +#define HSP_TRGINCFGR_TRG8POL_Pos (8UL) +#define HSP_TRGINCFGR_TRG8POL_Msk (0x1UL << HSP_TRGINCFGR_TRG8POL_Pos) /*!< 0x00000100 */ +#define HSP_TRGINCFGR_TRG8POL HSP_TRGINCFGR_TRG8POL_Msk /*!< TRG8POL (Polarity selection for TRGIN8) */ + +#define HSP_TRGINCFGR_TRG9POL_Pos (9UL) +#define HSP_TRGINCFGR_TRG9POL_Msk (0x1UL << HSP_TRGINCFGR_TRG9POL_Pos) /*!< 0x00000200 */ +#define HSP_TRGINCFGR_TRG9POL HSP_TRGINCFGR_TRG9POL_Msk /*!< TRG9POL (Polarity selection for TRGIN9) */ + +/******************** Bit definition for HSP_TRGOCFGR register ********************/ +#define HSP_TRGOCFGR_TRGO0SRC_Pos (0UL) +#define HSP_TRGOCFGR_TRGO0SRC_Msk (0x3UL << HSP_TRGOCFGR_TRGO0SRC_Pos) /*!< 0x00000003 */ +#define HSP_TRGOCFGR_TRGO0SRC HSP_TRGOCFGR_TRGO0SRC_Msk /*!< TRGO0SRC[1:0] bits (Trigger source selection for hsp_trg_out[0] (1)) */ +#define HSP_TRGOCFGR_TRGO0SRC_0 (0x1UL << HSP_TRGOCFGR_TRGO0SRC_Pos) /*!< 0x00000001 */ +#define HSP_TRGOCFGR_TRGO0SRC_1 (0x2UL << HSP_TRGOCFGR_TRGO0SRC_Pos) /*!< 0x00000002 */ + +#define HSP_TRGOCFGR_TRGO1SRC_Pos (2UL) +#define HSP_TRGOCFGR_TRGO1SRC_Msk (0x3UL << HSP_TRGOCFGR_TRGO1SRC_Pos) /*!< 0x0000000C */ +#define HSP_TRGOCFGR_TRGO1SRC HSP_TRGOCFGR_TRGO1SRC_Msk /*!< TRGO1SRC[1:0] bits (Trigger source selection for hsp_trg_out[1] (1)) */ +#define HSP_TRGOCFGR_TRGO1SRC_0 (0x1UL << HSP_TRGOCFGR_TRGO1SRC_Pos) /*!< 0x00000004 */ +#define HSP_TRGOCFGR_TRGO1SRC_1 (0x2UL << HSP_TRGOCFGR_TRGO1SRC_Pos) /*!< 0x00000008 */ + +#define HSP_TRGOCFGR_TRGO2SRC_Pos (4UL) +#define HSP_TRGOCFGR_TRGO2SRC_Msk (0x3UL << HSP_TRGOCFGR_TRGO2SRC_Pos) /*!< 0x00000030 */ +#define HSP_TRGOCFGR_TRGO2SRC HSP_TRGOCFGR_TRGO2SRC_Msk /*!< TRGO2SRC[1:0] bits (Trigger source selection for hsp_trg_out[2] (1)) */ +#define HSP_TRGOCFGR_TRGO2SRC_0 (0x1UL << HSP_TRGOCFGR_TRGO2SRC_Pos) /*!< 0x00000010 */ +#define HSP_TRGOCFGR_TRGO2SRC_1 (0x2UL << HSP_TRGOCFGR_TRGO2SRC_Pos) /*!< 0x00000020 */ + +#define HSP_TRGOCFGR_TRGO3SRC_Pos (6UL) +#define HSP_TRGOCFGR_TRGO3SRC_Msk (0x3UL << HSP_TRGOCFGR_TRGO3SRC_Pos) /*!< 0x000000C0 */ +#define HSP_TRGOCFGR_TRGO3SRC HSP_TRGOCFGR_TRGO3SRC_Msk /*!< TRGO3SRC[1:0] bits (Trigger source selection for hsp_trg_out[3] ) */ +#define HSP_TRGOCFGR_TRGO3SRC_0 (0x1UL << HSP_TRGOCFGR_TRGO3SRC_Pos) /*!< 0x00000040 */ +#define HSP_TRGOCFGR_TRGO3SRC_1 (0x2UL << HSP_TRGOCFGR_TRGO3SRC_Pos) /*!< 0x00000080 */ + +/******************** Bit definition for HSP_CSEGR register ********************/ +#define HSP_CSEGR_CSEVT_Pos (1UL) +#define HSP_CSEGR_CSEVT_Msk (0x3FFFFFUL << HSP_CSEGR_CSEVT_Pos) /*!< 0x007FFFFE */ +#define HSP_CSEGR_CSEVT HSP_CSEGR_CSEVT_Msk /*!< CSEVT[21:0] bits (CPU Shared Software Event ) */ +#define HSP_CSEGR_CSEVT_0 (0x0001UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000002 */ +#define HSP_CSEGR_CSEVT_1 (0x0002UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000004 */ +#define HSP_CSEGR_CSEVT_2 (0x0004UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000008 */ +#define HSP_CSEGR_CSEVT_3 (0x0008UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000010 */ +#define HSP_CSEGR_CSEVT_4 (0x0010UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000020 */ +#define HSP_CSEGR_CSEVT_5 (0x0020UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000040 */ +#define HSP_CSEGR_CSEVT_6 (0x0040UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000080 */ +#define HSP_CSEGR_CSEVT_7 (0x0080UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000100 */ +#define HSP_CSEGR_CSEVT_8 (0x0100UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000200 */ +#define HSP_CSEGR_CSEVT_9 (0x0200UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000400 */ +#define HSP_CSEGR_CSEVT_10 (0x0400UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000800 */ +#define HSP_CSEGR_CSEVT_11 (0x0800UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00001000 */ +#define HSP_CSEGR_CSEVT_12 (0x1000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00002000 */ +#define HSP_CSEGR_CSEVT_13 (0x2000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00004000 */ +#define HSP_CSEGR_CSEVT_14 (0x4000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00008000 */ +#define HSP_CSEGR_CSEVT_15 (0x8000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00010000 */ +#define HSP_CSEGR_CSEVT_16 (0x10000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00020000 */ +#define HSP_CSEGR_CSEVT_17 (0x20000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00040000 */ +#define HSP_CSEGR_CSEVT_18 (0x40000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00080000 */ +#define HSP_CSEGR_CSEVT_19 (0x80000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00100000 */ +#define HSP_CSEGR_CSEVT_20 (0x100000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00200000 */ +#define HSP_CSEGR_CSEVT_21 (0x200000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for HSP_CDEGR register ********************/ +#define HSP_CDEGR_CTSKN_Pos (0UL) +#define HSP_CDEGR_CTSKN_Msk (0x3FUL << HSP_CDEGR_CTSKN_Pos) /*!< 0x0000003F */ +#define HSP_CDEGR_CTSKN HSP_CDEGR_CTSKN_Msk /*!< CTSKN[5:0] bits (CPU Task number) */ + +#define HSP_CDEGR_CDEGBSY_Pos (31UL) +#define HSP_CDEGR_CDEGBSY_Msk (0x1UL << HSP_CDEGR_CDEGBSY_Pos) /*!< 0x80000000 */ +#define HSP_CDEGR_CDEGBSY HSP_CDEGR_CDEGBSY_Msk /*!< CDEGBSY (CPU dedicated event generator busy) */ + +/******************** Bit definition for HSP_TRGINSELR0 register ********************/ +#define HSP_TRGINSELR0_TRG0SEL_Pos (0UL) +#define HSP_TRGINSELR0_TRG0SEL_Msk (0x3FUL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x0000003F */ +#define HSP_TRGINSELR0_TRG0SEL HSP_TRGINSELR0_TRG0SEL_Msk /*!< TRG0SEL[5:0] bits (Input trigger selection for TRGIN0) */ +#define HSP_TRGINSELR0_TRG0SEL_0 (0x01UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000001 */ +#define HSP_TRGINSELR0_TRG0SEL_1 (0x02UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000002 */ +#define HSP_TRGINSELR0_TRG0SEL_2 (0x04UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000004 */ +#define HSP_TRGINSELR0_TRG0SEL_3 (0x08UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000008 */ +#define HSP_TRGINSELR0_TRG0SEL_4 (0x10UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000010 */ +#define HSP_TRGINSELR0_TRG0SEL_5 (0x20UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000020 */ + +#define HSP_TRGINSELR0_TRG1SEL_Pos (8UL) +#define HSP_TRGINSELR0_TRG1SEL_Msk (0x3FUL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00003F00 */ +#define HSP_TRGINSELR0_TRG1SEL HSP_TRGINSELR0_TRG1SEL_Msk /*!< TRG1SEL[5:0] bits (Input trigger selection for TRGIN1) */ +#define HSP_TRGINSELR0_TRG1SEL_0 (0x01UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00000100 */ +#define HSP_TRGINSELR0_TRG1SEL_1 (0x02UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00000200 */ +#define HSP_TRGINSELR0_TRG1SEL_2 (0x04UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00000400 */ +#define HSP_TRGINSELR0_TRG1SEL_3 (0x08UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00000800 */ +#define HSP_TRGINSELR0_TRG1SEL_4 (0x10UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00001000 */ +#define HSP_TRGINSELR0_TRG1SEL_5 (0x20UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00002000 */ + +#define HSP_TRGINSELR0_TRG2SEL_Pos (16UL) +#define HSP_TRGINSELR0_TRG2SEL_Msk (0x3FUL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x003F0000 */ +#define HSP_TRGINSELR0_TRG2SEL HSP_TRGINSELR0_TRG2SEL_Msk /*!< TRG2SEL[5:0] bits (Input trigger selection for TRGIN2) */ +#define HSP_TRGINSELR0_TRG2SEL_0 (0x01UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00010000 */ +#define HSP_TRGINSELR0_TRG2SEL_1 (0x02UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00020000 */ +#define HSP_TRGINSELR0_TRG2SEL_2 (0x04UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00040000 */ +#define HSP_TRGINSELR0_TRG2SEL_3 (0x08UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00080000 */ +#define HSP_TRGINSELR0_TRG2SEL_4 (0x10UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00100000 */ +#define HSP_TRGINSELR0_TRG2SEL_5 (0x20UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00200000 */ + +#define HSP_TRGINSELR0_TRG3SEL_Pos (24UL) +#define HSP_TRGINSELR0_TRG3SEL_Msk (0x3FUL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x3F000000 */ +#define HSP_TRGINSELR0_TRG3SEL HSP_TRGINSELR0_TRG3SEL_Msk /*!< TRG3SEL[5:0] bits (Input trigger selection for TRGIN3) */ +#define HSP_TRGINSELR0_TRG3SEL_0 (0x01UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x01000000 */ +#define HSP_TRGINSELR0_TRG3SEL_1 (0x02UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x02000000 */ +#define HSP_TRGINSELR0_TRG3SEL_2 (0x04UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x04000000 */ +#define HSP_TRGINSELR0_TRG3SEL_3 (0x08UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x08000000 */ +#define HSP_TRGINSELR0_TRG3SEL_4 (0x10UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x10000000 */ +#define HSP_TRGINSELR0_TRG3SEL_5 (0x20UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for HSP_TRGINSELR1 register ********************/ +#define HSP_TRGINSELR1_TRG4SEL_Pos (0UL) +#define HSP_TRGINSELR1_TRG4SEL_Msk (0x3FUL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x0000003F */ +#define HSP_TRGINSELR1_TRG4SEL HSP_TRGINSELR1_TRG4SEL_Msk /*!< TRG4SEL[5:0] bits (Input trigger selection for TRGIN4) */ +#define HSP_TRGINSELR1_TRG4SEL_0 (0x01UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000001 */ +#define HSP_TRGINSELR1_TRG4SEL_1 (0x02UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000002 */ +#define HSP_TRGINSELR1_TRG4SEL_2 (0x04UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000004 */ +#define HSP_TRGINSELR1_TRG4SEL_3 (0x08UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000008 */ +#define HSP_TRGINSELR1_TRG4SEL_4 (0x10UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000010 */ +#define HSP_TRGINSELR1_TRG4SEL_5 (0x20UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000020 */ + +#define HSP_TRGINSELR1_TRG5SEL_Pos (8UL) +#define HSP_TRGINSELR1_TRG5SEL_Msk (0x3FUL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00003F00 */ +#define HSP_TRGINSELR1_TRG5SEL HSP_TRGINSELR1_TRG5SEL_Msk /*!< TRG5SEL[5:0] bits (Input trigger selection for TRGIN5) */ +#define HSP_TRGINSELR1_TRG5SEL_0 (0x01UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00000100 */ +#define HSP_TRGINSELR1_TRG5SEL_1 (0x02UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00000200 */ +#define HSP_TRGINSELR1_TRG5SEL_2 (0x04UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00000400 */ +#define HSP_TRGINSELR1_TRG5SEL_3 (0x08UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00000800 */ +#define HSP_TRGINSELR1_TRG5SEL_4 (0x10UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00001000 */ +#define HSP_TRGINSELR1_TRG5SEL_5 (0x20UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00002000 */ + +#define HSP_TRGINSELR1_TRG6SEL_Pos (16UL) +#define HSP_TRGINSELR1_TRG6SEL_Msk (0x3FUL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x003F0000 */ +#define HSP_TRGINSELR1_TRG6SEL HSP_TRGINSELR1_TRG6SEL_Msk /*!< TRG6SEL[5:0] bits (Input trigger selection for TRGIN6) */ +#define HSP_TRGINSELR1_TRG6SEL_0 (0x01UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00010000 */ +#define HSP_TRGINSELR1_TRG6SEL_1 (0x02UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00020000 */ +#define HSP_TRGINSELR1_TRG6SEL_2 (0x04UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00040000 */ +#define HSP_TRGINSELR1_TRG6SEL_3 (0x08UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00080000 */ +#define HSP_TRGINSELR1_TRG6SEL_4 (0x10UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00100000 */ +#define HSP_TRGINSELR1_TRG6SEL_5 (0x20UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00200000 */ + +#define HSP_TRGINSELR1_TRG7SEL_Pos (24UL) +#define HSP_TRGINSELR1_TRG7SEL_Msk (0x3FUL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x3F000000 */ +#define HSP_TRGINSELR1_TRG7SEL HSP_TRGINSELR1_TRG7SEL_Msk /*!< TRG7SEL[5:0] bits (Input trigger selection for TRGIN7) */ +#define HSP_TRGINSELR1_TRG7SEL_0 (0x01UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x01000000 */ +#define HSP_TRGINSELR1_TRG7SEL_1 (0x02UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x02000000 */ +#define HSP_TRGINSELR1_TRG7SEL_2 (0x04UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x04000000 */ +#define HSP_TRGINSELR1_TRG7SEL_3 (0x08UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x08000000 */ +#define HSP_TRGINSELR1_TRG7SEL_4 (0x10UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x10000000 */ +#define HSP_TRGINSELR1_TRG7SEL_5 (0x20UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for HSP_TRGINSELR2 register ********************/ +#define HSP_TRGINSELR2_TRG8SEL_Pos (0UL) +#define HSP_TRGINSELR2_TRG8SEL_Msk (0x3FUL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x0000003F */ +#define HSP_TRGINSELR2_TRG8SEL HSP_TRGINSELR2_TRG8SEL_Msk /*!< TRG8SEL[5:0] bits (Input trigger selection for TRGIN8) */ +#define HSP_TRGINSELR2_TRG8SEL_0 (0x01UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000001 */ +#define HSP_TRGINSELR2_TRG8SEL_1 (0x02UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000002 */ +#define HSP_TRGINSELR2_TRG8SEL_2 (0x04UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000004 */ +#define HSP_TRGINSELR2_TRG8SEL_3 (0x08UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000008 */ +#define HSP_TRGINSELR2_TRG8SEL_4 (0x10UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000010 */ +#define HSP_TRGINSELR2_TRG8SEL_5 (0x20UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000020 */ + +#define HSP_TRGINSELR2_TRG9SEL_Pos (8UL) +#define HSP_TRGINSELR2_TRG9SEL_Msk (0x3FUL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00003F00 */ +#define HSP_TRGINSELR2_TRG9SEL HSP_TRGINSELR2_TRG9SEL_Msk /*!< TRG9SEL[5:0] bits (Input trigger selection for TRGIN9) */ +#define HSP_TRGINSELR2_TRG9SEL_0 (0x01UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00000100 */ +#define HSP_TRGINSELR2_TRG9SEL_1 (0x02UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00000200 */ +#define HSP_TRGINSELR2_TRG9SEL_2 (0x04UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00000400 */ +#define HSP_TRGINSELR2_TRG9SEL_3 (0x08UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00000800 */ +#define HSP_TRGINSELR2_TRG9SEL_4 (0x10UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00001000 */ +#define HSP_TRGINSELR2_TRG9SEL_5 (0x20UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00002000 */ + +/******************** Bit definition for HSP_BKOxCFGR register ********************/ +#define HSP_BKOCFGR_ACCEREN_Pos (0U) +#define HSP_BKOCFGR_ACCEREN_Msk (0x1UL << HSP_BKOCFGR_ACCEREN_Pos) /*!< 0x00000001 */ +#define HSP_BKOCFGR_ACCEREN HSP_BKOCFGR_ACCEREN_Msk /*!< ACCEREN (Access error break enable for ACCERRF (1)) */ + +#define HSP_BKOCFGR_FPUEREN_Pos (1U) +#define HSP_BKOCFGR_FPUEREN_Msk (0x1UL << HSP_BKOCFGR_FPUEREN_Pos) /*!< 0x00000002 */ +#define HSP_BKOCFGR_FPUEREN HSP_BKOCFGR_FPUEREN_Msk /*!< FPUEREN (FPU error break enable for FPUERRF (1)) */ + +#define HSP_BKOCFGR_OPCEREN_Pos (2U) +#define HSP_BKOCFGR_OPCEREN_Msk (0x1UL << HSP_BKOCFGR_OPCEREN_Pos) /*!< 0x00000004 */ +#define HSP_BKOCFGR_OPCEREN HSP_BKOCFGR_OPCEREN_Msk /*!< OPCEREN (Opcode error break enable for OPCOERRF ) */ + +#define HSP_BKOCFGR_PFCT28EN_Pos (4U) +#define HSP_BKOCFGR_PFCT28EN_Msk (0x1UL << HSP_BKOCFGR_PFCT28EN_Pos) /*!< 0x00000010 */ +#define HSP_BKOCFGR_PFCT28EN HSP_BKOCFGR_PFCT28EN_Msk /*!< PFCT28EN (Processing function flag break enable for PFCTF[28] (1)) */ + +#define HSP_BKOCFGR_PFCT29EN_Pos (5U) +#define HSP_BKOCFGR_PFCT29EN_Msk (0x1UL << HSP_BKOCFGR_PFCT29EN_Pos) /*!< 0x00000020 */ +#define HSP_BKOCFGR_PFCT29EN HSP_BKOCFGR_PFCT29EN_Msk /*!< PFCT29EN (Processing function flag break enable for PFCTF[29] (1)) */ + +#define HSP_BKOCFGR_PFCT30EN_Pos (6U) +#define HSP_BKOCFGR_PFCT30EN_Msk (0x1UL << HSP_BKOCFGR_PFCT30EN_Pos) /*!< 0x00000040 */ +#define HSP_BKOCFGR_PFCT30EN HSP_BKOCFGR_PFCT30EN_Msk /*!< PFCT30EN (Processing function flag break enable for PFCTF[30] (1)) */ + +#define HSP_BKOCFGR_PFCT31EN_Pos (7U) +#define HSP_BKOCFGR_PFCT31EN_Msk (0x1UL << HSP_BKOCFGR_PFCT31EN_Pos) /*!< 0x00000080 */ +#define HSP_BKOCFGR_PFCT31EN HSP_BKOCFGR_PFCT31EN_Msk /*!< PFCT31EN (Processing function flag break enable for PFCTF[31] (1)) */ + +#define HSP_BKOCFGR_FWEREN_Pos (12U) +#define HSP_BKOCFGR_FWEREN_Msk (0x1UL << HSP_BKOCFGR_FWEREN_Pos) /*!< 0x00001000 */ +#define HSP_BKOCFGR_FWEREN HSP_BKOCFGR_FWEREN_Msk /*!< FWEREN (Firmware error break enable for FWERRF (1)) */ + +#define HSP_BKOCFGR_HDEGOVEN_Pos (13U) +#define HSP_BKOCFGR_HDEGOVEN_Msk (0x1UL << HSP_BKOCFGR_HDEGOVEN_Pos) /*!< 0x00002000 */ +#define HSP_BKOCFGR_HDEGOVEN HSP_BKOCFGR_HDEGOVEN_Msk /*!< HDEGOVEN (HSP dedicated event generator overrun break enable for HDEGOVRF (1)) */ + +/******************** Bit definition for HSP_BKICFGR register ********************/ +#define HSP_BKICFGR_ACCEREN_Pos (0UL) +#define HSP_BKICFGR_ACCEREN_Msk (0x1UL << HSP_BKICFGR_ACCEREN_Pos) /*!< 0x00000001 */ +#define HSP_BKICFGR_ACCEREN HSP_BKICFGR_ACCEREN_Msk /*!< ACCEREN (Access error break enable for ACCERRF (1)) */ + +#define HSP_BKICFGR_FPUEREN_Pos (1UL) +#define HSP_BKICFGR_FPUEREN_Msk (0x1UL << HSP_BKICFGR_FPUEREN_Pos) /*!< 0x00000002 */ +#define HSP_BKICFGR_FPUEREN HSP_BKICFGR_FPUEREN_Msk /*!< FPUEREN (FPU error break enable for FPUERRF (1)) */ + +#define HSP_BKICFGR_OPCEREN_Pos (2UL) +#define HSP_BKICFGR_OPCEREN_Msk (0x1UL << HSP_BKICFGR_OPCEREN_Pos) /*!< 0x00000004 */ +#define HSP_BKICFGR_OPCEREN HSP_BKICFGR_OPCEREN_Msk /*!< OPCEREN (Opcode error break enable for OPCOERRF ) */ + +#define HSP_BKICFGR_PFCT28EN_Pos (4UL) +#define HSP_BKICFGR_PFCT28EN_Msk (0x1UL << HSP_BKICFGR_PFCT28EN_Pos) /*!< 0x00000010 */ +#define HSP_BKICFGR_PFCT28EN HSP_BKICFGR_PFCT28EN_Msk /*!< PFCT28EN (Processing function flag break enable for PFCTF[28] (1)) */ + +#define HSP_BKICFGR_PFCT29EN_Pos (5UL) +#define HSP_BKICFGR_PFCT29EN_Msk (0x1UL << HSP_BKICFGR_PFCT29EN_Pos) /*!< 0x00000020 */ +#define HSP_BKICFGR_PFCT29EN HSP_BKICFGR_PFCT29EN_Msk /*!< PFCT29EN (Processing function flag break enable for PFCTF[29] (1)) */ + +#define HSP_BKICFGR_PFCT30EN_Pos (6UL) +#define HSP_BKICFGR_PFCT30EN_Msk (0x1UL << HSP_BKICFGR_PFCT30EN_Pos) /*!< 0x00000040 */ +#define HSP_BKICFGR_PFCT30EN HSP_BKICFGR_PFCT30EN_Msk /*!< PFCT30EN (Processing function flag break enable for PFCTF[30] (1)) */ + +#define HSP_BKICFGR_PFCT31EN_Pos (7UL) +#define HSP_BKICFGR_PFCT31EN_Msk (0x1UL << HSP_BKICFGR_PFCT31EN_Pos) /*!< 0x00000080 */ +#define HSP_BKICFGR_PFCT31EN HSP_BKICFGR_PFCT31EN_Msk /*!< PFCT31EN (Processing function flag break enable for PFCTF[31] (1)) */ + +#define HSP_BKICFGR_FWEREN_Pos (12UL) +#define HSP_BKICFGR_FWEREN_Msk (0x1UL << HSP_BKICFGR_FWEREN_Pos) /*!< 0x00001000 */ +#define HSP_BKICFGR_FWEREN HSP_BKICFGR_FWEREN_Msk /*!< FWEREN (Firmware error break enable for FWERRF (1)) */ + +#define HSP_BKICFGR_HDEGOVEN_Pos (13UL) +#define HSP_BKICFGR_HDEGOVEN_Msk (0x1UL << HSP_BKICFGR_HDEGOVEN_Pos) /*!< 0x00002000 */ +#define HSP_BKICFGR_HDEGOVEN HSP_BKICFGR_HDEGOVEN_Msk /*!< HDEGOVEN (HSP dedicated event generator overrun break enable for HDEGOVRF (1)) */ + +#define HSP_BKICFGR_FSATEN_Pos (14UL) +#define HSP_BKICFGR_FSATEN_Msk (0x1UL << HSP_BKICFGR_FSATEN_Pos) /*!< 0x00004000 */ +#define HSP_BKICFGR_FSATEN HSP_BKICFGR_FSATEN_Msk /*!< FSATEN (FPU saturation break enable for FPUSATF (1)) */ + +#define HSP_BKICFGR_SSEN_Pos (17UL) +#define HSP_BKICFGR_SSEN_Msk (0x1UL << HSP_BKICFGR_SSEN_Pos) /*!< 0x00020000 */ +#define HSP_BKICFGR_SSEN HSP_BKICFGR_SSEN_Msk /*!< SSEN (Single step enable (1)) */ + +/******************** Bit definition for HSP_FWERR register ********************/ +#define HSP_FWERR_FWERRN_Pos (0UL) +#define HSP_FWERR_FWERRN_Msk (0x3FFUL << HSP_FWERR_FWERRN_Pos) /*!< 0x000003FF */ +#define HSP_FWERR_FWERRN HSP_FWERR_FWERRN_Msk /*!< FWERRN[9:0] bits (Firmware error number) */ + +/******************** Bit definition for HSP_PARAMR0 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR0_PARAM_Pos (0UL) +#define HSP_PARAMR0_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR0_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR0_PARAM HSP_PARAMR0_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR1 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR1_PARAM_Pos (0UL) +#define HSP_PARAMR1_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR1_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR1_PARAM HSP_PARAMR1_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR2 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR2_PARAM_Pos (0UL) +#define HSP_PARAMR2_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR2_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR2_PARAM HSP_PARAMR2_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR3 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR3_PARAM_Pos (0UL) +#define HSP_PARAMR3_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR3_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR3_PARAM HSP_PARAMR3_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR4 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR4_PARAM_Pos (0UL) +#define HSP_PARAMR4_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR4_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR4_PARAM HSP_PARAMR4_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR5 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR5_PARAM_Pos (0UL) +#define HSP_PARAMR5_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR5_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR5_PARAM HSP_PARAMR5_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR6 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR6_PARAM_Pos (0UL) +#define HSP_PARAMR6_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR6_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR6_PARAM HSP_PARAMR6_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR7 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR7_PARAM_Pos (0UL) +#define HSP_PARAMR7_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR7_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR7_PARAM HSP_PARAMR7_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR8 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR8_PARAM_Pos (0UL) +#define HSP_PARAMR8_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR8_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR8_PARAM HSP_PARAMR8_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR9 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR9_PARAM_Pos (0UL) +#define HSP_PARAMR9_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR9_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR9_PARAM HSP_PARAMR9_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR10 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR10_PARAM_Pos (0UL) +#define HSP_PARAMR10_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR10_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR10_PARAM HSP_PARAMR10_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR11 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR11_PARAM_Pos (0UL) +#define HSP_PARAMR11_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR11_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR11_PARAM HSP_PARAMR11_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR12 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR12_PARAM_Pos (0UL) +#define HSP_PARAMR12_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR12_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR12_PARAM HSP_PARAMR12_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR13 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR13_PARAM_Pos (0UL) +#define HSP_PARAMR13_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR13_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR13_PARAM HSP_PARAMR13_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR14 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR14_PARAM_Pos (0UL) +#define HSP_PARAMR14_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR14_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR14_PARAM HSP_PARAMR14_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_PARAMR15 register ********************/ +/*!< PARAM configuration */ +#define HSP_PARAMR15_PARAM_Pos (0UL) +#define HSP_PARAMR15_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR15_PARAM_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PARAMR15_PARAM HSP_PARAMR15_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ + +/******************** Bit definition for HSP_SPE_IER register ********************/ +#define HSP_SPE_IER_C2HMRDYIE_Pos (0UL) +#define HSP_SPE_IER_C2HMRDYIE_Msk (0x1UL << HSP_SPE_IER_C2HMRDYIE_Pos) /*!< 0x00000001 */ +#define HSP_SPE_IER_C2HMRDYIE HSP_SPE_IER_C2HMRDYIE_Msk /*!< C2HMRDYIE (CPU to SPE message ready interrupt enable) */ + +#define HSP_SPE_IER_H2CMFREEIE_Pos (1UL) +#define HSP_SPE_IER_H2CMFREEIE_Msk (0x1UL << HSP_SPE_IER_H2CMFREEIE_Pos) /*!< 0x00000002 */ +#define HSP_SPE_IER_H2CMFREEIE HSP_SPE_IER_H2CMFREEIE_Msk /*!< H2CMFREEIE (SPE to CPU message free interrupt enable) */ + +/******************** Bit definition for HSP_SPE_ISR register ********************/ +#define HSP_SPE_ISR_C2HMRDYF_Pos (0UL) +#define HSP_SPE_ISR_C2HMRDYF_Msk (0x1UL << HSP_SPE_ISR_C2HMRDYF_Pos) /*!< 0x00000001 */ +#define HSP_SPE_ISR_C2HMRDYF HSP_SPE_ISR_C2HMRDYF_Msk /*!< C2HMRDYF (CPU to SPE message box status) */ + +#define HSP_SPE_ISR_H2CMFREEF_Pos (1UL) +#define HSP_SPE_ISR_H2CMFREEF_Msk (0x1UL << HSP_SPE_ISR_H2CMFREEF_Pos) /*!< 0x00000002 */ +#define HSP_SPE_ISR_H2CMFREEF HSP_SPE_ISR_H2CMFREEF_Msk /*!< H2CMFREEF (SPE to CPU message box status) */ + +#define HSP_SPE_ISR_RSTREQF_Pos (4UL) +#define HSP_SPE_ISR_RSTREQF_Msk (0x1UL << HSP_SPE_ISR_RSTREQF_Pos) /*!< 0x00000010 */ +#define HSP_SPE_ISR_RSTREQF HSP_SPE_ISR_RSTREQF_Msk /*!< RSTREQF (HSP reset request) */ + +#define HSP_SPE_ISR_BUF0EVTF_Pos (12UL) +#define HSP_SPE_ISR_BUF0EVTF_Msk (0x1UL << HSP_SPE_ISR_BUF0EVTF_Pos) /*!< 0x00001000 */ +#define HSP_SPE_ISR_BUF0EVTF HSP_SPE_ISR_BUF0EVTF_Msk /*!< BUF0EVTF (BUF0 status) */ + +#define HSP_SPE_ISR_BUF1EVTF_Pos (13UL) +#define HSP_SPE_ISR_BUF1EVTF_Msk (0x1UL << HSP_SPE_ISR_BUF1EVTF_Pos) /*!< 0x00002000 */ +#define HSP_SPE_ISR_BUF1EVTF HSP_SPE_ISR_BUF1EVTF_Msk /*!< BUF1EVTF (BUF1 status) */ + +#define HSP_SPE_ISR_BUF2EVTF_Pos (14UL) +#define HSP_SPE_ISR_BUF2EVTF_Msk (0x1UL << HSP_SPE_ISR_BUF2EVTF_Pos) /*!< 0x00004000 */ +#define HSP_SPE_ISR_BUF2EVTF HSP_SPE_ISR_BUF2EVTF_Msk /*!< BUF2EVTF (BUF2 status) */ + +#define HSP_SPE_ISR_BUF3EVTF_Pos (15UL) +#define HSP_SPE_ISR_BUF3EVTF_Msk (0x1UL << HSP_SPE_ISR_BUF3EVTF_Pos) /*!< 0x00008000 */ +#define HSP_SPE_ISR_BUF3EVTF HSP_SPE_ISR_BUF3EVTF_Msk /*!< BUF3EVTF (BUF3 status) */ + +/******************** Bit definition for HSP_TCUCFGR register ********************/ +#define HSP_TCUCFGR_TSKCMP0_Pos (0UL) +#define HSP_TCUCFGR_TSKCMP0_Msk (0x3FUL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x0000003F */ +#define HSP_TCUCFGR_TSKCMP0 HSP_TCUCFGR_TSKCMP0_Msk /*!< TSKCMP0[5:0] bits (Task compare 0 (1)) */ +#define HSP_TCUCFGR_TSKCMP0_0 (0x01UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000001 */ +#define HSP_TCUCFGR_TSKCMP0_1 (0x02UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000002 */ +#define HSP_TCUCFGR_TSKCMP0_2 (0x04UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000004 */ +#define HSP_TCUCFGR_TSKCMP0_3 (0x08UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000008 */ +#define HSP_TCUCFGR_TSKCMP0_4 (0x10UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000010 */ +#define HSP_TCUCFGR_TSKCMP0_5 (0x20UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000020 */ + +#define HSP_TCUCFGR_TC0EN_Pos (7UL) +#define HSP_TCUCFGR_TC0EN_Msk (0x1UL << HSP_TCUCFGR_TC0EN_Pos) /*!< 0x00000080 */ +#define HSP_TCUCFGR_TC0EN HSP_TCUCFGR_TC0EN_Msk /*!< TC0EN (Task comparator 0 enable (1)) */ + +#define HSP_TCUCFGR_TSKCMP1_Pos (8UL) +#define HSP_TCUCFGR_TSKCMP1_Msk (0x3FUL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00003F00 */ +#define HSP_TCUCFGR_TSKCMP1 HSP_TCUCFGR_TSKCMP1_Msk /*!< TSKCMP1[5:0] bits (Task compare 1 (1)) */ +#define HSP_TCUCFGR_TSKCMP1_0 (0x01UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00000100 */ +#define HSP_TCUCFGR_TSKCMP1_1 (0x02UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00000200 */ +#define HSP_TCUCFGR_TSKCMP1_2 (0x04UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00000400 */ +#define HSP_TCUCFGR_TSKCMP1_3 (0x08UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00000800 */ +#define HSP_TCUCFGR_TSKCMP1_4 (0x10UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00001000 */ +#define HSP_TCUCFGR_TSKCMP1_5 (0x20UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00002000 */ + +#define HSP_TCUCFGR_TC1EN_Pos (15UL) +#define HSP_TCUCFGR_TC1EN_Msk (0x1UL << HSP_TCUCFGR_TC1EN_Pos) /*!< 0x00008000 */ +#define HSP_TCUCFGR_TC1EN HSP_TCUCFGR_TC1EN_Msk /*!< TC1EN (Task comparator 1 enable (1)) */ + +#define HSP_TCUCFGR_TSKCMP2_Pos (16UL) +#define HSP_TCUCFGR_TSKCMP2_Msk (0x3FUL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x003F0000 */ +#define HSP_TCUCFGR_TSKCMP2 HSP_TCUCFGR_TSKCMP2_Msk /*!< TSKCMP2[5:0] bits (Task compare 2 (1)) */ +#define HSP_TCUCFGR_TSKCMP2_0 (0x01UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00010000 */ +#define HSP_TCUCFGR_TSKCMP2_1 (0x02UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00020000 */ +#define HSP_TCUCFGR_TSKCMP2_2 (0x04UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00040000 */ +#define HSP_TCUCFGR_TSKCMP2_3 (0x08UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00080000 */ +#define HSP_TCUCFGR_TSKCMP2_4 (0x10UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00100000 */ +#define HSP_TCUCFGR_TSKCMP2_5 (0x20UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00200000 */ + +#define HSP_TCUCFGR_TC2EN_Pos (23UL) +#define HSP_TCUCFGR_TC2EN_Msk (0x1UL << HSP_TCUCFGR_TC2EN_Pos) /*!< 0x00800000 */ +#define HSP_TCUCFGR_TC2EN HSP_TCUCFGR_TC2EN_Msk /*!< TC2EN (Task comparator 2 enable (1)) */ + +#define HSP_TCUCFGR_TSKCMP3_Pos (24UL) +#define HSP_TCUCFGR_TSKCMP3_Msk (0x3FUL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x3F000000 */ +#define HSP_TCUCFGR_TSKCMP3 HSP_TCUCFGR_TSKCMP3_Msk /*!< TSKCMP3[5:0] bits (Task compare 3 (1)) */ +#define HSP_TCUCFGR_TSKCMP3_0 (0x01UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x01000000 */ +#define HSP_TCUCFGR_TSKCMP3_1 (0x02UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x02000000 */ +#define HSP_TCUCFGR_TSKCMP3_2 (0x04UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x04000000 */ +#define HSP_TCUCFGR_TSKCMP3_3 (0x08UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x08000000 */ +#define HSP_TCUCFGR_TSKCMP3_4 (0x10UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x10000000 */ +#define HSP_TCUCFGR_TSKCMP3_5 (0x20UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x20000000 */ + +#define HSP_TCUCFGR_TC3EN_Pos (31UL) +#define HSP_TCUCFGR_TC3EN_Msk (0x1UL << HSP_TCUCFGR_TC3EN_Pos) /*!< 0x80000000 */ +#define HSP_TCUCFGR_TC3EN HSP_TCUCFGR_TC3EN_Msk /*!< TC3EN (Task comparator 3 enable ) */ + +/******************** Bit definition for HSP_TOVLPCR register ********************/ +#define HSP_TOVLPCR_TOVLPEN_Pos (0UL) +#define HSP_TOVLPCR_TOVLPEN_Msk (0x1UL << HSP_TOVLPCR_TOVLPEN_Pos) /*!< 0x00000001 */ +#define HSP_TOVLPCR_TOVLPEN HSP_TOVLPCR_TOVLPEN_Msk /*!< TOVLPEN (Task overlap enable (1)) */ + +#define HSP_TOVLPCR_LTNB_Pos (8UL) +#define HSP_TOVLPCR_LTNB_Msk (0x3FUL << HSP_TOVLPCR_LTNB_Pos) /*!< 0x00003F00 */ +#define HSP_TOVLPCR_LTNB HSP_TOVLPCR_LTNB_Msk /*!< LTNB[5:0] bits (Lower task number value (1)) */ + +#define HSP_TOVLPCR_HTNB_Pos (16UL) +#define HSP_TOVLPCR_HTNB_Msk (0x3FUL << HSP_TOVLPCR_HTNB_Pos) /*!< 0x003F0000 */ +#define HSP_TOVLPCR_HTNB HSP_TOVLPCR_HTNB_Msk /*!< HTNB[5:0] bits (Higher task number value ) */ + +/******************** Bit definition for HSP_SNPR register ********************/ +#define HSP_SNPR_SNPSELA_Pos (0UL) +#define HSP_SNPR_SNPSELA_Msk (0x7UL << HSP_SNPR_SNPSELA_Pos) /*!< 0x00000007 */ +#define HSP_SNPR_SNPSELA HSP_SNPR_SNPSELA_Msk /*!< SNPSELA[2:0] bits (Snoop group A signal selection) */ +#define HSP_SNPR_SNPSELA_0 (0x1UL << HSP_SNPR_SNPSELA_Pos) /*!< 0x00000001 */ +#define HSP_SNPR_SNPSELA_1 (0x2UL << HSP_SNPR_SNPSELA_Pos) /*!< 0x00000002 */ +#define HSP_SNPR_SNPSELA_2 (0x4UL << HSP_SNPR_SNPSELA_Pos) /*!< 0x00000004 */ + +#define HSP_SNPR_SNPSELB_Pos (4UL) +#define HSP_SNPR_SNPSELB_Msk (0x7UL << HSP_SNPR_SNPSELB_Pos) /*!< 0x00000070 */ +#define HSP_SNPR_SNPSELB HSP_SNPR_SNPSELB_Msk /*!< SNPSELB[2:0] bits (Snoop group B signal selection) */ +#define HSP_SNPR_SNPSELB_0 (0x1UL << HSP_SNPR_SNPSELB_Pos) /*!< 0x00000010 */ +#define HSP_SNPR_SNPSELB_1 (0x2UL << HSP_SNPR_SNPSELB_Pos) /*!< 0x00000020 */ +#define HSP_SNPR_SNPSELB_2 (0x4UL << HSP_SNPR_SNPSELB_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for HSP_CCNTR register ********************/ +#define HSP_CCNTR_CCNTR_Pos (0UL) +#define HSP_CCNTR_CCNTR_Msk (0xFFFFFFFFUL << HSP_CCNTR_CCNTR_Pos) /*!< 0xFFFFFFFF */ +#define HSP_CCNTR_CCNTR HSP_CCNTR_CCNTR_Msk /*!< CCNTR[31:0] bits (Conflict counter) */ + +/****************** Bit definition for HSP_CAPDR register *******************/ +#define HSP_CAPDR_TSTAMP_Pos (0UL) +#define HSP_CAPDR_TSTAMP_Msk (0x3FFFUL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00003FFF */ +#define HSP_CAPDR_TSTAMP HSP_CAPDR_TSTAMP_Msk /*!< Time-stamp value */ +#define HSP_CAPDR_IFHIST_Pos (14UL) +#define HSP_CAPDR_IFHIST_Msk (0xFFUL << HSP_CAPDR_IFHIST_Pos) /*!< 0x003FC000 */ +#define HSP_CAPDR_IFHIST HSP_CAPDR_IFHIST_Msk /*!< IF condition history */ +#define HSP_CAPDR_IFCNT_Pos (22UL) +#define HSP_CAPDR_IFCNT_Msk (0xFUL << HSP_CAPDR_IFCNT_Pos) /*!< 0x03C00000 */ +#define HSP_CAPDR_IFCNT HSP_CAPDR_IFCNT_Msk /*!< IF instruction counter */ +#define HSP_CAPDR_TSKNB_Pos (26UL) +#define HSP_CAPDR_TSKNB_Msk (0x3FUL << HSP_CAPDR_TSKNB_Pos) /*!< 0xFC000000 */ +#define HSP_CAPDR_TSKNB HSP_CAPDR_TSKNB_Msk /*!< Last captured task number */ + +#define HSP_CAPDR_ALT_IFHIST_Pos (0UL) +#define HSP_CAPDR_ALT_IFHIST_Msk (0x7FFFUL << HSP_CAPDR_ALT_IFHIST_Pos) /*!< 0x00007FFF */ +#define HSP_CAPDR_ALT_IFHIST HSP_CAPDR_IFHIST_Msk /*!< IF condition history */ +#define HSP_CAPDR_ALT_PFCTNB_Pos (16UL) +#define HSP_CAPDR_ALT_PFCTNB_Msk (0x3FUL << HSP_CAPDR_ALT_PFCTNB_Pos) /*!< 0x0003F0000 */ +#define HSP_CAPDR_ALT_PFCTNB HSP_CAPDR_TSTAMP_Msk /*!< Processing Function Number */ +#define HSP_CAPDR_ALT_IFCNT_Pos (22UL) +#define HSP_CAPDR_ALT_IFCNT_Msk (0xFUL << HSP_CAPDR_ALT_IFCNT_Pos) /*!< 0x03C00000 */ +#define HSP_CAPDR_ALT_IFCNT HSP_CAPDR_IFCNT_Msk /*!< IF instruction counter */ +#define HSP_CAPDR_ALT_TSKNB_Pos (26UL) +#define HSP_CAPDR_ALT_TSKNB_Msk (0x3FUL << HSP_CAPDR_ALT_TSKNB_Pos) /*!< 0xFC000000 */ +#define HSP_CAPDR_ALT_TSKNB HSP_CAPDR_TSKNB_Msk /*!< Last captured task number */ + +/******************** Bit definition for HSP_CAPCR register ********************/ +#define HSP_CAPCR_CAPMOD_Pos (0UL) +#define HSP_CAPCR_CAPMOD_Msk (0x3UL << HSP_CAPCR_CAPMOD_Pos) /*!< 0x00000003 */ +#define HSP_CAPCR_CAPMOD HSP_CAPCR_CAPMOD_Msk /*!< CAPMOD[1:0] bits (Capture mode ) */ +#define HSP_CAPCR_CAPMOD_0 (0x1UL << HSP_CAPCR_CAPMOD_Pos) /*!< 0x00000001 */ +#define HSP_CAPCR_CAPMOD_1 (0x2UL << HSP_CAPCR_CAPMOD_Pos) /*!< 0x00000002 */ + +#define HSP_CAPCR_FRCNTEN_Pos (2UL) +#define HSP_CAPCR_FRCNTEN_Msk (0x1UL << HSP_CAPCR_FRCNTEN_Pos) /*!< 0x00000004 */ +#define HSP_CAPCR_FRCNTEN HSP_CAPCR_FRCNTEN_Msk /*!< FRCNTEN (Free-running counter enable ) */ + +#define HSP_CAPCR_PRESC_Pos (4UL) +#define HSP_CAPCR_PRESC_Msk (0x1FUL << HSP_CAPCR_PRESC_Pos) /*!< 0x000001F0 */ +#define HSP_CAPCR_PRESC HSP_CAPCR_PRESC_Msk /*!< PRESC[4:0] bits (Time-stamp prescaler value ) */ +#define HSP_CAPCR_PRESC_0 (0x01UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000010 */ +#define HSP_CAPCR_PRESC_1 (0x02UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000020 */ +#define HSP_CAPCR_PRESC_2 (0x04UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000040 */ +#define HSP_CAPCR_PRESC_3 (0x08UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000080 */ +#define HSP_CAPCR_PRESC_4 (0x10UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000100 */ + +#define HSP_CAPCR_TSKFLT_Pos (12UL) +#define HSP_CAPCR_TSKFLT_Msk (0x1UL << HSP_CAPCR_TSKFLT_Pos) /*!< 0x00001000 */ +#define HSP_CAPCR_TSKFLT HSP_CAPCR_TSKFLT_Msk /*!< TSKFLT (Task filter enable (1)) */ + +#define HSP_CAPCR_CCNTREN_Pos (16UL) +#define HSP_CAPCR_CCNTREN_Msk (0x1UL << HSP_CAPCR_CCNTREN_Pos) /*!< 0x00010000 */ +#define HSP_CAPCR_CCNTREN HSP_CAPCR_CCNTREN_Msk /*!< CCNTREN (Conflict counter enable ) */ + +/******************** Bit definition for HSP_ERR_IER register ********************/ +#define HSP_ERR_IER_TRGIOVRIE_Pos (8UL) +#define HSP_ERR_IER_TRGIOVRIE_Msk (0x1UL << HSP_ERR_IER_TRGIOVRIE_Pos) /*!< 0x00000100 */ +#define HSP_ERR_IER_TRGIOVRIE HSP_ERR_IER_TRGIOVRIE_Msk /*!< TRGIOVRIE (TRGITF overrun interrupt enable) */ + +#define HSP_ERR_IER_B0ERRIE_Pos (12UL) +#define HSP_ERR_IER_B0ERRIE_Msk (0x1UL << HSP_ERR_IER_B0ERRIE_Pos) /*!< 0x00001000 */ +#define HSP_ERR_IER_B0ERRIE HSP_ERR_IER_B0ERRIE_Msk /*!< B0ERRIE (H2CBUFF0 underrun or C2HBUFF0 overrun interrupt enable) */ + +#define HSP_ERR_IER_B1ERRIE_Pos (13UL) +#define HSP_ERR_IER_B1ERRIE_Msk (0x1UL << HSP_ERR_IER_B1ERRIE_Pos) /*!< 0x00002000 */ +#define HSP_ERR_IER_B1ERRIE HSP_ERR_IER_B1ERRIE_Msk /*!< B1ERRIE (H2CBUFF1 underrun or C2HBUFF1 overrun interrupt enable) */ + +#define HSP_ERR_IER_B2ERRIE_Pos (14UL) +#define HSP_ERR_IER_B2ERRIE_Msk (0x1UL << HSP_ERR_IER_B2ERRIE_Pos) /*!< 0x00004000 */ +#define HSP_ERR_IER_B2ERRIE HSP_ERR_IER_B2ERRIE_Msk /*!< B2ERRIE (H2CBUFF2 underrun or C2HBUFF2 overrun interrupt enable) */ + +#define HSP_ERR_IER_B3ERRIE_Pos (15UL) +#define HSP_ERR_IER_B3ERRIE_Msk (0x1UL << HSP_ERR_IER_B3ERRIE_Pos) /*!< 0x00008000 */ +#define HSP_ERR_IER_B3ERRIE HSP_ERR_IER_B3ERRIE_Msk /*!< B3ERRIE (H2CBUFF3 underrun or C2HBUFF3 overrun interrupt enable) */ + +#define HSP_ERR_IER_CAPOVRIE_Pos (16UL) +#define HSP_ERR_IER_CAPOVRIE_Msk (0x1UL << HSP_ERR_IER_CAPOVRIE_Pos) /*!< 0x00010000 */ +#define HSP_ERR_IER_CAPOVRIE HSP_ERR_IER_CAPOVRIE_Msk /*!< CAPOVRIE (Capture register overrun interrupt enable) */ + +#define HSP_ERR_IER_FWERRIE_Pos (17UL) +#define HSP_ERR_IER_FWERRIE_Msk (0x1UL << HSP_ERR_IER_FWERRIE_Pos) /*!< 0x00020000 */ +#define HSP_ERR_IER_FWERRIE HSP_ERR_IER_FWERRIE_Msk /*!< FWERRIE (Firmware error interrupt enable) */ + +#define HSP_ERR_IER_SCHERRIE_Pos (18UL) +#define HSP_ERR_IER_SCHERRIE_Msk (0x1UL << HSP_ERR_IER_SCHERRIE_Pos) /*!< 0x00040000 */ +#define HSP_ERR_IER_SCHERRIE HSP_ERR_IER_SCHERRIE_Msk /*!< SCHERRIE (Scheduler error interrupt enable) */ + +#define HSP_ERR_IER_BKINIE_Pos (19UL) +#define HSP_ERR_IER_BKINIE_Msk (0x1UL << HSP_ERR_IER_BKINIE_Pos) /*!< 0x00080000 */ +#define HSP_ERR_IER_BKINIE HSP_ERR_IER_BKINIE_Msk /*!< BKINIE (Break input interrupt enable) */ + +#define HSP_ERR_IER_HDEGOVRIE_Pos (20UL) +#define HSP_ERR_IER_HDEGOVRIE_Msk (0x1UL << HSP_ERR_IER_HDEGOVRIE_Pos) /*!< 0x00100000 */ +#define HSP_ERR_IER_HDEGOVRIE HSP_ERR_IER_HDEGOVRIE_Msk /*!< HDEGOVRIE (SPE event overrun interrupt enable) */ + +#define HSP_ERR_IER_OPCOERRIE_Pos (22UL) +#define HSP_ERR_IER_OPCOERRIE_Msk (0x1UL << HSP_ERR_IER_OPCOERRIE_Pos) /*!< 0x00400000 */ +#define HSP_ERR_IER_OPCOERRIE HSP_ERR_IER_OPCOERRIE_Msk /*!< OPCOERRIE (Invalid Op. code error interrupt enable) */ + +#define HSP_ERR_IER_ACCERRIE_Pos (23UL) +#define HSP_ERR_IER_ACCERRIE_Msk (0x1UL << HSP_ERR_IER_ACCERRIE_Pos) /*!< 0x00800000 */ +#define HSP_ERR_IER_ACCERRIE HSP_ERR_IER_ACCERRIE_Msk /*!< ACCERRIE (SPE access error interrupt enable) */ + +#define HSP_ERR_IER_UDFIE_Pos (24UL) +#define HSP_ERR_IER_UDFIE_Msk (0x1UL << HSP_ERR_IER_UDFIE_Pos) /*!< 0x01000000 */ +#define HSP_ERR_IER_UDFIE HSP_ERR_IER_UDFIE_Msk /*!< UDFIE (FPU Underflow exception interrupt enable) */ + +#define HSP_ERR_IER_OVFIE_Pos (25UL) +#define HSP_ERR_IER_OVFIE_Msk (0x1UL << HSP_ERR_IER_OVFIE_Pos) /*!< 0x02000000 */ +#define HSP_ERR_IER_OVFIE HSP_ERR_IER_OVFIE_Msk /*!< OVFIE (FPU Overflow exception interrupt enable) */ + +#define HSP_ERR_IER_DBZIE_Pos (26UL) +#define HSP_ERR_IER_DBZIE_Msk (0x1UL << HSP_ERR_IER_DBZIE_Pos) /*!< 0x04000000 */ +#define HSP_ERR_IER_DBZIE HSP_ERR_IER_DBZIE_Msk /*!< DBZIE (FPU division-by-zero exception interrupt enable) */ + +#define HSP_ERR_IER_INVIE_Pos (27UL) +#define HSP_ERR_IER_INVIE_Msk (0x1UL << HSP_ERR_IER_INVIE_Pos) /*!< 0x08000000 */ +#define HSP_ERR_IER_INVIE HSP_ERR_IER_INVIE_Msk /*!< INVIE (FPU Invalid exception interrupt enable) */ + +#define HSP_ERR_IER_DENORMIE_Pos (28UL) +#define HSP_ERR_IER_DENORMIE_Msk (0x1UL << HSP_ERR_IER_DENORMIE_Pos) /*!< 0x10000000 */ +#define HSP_ERR_IER_DENORMIE HSP_ERR_IER_DENORMIE_Msk /*!< DENORMIE (FPU denormal interrupt enable) */ + +/******************** Bit definition for HSP_EVT_IER register ********************/ +#define HSP_EVT_IER_H2CMRDYIE_Pos (0UL) +#define HSP_EVT_IER_H2CMRDYIE_Msk (0x1UL << HSP_EVT_IER_H2CMRDYIE_Pos) /*!< 0x00000001 */ +#define HSP_EVT_IER_H2CMRDYIE HSP_EVT_IER_H2CMRDYIE_Msk /*!< H2CMRDYIE (HSP to CPU message ready interrupt enable) */ + +#define HSP_EVT_IER_C2HMFREEIE_Pos (1UL) +#define HSP_EVT_IER_C2HMFREEIE_Msk (0x1UL << HSP_EVT_IER_C2HMFREEIE_Pos) /*!< 0x00000002 */ +#define HSP_EVT_IER_C2HMFREEIE HSP_EVT_IER_C2HMFREEIE_Msk /*!< C2HMFREEIE (CPU to HSP message box free interrupt enable) */ + +#define HSP_EVT_IER_DCDONEIE_Pos (2UL) +#define HSP_EVT_IER_DCDONEIE_Msk (0x1UL << HSP_EVT_IER_DCDONEIE_Pos) /*!< 0x00000004 */ +#define HSP_EVT_IER_DCDONEIE HSP_EVT_IER_DCDONEIE_Msk /*!< DCDONEIE (Direct command done interrupt enable) */ + +#define HSP_EVT_IER_CAPRDYIE_Pos (4UL) +#define HSP_EVT_IER_CAPRDYIE_Msk (0x1UL << HSP_EVT_IER_CAPRDYIE_Pos) /*!< 0x00000010 */ +#define HSP_EVT_IER_CAPRDYIE HSP_EVT_IER_CAPRDYIE_Msk /*!< CAPRDYIE (Capture buffer data ready interrupt enable) */ + +#define HSP_EVT_IER_CDEGRDYIE_Pos (7UL) +#define HSP_EVT_IER_CDEGRDYIE_Msk (0x1UL << HSP_EVT_IER_CDEGRDYIE_Pos) /*!< 0x00000080 */ +#define HSP_EVT_IER_CDEGRDYIE HSP_EVT_IER_CDEGRDYIE_Msk /*!< CDEGRDYIE (CPU Dedicated event generator ready interrupt enable) */ + +#define HSP_EVT_IER_SOFWFEIE_Pos (8UL) +#define HSP_EVT_IER_SOFWFEIE_Msk (0x1UL << HSP_EVT_IER_SOFWFEIE_Pos) /*!< 0x00000100 */ +#define HSP_EVT_IER_SOFWFEIE HSP_EVT_IER_SOFWFEIE_Msk /*!< SOFWFEIE (Start of WFE interrupt enable) */ + +#define HSP_EVT_IER_EOFWFEIE_Pos (9UL) +#define HSP_EVT_IER_EOFWFEIE_Msk (0x1UL << HSP_EVT_IER_EOFWFEIE_Pos) /*!< 0x00000200 */ +#define HSP_EVT_IER_EOFWFEIE HSP_EVT_IER_EOFWFEIE_Msk /*!< EOFWFEIE (End of WFE interrupt enable) */ + +#define HSP_EVT_IER_B0EVTIE_Pos (12UL) +#define HSP_EVT_IER_B0EVTIE_Msk (0x1UL << HSP_EVT_IER_B0EVTIE_Pos) /*!< 0x00001000 */ +#define HSP_EVT_IER_B0EVTIE HSP_EVT_IER_B0EVTIE_Msk /*!< B0EVTIE (BUFF0 event interrupt enable) */ + +#define HSP_EVT_IER_B1EVTIE_Pos (13UL) +#define HSP_EVT_IER_B1EVTIE_Msk (0x1UL << HSP_EVT_IER_B1EVTIE_Pos) /*!< 0x00002000 */ +#define HSP_EVT_IER_B1EVTIE HSP_EVT_IER_B1EVTIE_Msk /*!< B1EVTIE (BUFF1 event interrupt enable) */ + +#define HSP_EVT_IER_B2EVTIE_Pos (14UL) +#define HSP_EVT_IER_B2EVTIE_Msk (0x1UL << HSP_EVT_IER_B2EVTIE_Pos) /*!< 0x00004000 */ +#define HSP_EVT_IER_B2EVTIE HSP_EVT_IER_B2EVTIE_Msk /*!< B2EVTIE (BUFF2 event interrupt enable) */ + +#define HSP_EVT_IER_B3EVTIE_Pos (15UL) +#define HSP_EVT_IER_B3EVTIE_Msk (0x1UL << HSP_EVT_IER_B3EVTIE_Pos) /*!< 0x00008000 */ +#define HSP_EVT_IER_B3EVTIE HSP_EVT_IER_B3EVTIE_Msk /*!< B3EVTIE (BUFF3 event interrupt enable) */ + +#define HSP_EVT_IER_SOTECP0IE_Pos (16UL) +#define HSP_EVT_IER_SOTECP0IE_Msk (0x1UL << HSP_EVT_IER_SOTECP0IE_Pos) /*!< 0x00010000 */ +#define HSP_EVT_IER_SOTECP0IE HSP_EVT_IER_SOTECP0IE_Msk /*!< SOTECP0IE (Start of task generated by event comparator 0 interrupt enable) */ + +#define HSP_EVT_IER_SOTECP1IE_Pos (17UL) +#define HSP_EVT_IER_SOTECP1IE_Msk (0x1UL << HSP_EVT_IER_SOTECP1IE_Pos) /*!< 0x00020000 */ +#define HSP_EVT_IER_SOTECP1IE HSP_EVT_IER_SOTECP1IE_Msk /*!< SOTECP1IE (Start of task generated by event comparator 1 interrupt enable) */ + +#define HSP_EVT_IER_SOTECP2IE_Pos (18UL) +#define HSP_EVT_IER_SOTECP2IE_Msk (0x1UL << HSP_EVT_IER_SOTECP2IE_Pos) /*!< 0x00040000 */ +#define HSP_EVT_IER_SOTECP2IE HSP_EVT_IER_SOTECP2IE_Msk /*!< SOTECP2IE (Start of task generated by event comparator 2 interrupt enable) */ + +#define HSP_EVT_IER_SOTECP3IE_Pos (19UL) +#define HSP_EVT_IER_SOTECP3IE_Msk (0x1UL << HSP_EVT_IER_SOTECP3IE_Pos) /*!< 0x00080000 */ +#define HSP_EVT_IER_SOTECP3IE HSP_EVT_IER_SOTECP3IE_Msk /*!< SOTECP3IE (Start of task generated by event comparator 3 interrupt enable) */ + +#define HSP_EVT_IER_EOTECP0IE_Pos (20UL) +#define HSP_EVT_IER_EOTECP0IE_Msk (0x1UL << HSP_EVT_IER_EOTECP0IE_Pos) /*!< 0x00100000 */ +#define HSP_EVT_IER_EOTECP0IE HSP_EVT_IER_EOTECP0IE_Msk /*!< EOTECP0IE (End of task generated by event comparator 0 interrupt enable) */ + +#define HSP_EVT_IER_EOTECP1IE_Pos (21UL) +#define HSP_EVT_IER_EOTECP1IE_Msk (0x1UL << HSP_EVT_IER_EOTECP1IE_Pos) /*!< 0x00200000 */ +#define HSP_EVT_IER_EOTECP1IE HSP_EVT_IER_EOTECP1IE_Msk /*!< EOTECP1IE (End of task generated by event comparator 1 interrupt enable) */ + +#define HSP_EVT_IER_EOTECP2IE_Pos (22UL) +#define HSP_EVT_IER_EOTECP2IE_Msk (0x1UL << HSP_EVT_IER_EOTECP2IE_Pos) /*!< 0x00400000 */ +#define HSP_EVT_IER_EOTECP2IE HSP_EVT_IER_EOTECP2IE_Msk /*!< EOTECP2IE (End of task generated by event comparator 2 interrupt enable) */ + +#define HSP_EVT_IER_EOTECP3IE_Pos (23UL) +#define HSP_EVT_IER_EOTECP3IE_Msk (0x1UL << HSP_EVT_IER_EOTECP3IE_Pos) /*!< 0x00800000 */ +#define HSP_EVT_IER_EOTECP3IE HSP_EVT_IER_EOTECP3IE_Msk /*!< EOTECP3IE (End of task generated by event comparator 3 interrupt enable) */ + +#define HSP_EVT_IER_TOVLPIE_Pos (28UL) +#define HSP_EVT_IER_TOVLPIE_Msk (0x1UL << HSP_EVT_IER_TOVLPIE_Pos) /*!< 0x10000000 */ +#define HSP_EVT_IER_TOVLPIE HSP_EVT_IER_TOVLPIE_Msk /*!< TOVLPIE (Task overlap flag interrupt enable) */ + +#define HSP_EVT_IER_FPUSATIE_Pos (31UL) +#define HSP_EVT_IER_FPUSATIE_Msk (0x1UL << HSP_EVT_IER_FPUSATIE_Pos) /*!< 0x80000000 */ +#define HSP_EVT_IER_FPUSATIE HSP_EVT_IER_FPUSATIE_Msk /*!< FPUSATIE (Saturation flag interrupt enable) */ + +/******************** Bit definition for HSP_PFCTEVT_IER register ********************/ +#define HSP_PFCTEVT_IER_PFCTIE_Pos (0UL) +#define HSP_PFCTEVT_IER_PFCTIE_Msk (0xFFFFFFFFUL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PFCTEVT_IER_PFCTIE HSP_PFCTEVT_IER_PFCTIE_Msk /*!< PFCTIE[31:0] bits (Processing function flags interrupt enable) */ +#define HSP_PFCTEVT_IER_PFCTIE_0 (0x00001UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000001 */ +#define HSP_PFCTEVT_IER_PFCTIE_1 (0x00002UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000002 */ +#define HSP_PFCTEVT_IER_PFCTIE_2 (0x00004UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000004 */ +#define HSP_PFCTEVT_IER_PFCTIE_3 (0x00008UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000008 */ +#define HSP_PFCTEVT_IER_PFCTIE_4 (0x00010UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000010 */ +#define HSP_PFCTEVT_IER_PFCTIE_5 (0x00020UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000020 */ +#define HSP_PFCTEVT_IER_PFCTIE_6 (0x00040UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000040 */ +#define HSP_PFCTEVT_IER_PFCTIE_7 (0x00080UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000080 */ +#define HSP_PFCTEVT_IER_PFCTIE_8 (0x00100UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000100 */ +#define HSP_PFCTEVT_IER_PFCTIE_9 (0x00200UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000200 */ +#define HSP_PFCTEVT_IER_PFCTIE_10 (0x00400UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000400 */ +#define HSP_PFCTEVT_IER_PFCTIE_11 (0x00800UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000800 */ +#define HSP_PFCTEVT_IER_PFCTIE_12 (0x01000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00001000 */ +#define HSP_PFCTEVT_IER_PFCTIE_13 (0x02000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00002000 */ +#define HSP_PFCTEVT_IER_PFCTIE_14 (0x04000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00004000 */ +#define HSP_PFCTEVT_IER_PFCTIE_15 (0x08000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00008000 */ +#define HSP_PFCTEVT_IER_PFCTIE_16 (0x10000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00010000 */ +#define HSP_PFCTEVT_IER_PFCTIE_17 (0x20000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00020000 */ +#define HSP_PFCTEVT_IER_PFCTIE_18 (0x40000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00040000 */ +#define HSP_PFCTEVT_IER_PFCTIE_19 (0x80000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00080000 */ +#define HSP_PFCTEVT_IER_PFCTIE_20 (0x100000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00100000 */ +#define HSP_PFCTEVT_IER_PFCTIE_21 (0x200000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00200000 */ +#define HSP_PFCTEVT_IER_PFCTIE_22 (0x400000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00400000 */ +#define HSP_PFCTEVT_IER_PFCTIE_23 (0x800000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00800000 */ +#define HSP_PFCTEVT_IER_PFCTIE_24 (0x1000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x01000000 */ +#define HSP_PFCTEVT_IER_PFCTIE_25 (0x2000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x02000000 */ +#define HSP_PFCTEVT_IER_PFCTIE_26 (0x4000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x04000000 */ +#define HSP_PFCTEVT_IER_PFCTIE_27 (0x8000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x08000000 */ +#define HSP_PFCTEVT_IER_PFCTIE_28 (0x10000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x10000000 */ +#define HSP_PFCTEVT_IER_PFCTIE_29 (0x20000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x20000000 */ +#define HSP_PFCTEVT_IER_PFCTIE_30 (0x40000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x40000000 */ +#define HSP_PFCTEVT_IER_PFCTIE_31 (0x80000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for HSP_ERR_ISR register ********************/ +#define HSP_ERR_ISR_TRGIOVRF_Pos (8UL) +#define HSP_ERR_ISR_TRGIOVRF_Msk (0x1UL << HSP_ERR_ISR_TRGIOVRF_Pos) /*!< 0x00000100 */ +#define HSP_ERR_ISR_TRGIOVRF HSP_ERR_ISR_TRGIOVRF_Msk /*!< TRGIOVRF (TRGITF overrun flag) */ + +#define HSP_ERR_ISR_B0ERRF_Pos (12UL) +#define HSP_ERR_ISR_B0ERRF_Msk (0x1UL << HSP_ERR_ISR_B0ERRF_Pos) /*!< 0x00001000 */ +#define HSP_ERR_ISR_B0ERRF HSP_ERR_ISR_B0ERRF_Msk /*!< B0ERRF (H2CBUFF0 underrun or C2HBUFF0 overrun flag) */ + +#define HSP_ERR_ISR_B1ERRF_Pos (13UL) +#define HSP_ERR_ISR_B1ERRF_Msk (0x1UL << HSP_ERR_ISR_B1ERRF_Pos) /*!< 0x00002000 */ +#define HSP_ERR_ISR_B1ERRF HSP_ERR_ISR_B1ERRF_Msk /*!< B1ERRF (H2CBUFF1 underrun or C2HBUFF1 overrun flag) */ + +#define HSP_ERR_ISR_B2ERRF_Pos (14UL) +#define HSP_ERR_ISR_B2ERRF_Msk (0x1UL << HSP_ERR_ISR_B2ERRF_Pos) /*!< 0x00004000 */ +#define HSP_ERR_ISR_B2ERRF HSP_ERR_ISR_B2ERRF_Msk /*!< B2ERRF (H2CBUFF2 underrun or C2HBUFF2 overrun flag) */ + +#define HSP_ERR_ISR_B3ERRF_Pos (15UL) +#define HSP_ERR_ISR_B3ERRF_Msk (0x1UL << HSP_ERR_ISR_B3ERRF_Pos) /*!< 0x00008000 */ +#define HSP_ERR_ISR_B3ERRF HSP_ERR_ISR_B3ERRF_Msk /*!< B3ERRF (H2CBUFF3 underrun or C2HBUFF3 overrun flag) */ + +#define HSP_ERR_ISR_CAPOVRF_Pos (16UL) +#define HSP_ERR_ISR_CAPOVRF_Msk (0x1UL << HSP_ERR_ISR_CAPOVRF_Pos) /*!< 0x00010000 */ +#define HSP_ERR_ISR_CAPOVRF HSP_ERR_ISR_CAPOVRF_Msk /*!< CAPOVRF (Capture register overrun flag) */ + +#define HSP_ERR_ISR_FWERRF_Pos (17UL) +#define HSP_ERR_ISR_FWERRF_Msk (0x1UL << HSP_ERR_ISR_FWERRF_Pos) /*!< 0x00020000 */ +#define HSP_ERR_ISR_FWERRF HSP_ERR_ISR_FWERRF_Msk /*!< FWERRF (Firmware error flag) */ + +#define HSP_ERR_ISR_SCHERRF_Pos (18UL) +#define HSP_ERR_ISR_SCHERRF_Msk (0x1UL << HSP_ERR_ISR_SCHERRF_Pos) /*!< 0x00040000 */ +#define HSP_ERR_ISR_SCHERRF HSP_ERR_ISR_SCHERRF_Msk /*!< SCHERRF (Scheduler error flag) */ + +#define HSP_ERR_ISR_BKINF_Pos (19UL) +#define HSP_ERR_ISR_BKINF_Msk (0x1UL << HSP_ERR_ISR_BKINF_Pos) /*!< 0x00080000 */ +#define HSP_ERR_ISR_BKINF HSP_ERR_ISR_BKINF_Msk /*!< BKINF (Break input flag) */ + +#define HSP_ERR_ISR_HDEGOVRF_Pos (20UL) +#define HSP_ERR_ISR_HDEGOVRF_Msk (0x1UL << HSP_ERR_ISR_HDEGOVRF_Pos) /*!< 0x00100000 */ +#define HSP_ERR_ISR_HDEGOVRF HSP_ERR_ISR_HDEGOVRF_Msk /*!< HDEGOVRF (SPE event overrun flag) */ + +#define HSP_ERR_ISR_OPCOERRF_Pos (22UL) +#define HSP_ERR_ISR_OPCOERRF_Msk (0x1UL << HSP_ERR_ISR_OPCOERRF_Pos) /*!< 0x00400000 */ +#define HSP_ERR_ISR_OPCOERRF HSP_ERR_ISR_OPCOERRF_Msk /*!< OPCOERRF (Invalid OpCode error flag) */ + +#define HSP_ERR_ISR_ACCERRF_Pos (23UL) +#define HSP_ERR_ISR_ACCERRF_Msk (0x1UL << HSP_ERR_ISR_ACCERRF_Pos) /*!< 0x00800000 */ +#define HSP_ERR_ISR_ACCERRF HSP_ERR_ISR_ACCERRF_Msk /*!< ACCERRF (SPE Access error flag) */ + +#define HSP_ERR_ISR_FPUERRF_Pos (24UL) +#define HSP_ERR_ISR_FPUERRF_Msk (0x1UL << HSP_ERR_ISR_FPUERRF_Pos) /*!< 0x01000000 */ +#define HSP_ERR_ISR_FPUERRF HSP_ERR_ISR_FPUERRF_Msk /*!< FPUERRF (Computation error flag) */ + +/******************** Bit definition for HSP_EVT_ISR register ********************/ +#define HSP_EVT_ISR_H2CMRDYF_Pos (0UL) +#define HSP_EVT_ISR_H2CMRDYF_Msk (0x1UL << HSP_EVT_ISR_H2CMRDYF_Pos) /*!< 0x00000001 */ +#define HSP_EVT_ISR_H2CMRDYF HSP_EVT_ISR_H2CMRDYF_Msk /*!< H2CMRDYF (HSP to CPU message ready flag) */ + +#define HSP_EVT_ISR_C2HMFREEF_Pos (1UL) +#define HSP_EVT_ISR_C2HMFREEF_Msk (0x1UL << HSP_EVT_ISR_C2HMFREEF_Pos) /*!< 0x00000002 */ +#define HSP_EVT_ISR_C2HMFREEF HSP_EVT_ISR_C2HMFREEF_Msk /*!< C2HMFREEF (CPU to HSP message box free flag) */ + +#define HSP_EVT_ISR_DCDONEF_Pos (2UL) +#define HSP_EVT_ISR_DCDONEF_Msk (0x1UL << HSP_EVT_ISR_DCDONEF_Pos) /*!< 0x00000004 */ +#define HSP_EVT_ISR_DCDONEF HSP_EVT_ISR_DCDONEF_Msk /*!< DCDONEF (Direct command done flag) */ + +#define HSP_EVT_ISR_CAPRDYF_Pos (4UL) +#define HSP_EVT_ISR_CAPRDYF_Msk (0x1UL << HSP_EVT_ISR_CAPRDYF_Pos) /*!< 0x00000010 */ +#define HSP_EVT_ISR_CAPRDYF HSP_EVT_ISR_CAPRDYF_Msk /*!< CAPRDYF (Capture buffer data ready flag) */ + +#define HSP_EVT_ISR_CDEGRDYF_Pos (7UL) +#define HSP_EVT_ISR_CDEGRDYF_Msk (0x1UL << HSP_EVT_ISR_CDEGRDYF_Pos) /*!< 0x00000080 */ +#define HSP_EVT_ISR_CDEGRDYF HSP_EVT_ISR_CDEGRDYF_Msk /*!< CDEGRDYF (CPU Dedicated event generator ready flag) */ + +#define HSP_EVT_ISR_SOFWFEF_Pos (8UL) +#define HSP_EVT_ISR_SOFWFEF_Msk (0x1UL << HSP_EVT_ISR_SOFWFEF_Pos) /*!< 0x00000100 */ +#define HSP_EVT_ISR_SOFWFEF HSP_EVT_ISR_SOFWFEF_Msk /*!< SOFWFEF (Start of WFE flag) */ + +#define HSP_EVT_ISR_EOFWFEF_Pos (9UL) +#define HSP_EVT_ISR_EOFWFEF_Msk (0x1UL << HSP_EVT_ISR_EOFWFEF_Pos) /*!< 0x00000200 */ +#define HSP_EVT_ISR_EOFWFEF HSP_EVT_ISR_EOFWFEF_Msk /*!< EOFWFEF (End of WFE flag) */ + +#define HSP_EVT_ISR_B0EVTF_Pos (12UL) +#define HSP_EVT_ISR_B0EVTF_Msk (0x1UL << HSP_EVT_ISR_B0EVTF_Pos) /*!< 0x00001000 */ +#define HSP_EVT_ISR_B0EVTF HSP_EVT_ISR_B0EVTF_Msk /*!< B0EVTF (BUFF0 event flag) */ + +#define HSP_EVT_ISR_B1EVTF_Pos (13UL) +#define HSP_EVT_ISR_B1EVTF_Msk (0x1UL << HSP_EVT_ISR_B1EVTF_Pos) /*!< 0x00002000 */ +#define HSP_EVT_ISR_B1EVTF HSP_EVT_ISR_B1EVTF_Msk /*!< B1EVTF (BUFF1 event flag) */ + +#define HSP_EVT_ISR_B2EVTF_Pos (14UL) +#define HSP_EVT_ISR_B2EVTF_Msk (0x1UL << HSP_EVT_ISR_B2EVTF_Pos) /*!< 0x00004000 */ +#define HSP_EVT_ISR_B2EVTF HSP_EVT_ISR_B2EVTF_Msk /*!< B2EVTF (BUFF2 event flag) */ + +#define HSP_EVT_ISR_B3EVTF_Pos (15UL) +#define HSP_EVT_ISR_B3EVTF_Msk (0x1UL << HSP_EVT_ISR_B3EVTF_Pos) /*!< 0x00008000 */ +#define HSP_EVT_ISR_B3EVTF HSP_EVT_ISR_B3EVTF_Msk /*!< B3EVTF (BUFF3 event flag) */ + +#define HSP_EVT_ISR_SOTECP0F_Pos (16UL) +#define HSP_EVT_ISR_SOTECP0F_Msk (0x1UL << HSP_EVT_ISR_SOTECP0F_Pos) /*!< 0x00010000 */ +#define HSP_EVT_ISR_SOTECP0F HSP_EVT_ISR_SOTECP0F_Msk /*!< SOTECP0F (Start of task flag, for event comparator 0) */ + +#define HSP_EVT_ISR_SOTECP1F_Pos (17UL) +#define HSP_EVT_ISR_SOTECP1F_Msk (0x1UL << HSP_EVT_ISR_SOTECP1F_Pos) /*!< 0x00020000 */ +#define HSP_EVT_ISR_SOTECP1F HSP_EVT_ISR_SOTECP1F_Msk /*!< SOTECP1F (Start of task flag, for event comparator 1) */ + +#define HSP_EVT_ISR_SOTECP2F_Pos (18UL) +#define HSP_EVT_ISR_SOTECP2F_Msk (0x1UL << HSP_EVT_ISR_SOTECP2F_Pos) /*!< 0x00040000 */ +#define HSP_EVT_ISR_SOTECP2F HSP_EVT_ISR_SOTECP2F_Msk /*!< SOTECP2F (Start of task flag, for event comparator 2) */ + +#define HSP_EVT_ISR_SOTECP3F_Pos (19UL) +#define HSP_EVT_ISR_SOTECP3F_Msk (0x1UL << HSP_EVT_ISR_SOTECP3F_Pos) /*!< 0x00080000 */ +#define HSP_EVT_ISR_SOTECP3F HSP_EVT_ISR_SOTECP3F_Msk /*!< SOTECP3F (Start of task flag, for event comparator 3) */ + +#define HSP_EVT_ISR_EOTECP0F_Pos (20UL) +#define HSP_EVT_ISR_EOTECP0F_Msk (0x1UL << HSP_EVT_ISR_EOTECP0F_Pos) /*!< 0x00100000 */ +#define HSP_EVT_ISR_EOTECP0F HSP_EVT_ISR_EOTECP0F_Msk /*!< EOTECP0F (End of task flag, for event comparator 0) */ + +#define HSP_EVT_ISR_EOTECP1F_Pos (21UL) +#define HSP_EVT_ISR_EOTECP1F_Msk (0x1UL << HSP_EVT_ISR_EOTECP1F_Pos) /*!< 0x00200000 */ +#define HSP_EVT_ISR_EOTECP1F HSP_EVT_ISR_EOTECP1F_Msk /*!< EOTECP1F (End of task flag, for event comparator 1) */ + +#define HSP_EVT_ISR_EOTECP2F_Pos (22UL) +#define HSP_EVT_ISR_EOTECP2F_Msk (0x1UL << HSP_EVT_ISR_EOTECP2F_Pos) /*!< 0x00400000 */ +#define HSP_EVT_ISR_EOTECP2F HSP_EVT_ISR_EOTECP2F_Msk /*!< EOTECP2F (End of task flag, for event comparator 2) */ + +#define HSP_EVT_ISR_EOTECP3F_Pos (23UL) +#define HSP_EVT_ISR_EOTECP3F_Msk (0x1UL << HSP_EVT_ISR_EOTECP3F_Pos) /*!< 0x00800000 */ +#define HSP_EVT_ISR_EOTECP3F HSP_EVT_ISR_EOTECP3F_Msk /*!< EOTECP3F (End of task flag, for event comparator 3) */ + +#define HSP_EVT_ISR_TOVLPF_Pos (28UL) +#define HSP_EVT_ISR_TOVLPF_Msk (0x1UL << HSP_EVT_ISR_TOVLPF_Pos) /*!< 0x10000000 */ +#define HSP_EVT_ISR_TOVLPF HSP_EVT_ISR_TOVLPF_Msk /*!< TOVLPF (Task overlap flag) */ + +#define HSP_EVT_ISR_FPUSATF_Pos (31UL) +#define HSP_EVT_ISR_FPUSATF_Msk (0x1UL << HSP_EVT_ISR_FPUSATF_Pos) /*!< 0x80000000 */ +#define HSP_EVT_ISR_FPUSATF HSP_EVT_ISR_FPUSATF_Msk /*!< FPUSATF (FPU saturation flag) */ + +/******************** Bit definition for HSP_PFCTEVT_ISR register ********************/ +#define HSP_PFCTEVT_ISR_PFCTF_Pos (0UL) +#define HSP_PFCTEVT_ISR_PFCTF_Msk (0xFFFFFFFFUL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PFCTEVT_ISR_PFCTF HSP_PFCTEVT_ISR_PFCTF_Msk /*!< PFCTF[31:0] bits (Flags generated by SPE processing functions ) */ +#define HSP_PFCTEVT_ISR_PFCTF_0 (0x00001UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000001 */ +#define HSP_PFCTEVT_ISR_PFCTF_1 (0x00002UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000002 */ +#define HSP_PFCTEVT_ISR_PFCTF_2 (0x00004UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000004 */ +#define HSP_PFCTEVT_ISR_PFCTF_3 (0x00008UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000008 */ +#define HSP_PFCTEVT_ISR_PFCTF_4 (0x00010UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000010 */ +#define HSP_PFCTEVT_ISR_PFCTF_5 (0x00020UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000020 */ +#define HSP_PFCTEVT_ISR_PFCTF_6 (0x00040UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000040 */ +#define HSP_PFCTEVT_ISR_PFCTF_7 (0x00080UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000080 */ +#define HSP_PFCTEVT_ISR_PFCTF_8 (0x00100UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000100 */ +#define HSP_PFCTEVT_ISR_PFCTF_9 (0x00200UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000200 */ +#define HSP_PFCTEVT_ISR_PFCTF_10 (0x00400UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000400 */ +#define HSP_PFCTEVT_ISR_PFCTF_11 (0x00800UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000800 */ +#define HSP_PFCTEVT_ISR_PFCTF_12 (0x01000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00001000 */ +#define HSP_PFCTEVT_ISR_PFCTF_13 (0x02000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00002000 */ +#define HSP_PFCTEVT_ISR_PFCTF_14 (0x04000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00004000 */ +#define HSP_PFCTEVT_ISR_PFCTF_15 (0x08000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00008000 */ +#define HSP_PFCTEVT_ISR_PFCTF_16 (0x10000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00010000 */ +#define HSP_PFCTEVT_ISR_PFCTF_17 (0x20000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00020000 */ +#define HSP_PFCTEVT_ISR_PFCTF_18 (0x40000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00040000 */ +#define HSP_PFCTEVT_ISR_PFCTF_19 (0x80000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00080000 */ +#define HSP_PFCTEVT_ISR_PFCTF_20 (0x100000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00100000 */ +#define HSP_PFCTEVT_ISR_PFCTF_21 (0x200000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00200000 */ +#define HSP_PFCTEVT_ISR_PFCTF_22 (0x400000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00400000 */ +#define HSP_PFCTEVT_ISR_PFCTF_23 (0x800000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00800000 */ +#define HSP_PFCTEVT_ISR_PFCTF_24 (0x1000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x01000000 */ +#define HSP_PFCTEVT_ISR_PFCTF_25 (0x2000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x02000000 */ +#define HSP_PFCTEVT_ISR_PFCTF_26 (0x4000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x04000000 */ +#define HSP_PFCTEVT_ISR_PFCTF_27 (0x8000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x08000000 */ +#define HSP_PFCTEVT_ISR_PFCTF_28 (0x10000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x10000000 */ +#define HSP_PFCTEVT_ISR_PFCTF_29 (0x20000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x20000000 */ +#define HSP_PFCTEVT_ISR_PFCTF_30 (0x40000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x40000000 */ +#define HSP_PFCTEVT_ISR_PFCTF_31 (0x80000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for HSP_ERRINFR register ********************/ +#define HSP_ERRINFR_INEXACT_Pos (0UL) +#define HSP_ERRINFR_INEXACT_Msk (0x1UL << HSP_ERRINFR_INEXACT_Pos) /*!< 0x00000001 */ +#define HSP_ERRINFR_INEXACT HSP_ERRINFR_INEXACT_Msk /*!< INEXACT (INEXACT exception flag) */ + +#define HSP_ERRINFR_UDFLOW_Pos (1UL) +#define HSP_ERRINFR_UDFLOW_Msk (0x1UL << HSP_ERRINFR_UDFLOW_Pos) /*!< 0x00000002 */ +#define HSP_ERRINFR_UDFLOW HSP_ERRINFR_UDFLOW_Msk /*!< UDFLOW (UNDERFLOW exception flag) */ + +#define HSP_ERRINFR_OVFLOW_Pos (2UL) +#define HSP_ERRINFR_OVFLOW_Msk (0x1UL << HSP_ERRINFR_OVFLOW_Pos) /*!< 0x00000004 */ +#define HSP_ERRINFR_OVFLOW HSP_ERRINFR_OVFLOW_Msk /*!< OVFLOW (OVERFLOW exception flag) */ + +#define HSP_ERRINFR_DIVZERO_Pos (3UL) +#define HSP_ERRINFR_DIVZERO_Msk (0x1UL << HSP_ERRINFR_DIVZERO_Pos) /*!< 0x00000008 */ +#define HSP_ERRINFR_DIVZERO HSP_ERRINFR_DIVZERO_Msk /*!< DIVZERO (Division by zero exception flag) */ + +#define HSP_ERRINFR_INVALID_Pos (4UL) +#define HSP_ERRINFR_INVALID_Msk (0x1UL << HSP_ERRINFR_INVALID_Pos) /*!< 0x00000010 */ +#define HSP_ERRINFR_INVALID HSP_ERRINFR_INVALID_Msk /*!< INVALID (INVALID exception flag) */ + +#define HSP_ERRINFR_DENORM_Pos (5UL) +#define HSP_ERRINFR_DENORM_Msk (0x1UL << HSP_ERRINFR_DENORM_Pos) /*!< 0x00000020 */ +#define HSP_ERRINFR_DENORM HSP_ERRINFR_DENORM_Msk /*!< DENORM (DENORMAL exception flag) */ + +#define HSP_ERRINFR_CMERR_Pos (8UL) +#define HSP_ERRINFR_CMERR_Msk (0x1UL << HSP_ERRINFR_CMERR_Pos) /*!< 0x00000100 */ +#define HSP_ERRINFR_CMERR HSP_ERRINFR_CMERR_Msk /*!< CMERR (Code memory access error flag) */ + +#define HSP_ERRINFR_DMERR_Pos (9UL) +#define HSP_ERRINFR_DMERR_Msk (0x1UL << HSP_ERRINFR_DMERR_Pos) /*!< 0x00000200 */ +#define HSP_ERRINFR_DMERR HSP_ERRINFR_DMERR_Msk /*!< DMERR (Data memory access error flag) */ + +#define HSP_ERRINFR_MAHBERR_Pos (11UL) +#define HSP_ERRINFR_MAHBERR_Msk (0x1UL << HSP_ERRINFR_MAHBERR_Pos) /*!< 0x00000800 */ +#define HSP_ERRINFR_MAHBERR HSP_ERRINFR_MAHBERR_Msk /*!< MAHBERR (Internal AHB access error flag) */ + +#define HSP_ERRINFR_SAHBERR_Pos (12UL) +#define HSP_ERRINFR_SAHBERR_Msk (0x1UL << HSP_ERRINFR_SAHBERR_Pos) /*!< 0x00001000 */ +#define HSP_ERRINFR_SAHBERR HSP_ERRINFR_SAHBERR_Msk /*!< SAHBERR (Slave AHB access error flag) */ + +#define HSP_ERRINFR_TRGIERR_Pos (16UL) +#define HSP_ERRINFR_TRGIERR_Msk (0x3FFUL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x03FF0000 */ +#define HSP_ERRINFR_TRGIERR HSP_ERRINFR_TRGIERR_Msk /*!< TRGIERR[9:0] bits (TRGIN error information) */ +#define HSP_ERRINFR_TRGIERR_0 (0x001UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00010000 */ +#define HSP_ERRINFR_TRGIERR_1 (0x002UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00020000 */ +#define HSP_ERRINFR_TRGIERR_2 (0x004UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00040000 */ +#define HSP_ERRINFR_TRGIERR_3 (0x008UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00080000 */ +#define HSP_ERRINFR_TRGIERR_4 (0x010UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00100000 */ +#define HSP_ERRINFR_TRGIERR_5 (0x020UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00200000 */ +#define HSP_ERRINFR_TRGIERR_6 (0x040UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00400000 */ +#define HSP_ERRINFR_TRGIERR_7 (0x080UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00800000 */ +#define HSP_ERRINFR_TRGIERR_8 (0x100UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x01000000 */ +#define HSP_ERRINFR_TRGIERR_9 (0x200UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x02000000 */ + +/******************** Bit definition for HSP_ERR_ICR register ********************/ +#define HSP_ERR_ICR_TRGIOVRC_Pos (8UL) +#define HSP_ERR_ICR_TRGIOVRC_Msk (0x1UL << HSP_ERR_ICR_TRGIOVRC_Pos) /*!< 0x00000100 */ +#define HSP_ERR_ICR_TRGIOVRC HSP_ERR_ICR_TRGIOVRC_Msk /*!< TRGIOVRC (Clear TRGIOVRF flag) */ + +#define HSP_ERR_ICR_B0ERRC_Pos (12UL) +#define HSP_ERR_ICR_B0ERRC_Msk (0x1UL << HSP_ERR_ICR_B0ERRC_Pos) /*!< 0x00001000 */ +#define HSP_ERR_ICR_B0ERRC HSP_ERR_ICR_B0ERRC_Msk /*!< B0ERRC (Clear B0ERRF flag) */ + +#define HSP_ERR_ICR_B1ERRC_Pos (13UL) +#define HSP_ERR_ICR_B1ERRC_Msk (0x1UL << HSP_ERR_ICR_B1ERRC_Pos) /*!< 0x00002000 */ +#define HSP_ERR_ICR_B1ERRC HSP_ERR_ICR_B1ERRC_Msk /*!< B1ERRC (Clear B1ERRF flag) */ + +#define HSP_ERR_ICR_B2ERRC_Pos (14UL) +#define HSP_ERR_ICR_B2ERRC_Msk (0x1UL << HSP_ERR_ICR_B2ERRC_Pos) /*!< 0x00004000 */ +#define HSP_ERR_ICR_B2ERRC HSP_ERR_ICR_B2ERRC_Msk /*!< B2ERRC (Clear B2ERRF flag) */ + +#define HSP_ERR_ICR_B3ERRC_Pos (15UL) +#define HSP_ERR_ICR_B3ERRC_Msk (0x1UL << HSP_ERR_ICR_B3ERRC_Pos) /*!< 0x00008000 */ +#define HSP_ERR_ICR_B3ERRC HSP_ERR_ICR_B3ERRC_Msk /*!< B3ERRC (Clear B3ERRF flag) */ + +#define HSP_ERR_ICR_CAPOVRC_Pos (16UL) +#define HSP_ERR_ICR_CAPOVRC_Msk (0x1UL << HSP_ERR_ICR_CAPOVRC_Pos) /*!< 0x00010000 */ +#define HSP_ERR_ICR_CAPOVRC HSP_ERR_ICR_CAPOVRC_Msk /*!< CAPOVRC (Clear CAPOVRF flag) */ + +#define HSP_ERR_ICR_FWERRC_Pos (17UL) +#define HSP_ERR_ICR_FWERRC_Msk (0x1UL << HSP_ERR_ICR_FWERRC_Pos) /*!< 0x00020000 */ +#define HSP_ERR_ICR_FWERRC HSP_ERR_ICR_FWERRC_Msk /*!< FWERRC (Clear FWERRF flag) */ + +#define HSP_ERR_ICR_SCHERRC_Pos (18UL) +#define HSP_ERR_ICR_SCHERRC_Msk (0x1UL << HSP_ERR_ICR_SCHERRC_Pos) /*!< 0x00040000 */ +#define HSP_ERR_ICR_SCHERRC HSP_ERR_ICR_SCHERRC_Msk /*!< SCHERRC (Clear SCHERRF flag) */ + +#define HSP_ERR_ICR_BKINC_Pos (19UL) +#define HSP_ERR_ICR_BKINC_Msk (0x1UL << HSP_ERR_ICR_BKINC_Pos) /*!< 0x00080000 */ +#define HSP_ERR_ICR_BKINC HSP_ERR_ICR_BKINC_Msk /*!< BKINC (Clear BKINF flag) */ + +#define HSP_ERR_ICR_HDEGOVRC_Pos (20UL) +#define HSP_ERR_ICR_HDEGOVRC_Msk (0x1UL << HSP_ERR_ICR_HDEGOVRC_Pos) /*!< 0x00100000 */ +#define HSP_ERR_ICR_HDEGOVRC HSP_ERR_ICR_HDEGOVRC_Msk /*!< HDEGOVRC (Clear HDEGOVRF flag) */ + +#define HSP_ERR_ICR_OPCOERRC_Pos (22UL) +#define HSP_ERR_ICR_OPCOERRC_Msk (0x1UL << HSP_ERR_ICR_OPCOERRC_Pos) /*!< 0x00400000 */ +#define HSP_ERR_ICR_OPCOERRC HSP_ERR_ICR_OPCOERRC_Msk /*!< OPCOERRC (Clear OPCOERRF flag) */ + +#define HSP_ERR_ICR_ACCERRC_Pos (23UL) +#define HSP_ERR_ICR_ACCERRC_Msk (0x1UL << HSP_ERR_ICR_ACCERRC_Pos) /*!< 0x00800000 */ +#define HSP_ERR_ICR_ACCERRC HSP_ERR_ICR_ACCERRC_Msk /*!< ACCERRC (Clear ACCERRF flag) */ + +#define HSP_ERR_ICR_FPUERRC_Pos (24UL) +#define HSP_ERR_ICR_FPUERRC_Msk (0x1UL << HSP_ERR_ICR_FPUERRC_Pos) /*!< 0x01000000 */ +#define HSP_ERR_ICR_FPUERRC HSP_ERR_ICR_FPUERRC_Msk /*!< FPUERRC (Clear FPUERRF flag) */ + +/******************** Bit definition for HSP_EVT_ICR register ********************/ +#define HSP_EVT_ICR_H2CMRDYC_Pos (0UL) +#define HSP_EVT_ICR_H2CMRDYC_Msk (0x1UL << HSP_EVT_ICR_H2CMRDYC_Pos) /*!< 0x00000001 */ +#define HSP_EVT_ICR_H2CMRDYC HSP_EVT_ICR_H2CMRDYC_Msk /*!< H2CMRDYC (Clear H2CMRDYF flag) */ + +#define HSP_EVT_ICR_C2HMFREEC_Pos (1UL) +#define HSP_EVT_ICR_C2HMFREEC_Msk (0x1UL << HSP_EVT_ICR_C2HMFREEC_Pos) /*!< 0x00000002 */ +#define HSP_EVT_ICR_C2HMFREEC HSP_EVT_ICR_C2HMFREEC_Msk /*!< C2HMFREEC (Clear C2HMFREEF flag) */ + +#define HSP_EVT_ICR_DCDONEC_Pos (2UL) +#define HSP_EVT_ICR_DCDONEC_Msk (0x1UL << HSP_EVT_ICR_DCDONEC_Pos) /*!< 0x00000004 */ +#define HSP_EVT_ICR_DCDONEC HSP_EVT_ICR_DCDONEC_Msk /*!< DCDONEC (Clear DCDONEF flag) */ + +#define HSP_EVT_ICR_CDEGRDYC_Pos (7UL) +#define HSP_EVT_ICR_CDEGRDYC_Msk (0x1UL << HSP_EVT_ICR_CDEGRDYC_Pos) /*!< 0x00000080 */ +#define HSP_EVT_ICR_CDEGRDYC HSP_EVT_ICR_CDEGRDYC_Msk /*!< CDEGRDYC (Clear of CDEGRDYF flag) */ + +#define HSP_EVT_ICR_SOFWFEC_Pos (8UL) +#define HSP_EVT_ICR_SOFWFEC_Msk (0x1UL << HSP_EVT_ICR_SOFWFEC_Pos) /*!< 0x00000100 */ +#define HSP_EVT_ICR_SOFWFEC HSP_EVT_ICR_SOFWFEC_Msk /*!< SOFWFEC (Clear of SOFWFEF flag) */ + +#define HSP_EVT_ICR_EOFWFEC_Pos (9UL) +#define HSP_EVT_ICR_EOFWFEC_Msk (0x1UL << HSP_EVT_ICR_EOFWFEC_Pos) /*!< 0x00000200 */ +#define HSP_EVT_ICR_EOFWFEC HSP_EVT_ICR_EOFWFEC_Msk /*!< EOFWFEC (Clear of EOFWFEF flag) */ + +#define HSP_EVT_ICR_SOTECP0C_Pos (16UL) +#define HSP_EVT_ICR_SOTECP0C_Msk (0x1UL << HSP_EVT_ICR_SOTECP0C_Pos) /*!< 0x00010000 */ +#define HSP_EVT_ICR_SOTECP0C HSP_EVT_ICR_SOTECP0C_Msk /*!< SOTECP0C (Clear SOTECP0F flag) */ + +#define HSP_EVT_ICR_SOTECP1C_Pos (17UL) +#define HSP_EVT_ICR_SOTECP1C_Msk (0x1UL << HSP_EVT_ICR_SOTECP1C_Pos) /*!< 0x00020000 */ +#define HSP_EVT_ICR_SOTECP1C HSP_EVT_ICR_SOTECP1C_Msk /*!< SOTECP1C (Clear SOTECP1F flag) */ + +#define HSP_EVT_ICR_SOTECP2C_Pos (18UL) +#define HSP_EVT_ICR_SOTECP2C_Msk (0x1UL << HSP_EVT_ICR_SOTECP2C_Pos) /*!< 0x00040000 */ +#define HSP_EVT_ICR_SOTECP2C HSP_EVT_ICR_SOTECP2C_Msk /*!< SOTECP2C (Clear SOTECP2F flag) */ + +#define HSP_EVT_ICR_SOTECP3C_Pos (19UL) +#define HSP_EVT_ICR_SOTECP3C_Msk (0x1UL << HSP_EVT_ICR_SOTECP3C_Pos) /*!< 0x00080000 */ +#define HSP_EVT_ICR_SOTECP3C HSP_EVT_ICR_SOTECP3C_Msk /*!< SOTECP3C (Clear SOTECP3F flag) */ + +#define HSP_EVT_ICR_EOTECP0C_Pos (20UL) +#define HSP_EVT_ICR_EOTECP0C_Msk (0x1UL << HSP_EVT_ICR_EOTECP0C_Pos) /*!< 0x00100000 */ +#define HSP_EVT_ICR_EOTECP0C HSP_EVT_ICR_EOTECP0C_Msk /*!< EOTECP0C (Clear EOTECP0F flag) */ + +#define HSP_EVT_ICR_EOTECP1C_Pos (21UL) +#define HSP_EVT_ICR_EOTECP1C_Msk (0x1UL << HSP_EVT_ICR_EOTECP1C_Pos) /*!< 0x00200000 */ +#define HSP_EVT_ICR_EOTECP1C HSP_EVT_ICR_EOTECP1C_Msk /*!< EOTECP1C (Clear EOTECP1F flag) */ + +#define HSP_EVT_ICR_EOTECP2C_Pos (22UL) +#define HSP_EVT_ICR_EOTECP2C_Msk (0x1UL << HSP_EVT_ICR_EOTECP2C_Pos) /*!< 0x00400000 */ +#define HSP_EVT_ICR_EOTECP2C HSP_EVT_ICR_EOTECP2C_Msk /*!< EOTECP2C (Clear EOTECP2F flag) */ + +#define HSP_EVT_ICR_EOTECP3C_Pos (23UL) +#define HSP_EVT_ICR_EOTECP3C_Msk (0x1UL << HSP_EVT_ICR_EOTECP3C_Pos) /*!< 0x00800000 */ +#define HSP_EVT_ICR_EOTECP3C HSP_EVT_ICR_EOTECP3C_Msk /*!< EOTECP3C (Clear EOTECP3F flag) */ + +#define HSP_EVT_ICR_TOVLPC_Pos (28UL) +#define HSP_EVT_ICR_TOVLPC_Msk (0x1UL << HSP_EVT_ICR_TOVLPC_Pos) /*!< 0x10000000 */ +#define HSP_EVT_ICR_TOVLPC HSP_EVT_ICR_TOVLPC_Msk /*!< TOVLPC (Clear TOVLPF flag) */ + +#define HSP_EVT_ICR_FPUSATC_Pos (31UL) +#define HSP_EVT_ICR_FPUSATC_Msk (0x1UL << HSP_EVT_ICR_FPUSATC_Pos) /*!< 0x80000000 */ +#define HSP_EVT_ICR_FPUSATC HSP_EVT_ICR_FPUSATC_Msk /*!< FPUSATC (Clear FPUSATF flag) */ + +/******************** Bit definition for HSP_PFCTEVT_ICR register ********************/ +#define HSP_PFCTEVT_ICR_PFCTC_Pos (0UL) +#define HSP_PFCTEVT_ICR_PFCTC_Msk (0xFFFFFFFFUL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0xFFFFFFFF */ +#define HSP_PFCTEVT_ICR_PFCTC HSP_PFCTEVT_ICR_PFCTC_Msk /*!< PFCTC[31:0] bits (Clear PFCTF[31:0] flag) */ +#define HSP_PFCTEVT_ICR_PFCTC_0 (0x00001UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000001 */ +#define HSP_PFCTEVT_ICR_PFCTC_1 (0x00002UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000002 */ +#define HSP_PFCTEVT_ICR_PFCTC_2 (0x00004UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000004 */ +#define HSP_PFCTEVT_ICR_PFCTC_3 (0x00008UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000008 */ +#define HSP_PFCTEVT_ICR_PFCTC_4 (0x00010UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000010 */ +#define HSP_PFCTEVT_ICR_PFCTC_5 (0x00020UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000020 */ +#define HSP_PFCTEVT_ICR_PFCTC_6 (0x00040UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000040 */ +#define HSP_PFCTEVT_ICR_PFCTC_7 (0x00080UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000080 */ +#define HSP_PFCTEVT_ICR_PFCTC_8 (0x00100UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000100 */ +#define HSP_PFCTEVT_ICR_PFCTC_9 (0x00200UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000200 */ +#define HSP_PFCTEVT_ICR_PFCTC_10 (0x00400UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000400 */ +#define HSP_PFCTEVT_ICR_PFCTC_11 (0x00800UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000800 */ +#define HSP_PFCTEVT_ICR_PFCTC_12 (0x01000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00001000 */ +#define HSP_PFCTEVT_ICR_PFCTC_13 (0x02000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00002000 */ +#define HSP_PFCTEVT_ICR_PFCTC_14 (0x04000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00004000 */ +#define HSP_PFCTEVT_ICR_PFCTC_15 (0x08000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00008000 */ +#define HSP_PFCTEVT_ICR_PFCTC_16 (0x10000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00010000 */ +#define HSP_PFCTEVT_ICR_PFCTC_17 (0x20000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00020000 */ +#define HSP_PFCTEVT_ICR_PFCTC_18 (0x40000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00040000 */ +#define HSP_PFCTEVT_ICR_PFCTC_19 (0x80000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00080000 */ +#define HSP_PFCTEVT_ICR_PFCTC_20 (0x100000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00100000 */ +#define HSP_PFCTEVT_ICR_PFCTC_21 (0x200000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00200000 */ +#define HSP_PFCTEVT_ICR_PFCTC_22 (0x400000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00400000 */ +#define HSP_PFCTEVT_ICR_PFCTC_23 (0x800000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00800000 */ +#define HSP_PFCTEVT_ICR_PFCTC_24 (0x1000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x01000000 */ +#define HSP_PFCTEVT_ICR_PFCTC_25 (0x2000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x02000000 */ +#define HSP_PFCTEVT_ICR_PFCTC_26 (0x4000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x04000000 */ +#define HSP_PFCTEVT_ICR_PFCTC_27 (0x8000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x08000000 */ +#define HSP_PFCTEVT_ICR_PFCTC_28 (0x10000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x10000000 */ +#define HSP_PFCTEVT_ICR_PFCTC_29 (0x20000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x20000000 */ +#define HSP_PFCTEVT_ICR_PFCTC_30 (0x40000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x40000000 */ +#define HSP_PFCTEVT_ICR_PFCTC_31 (0x80000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for HSP_FWVERR register ********************/ +#define HSP_FWVERR_CRAMINREV_Pos (0UL) +#define HSP_FWVERR_CRAMINREV_Msk (0xFFUL << HSP_FWVERR_CRAMINREV_Pos) /*!< 0x000000FF */ +#define HSP_FWVERR_CRAMINREV HSP_FWVERR_CRAMINREV_Msk /*!< CRAMINREV[7:0] bits (Code RAM Minor revision) */ + +#define HSP_FWVERR_CRAMAJREV_Pos (8UL) +#define HSP_FWVERR_CRAMAJREV_Msk (0xFUL << HSP_FWVERR_CRAMAJREV_Pos) /*!< 0x00000F00 */ +#define HSP_FWVERR_CRAMAJREV HSP_FWVERR_CRAMAJREV_Msk /*!< CRAMAJREV[3:0] bits (Code RAM Major revision) */ + +#define HSP_FWVERR_CROMINREV_Pos (12UL) +#define HSP_FWVERR_CROMINREV_Msk (0xFFUL << HSP_FWVERR_CROMINREV_Pos) /*!< 0x000FF000 */ +#define HSP_FWVERR_CROMINREV HSP_FWVERR_CROMINREV_Msk /*!< CROMINREV[7:0] bits (Code ROM Minor revision) */ + +#define HSP_FWVERR_CROMAJREV_Pos (20UL) +#define HSP_FWVERR_CROMAJREV_Msk (0xFUL << HSP_FWVERR_CROMAJREV_Pos) /*!< 0x000F0000 */ +#define HSP_FWVERR_CROMAJREV HSP_FWVERR_CROMAJREV_Msk /*!< CROMAJREV[3:0] bits (Code ROM Major revision) */ + +#define HSP_FWVERR_DROMINREV_Pos (24UL) +#define HSP_FWVERR_DROMINREV_Msk (0xFUL << HSP_FWVERR_DROMINREV_Pos) /*!< 0x00F00000 */ +#define HSP_FWVERR_DROMINREV HSP_FWVERR_DROMINREV_Msk /*!< DROMINREV[3:0] bits (Data ROM Minor revision) */ + +#define HSP_FWVERR_DROMAJREV_Pos (28UL) +#define HSP_FWVERR_DROMAJREV_Msk (0xFUL << HSP_FWVERR_DROMAJREV_Pos) /*!< 0x0F000000 */ +#define HSP_FWVERR_DROMAJREV HSP_FWVERR_DROMAJREV_Msk /*!< DROMAJREV[3:0] bits (Data ROM Major revision) */ + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0UL) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1UL) +#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2UL) +#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3UL) +#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4UL) +#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5UL) +#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6UL) +#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7UL) +#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8UL) +#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12UL) +#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_SWRST_Pos (13UL) +#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ +#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ +#define I2C_CR1_TXDMAEN_Pos (14UL) +#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15UL) +#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16UL) +#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17UL) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18UL) +#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19UL) +#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20UL) +#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21UL) +#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22UL) +#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23UL) +#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ +#define I2C_CR1_FMP_Pos (24UL) +#define I2C_CR1_FMP_Msk (0x1UL << I2C_CR1_FMP_Pos) /*!< 0x01000000 */ +#define I2C_CR1_FMP I2C_CR1_FMP_Msk /*!< FMP enable */ +#define I2C_CR1_ADDRACLR_Pos (30UL) +#define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ +#define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ +#define I2C_CR1_STOPFACLR_Pos (31UL) +#define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ +#define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0UL) +#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10UL) +#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11UL) +#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12UL) +#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13UL) +#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14UL) +#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15UL) +#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16UL) +#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24UL) +#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25UL) +#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26UL) +#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0UL) +#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10UL) +#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15UL) +#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1UL) +#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8UL) +#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8UL) +#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9UL) +#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8UL) +#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10UL) +#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8UL) +#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9UL) +#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8UL) +#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15UL) +#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *******************/ +#define I2C_TIMINGR_SCLL_Pos (0UL) +#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8UL) +#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16UL) +#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20UL) +#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28UL) +#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *******************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0UL) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12UL) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15UL) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16UL) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31UL) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE_Pos (0UL) +#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1UL) +#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2UL) +#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3UL) +#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4UL) +#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5UL) +#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6UL) +#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7UL) +#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8UL) +#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9UL) +#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10UL) +#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11UL) +#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12UL) +#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13UL) +#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15UL) +#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16UL) +#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17UL) +#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF_Pos (3UL) +#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4UL) +#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5UL) +#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8UL) +#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9UL) +#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10UL) +#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11UL) +#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12UL) +#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13UL) +#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register *********************/ +#define I2C_PECR_PEC_Pos (0UL) +#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0UL) +#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA_Pos (0UL) +#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ + +/****************** Bit definition for I2C_AUTOCR register ********************/ +#define I2C_AUTOCR_TCDMAEN_Pos (6UL) +#define I2C_AUTOCR_TCDMAEN_Msk (0x1UL << I2C_AUTOCR_TCDMAEN_Pos) /*!< 0x00000040 */ +#define I2C_AUTOCR_TCDMAEN I2C_AUTOCR_TCDMAEN_Msk /*!< DMA request enable on Transfer Complete event */ +#define I2C_AUTOCR_TCRDMAEN_Pos (7UL) +#define I2C_AUTOCR_TCRDMAEN_Msk (0x1UL << I2C_AUTOCR_TCRDMAEN_Pos) /*!< 0x00000080 */ +#define I2C_AUTOCR_TCRDMAEN I2C_AUTOCR_TCRDMAEN_Msk /*!< DMA request enable on Transfer Complete Reload event */ +#define I2C_AUTOCR_TRIGSEL_Pos (16UL) +#define I2C_AUTOCR_TRIGSEL_Msk (0xFUL << I2C_AUTOCR_TRIGSEL_Pos) /*!< 0x000F0000 */ +#define I2C_AUTOCR_TRIGSEL I2C_AUTOCR_TRIGSEL_Msk /*!< Trigger selection */ +#define I2C_AUTOCR_TRIGPOL_Pos (20UL) +#define I2C_AUTOCR_TRIGPOL_Msk (0x1UL << I2C_AUTOCR_TRIGPOL_Pos) /*!< 0x000100000 */ +#define I2C_AUTOCR_TRIGPOL I2C_AUTOCR_TRIGPOL_Msk /*!< Trigger polarity */ +#define I2C_AUTOCR_TRIGEN_Pos (21UL) +#define I2C_AUTOCR_TRIGEN_Msk (0x1UL << I2C_AUTOCR_TRIGEN_Pos) /*!< 0x000200000 */ +#define I2C_AUTOCR_TRIGEN I2C_AUTOCR_TRIGEN_Msk /*!< Trigger enable */ + +/******************************************************************************/ +/* */ +/* Improved Inter-integrated Circuit Interface (I3C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I3C_CR register *********************/ +#define I3C_CR_DCNT_Pos (0UL) +#define I3C_CR_DCNT_Msk (0xFFFFUL << I3C_CR_DCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_CR_DCNT I3C_CR_DCNT_Msk /*!< Data Byte Count */ +#define I3C_CR_RNW_Pos (16UL) +#define I3C_CR_RNW_Msk (0x1UL << I3C_CR_RNW_Pos) /*!< 0x00010000 */ +#define I3C_CR_RNW I3C_CR_RNW_Msk /*!< Read Not Write */ +#define I3C_CR_CCC_Pos (16UL) +#define I3C_CR_CCC_Msk (0xFFUL << I3C_CR_CCC_Pos) /*!< 0x00FF0000 */ +#define I3C_CR_CCC I3C_CR_CCC_Msk /*!< 8-Bit CCC code */ +#define I3C_CR_ADD_Pos (17UL) +#define I3C_CR_ADD_Msk (0x7FUL << I3C_CR_ADD_Pos) /*!< 0x00FE0000 */ +#define I3C_CR_ADD I3C_CR_ADD_Msk /*!< Target Address */ +#define I3C_CR_MTYPE_Pos (27UL) +#define I3C_CR_MTYPE_Msk (0xFUL << I3C_CR_MTYPE_Pos) /*!< 0xF8000000 */ +#define I3C_CR_MTYPE I3C_CR_MTYPE_Msk /*!< Message Type */ +#define I3C_CR_MTYPE_0 (0x1UL << I3C_CR_MTYPE_Pos) /*!< 0x08000000 */ +#define I3C_CR_MTYPE_1 (0x2UL << I3C_CR_MTYPE_Pos) /*!< 0x10000000 */ +#define I3C_CR_MTYPE_2 (0x4UL << I3C_CR_MTYPE_Pos) /*!< 0x20000000 */ +#define I3C_CR_MTYPE_3 (0x8UL << I3C_CR_MTYPE_Pos) /*!< 0x40000000 */ +#define I3C_CR_MEND_Pos (31UL) +#define I3C_CR_MEND_Msk (0x1UL << I3C_CR_MEND_Pos) /*!< 0x80000000 */ +#define I3C_CR_MEND I3C_CR_MEND_Msk /*!< Message End */ + +/******************* Bit definition for I3C_CFGR register *******************/ +#define I3C_CFGR_EN_Pos (0UL) +#define I3C_CFGR_EN_Msk (0x1UL << I3C_CFGR_EN_Pos) /*!< 0x00000001 */ +#define I3C_CFGR_EN I3C_CFGR_EN_Msk /*!< Peripheral Enable */ +#define I3C_CFGR_CRINIT_Pos (1UL) +#define I3C_CFGR_CRINIT_Msk (0x1UL << I3C_CFGR_CRINIT_Pos) /*!< 0x00000002 */ +#define I3C_CFGR_CRINIT I3C_CFGR_CRINIT_Msk /*!< Peripheral Init mode (Target/Controller) */ +#define I3C_CFGR_NOARBH_Pos (2UL) +#define I3C_CFGR_NOARBH_Msk (0x1UL << I3C_CFGR_NOARBH_Pos) /*!< 0x00000004 */ +#define I3C_CFGR_NOARBH I3C_CFGR_NOARBH_Msk /*!< No Arbitration Header (7'h7E)*/ +#define I3C_CFGR_RSTPTRN_Pos (3UL) +#define I3C_CFGR_RSTPTRN_Msk (0x1UL << I3C_CFGR_RSTPTRN_Pos) /*!< 0x00000008 */ +#define I3C_CFGR_RSTPTRN I3C_CFGR_RSTPTRN_Msk /*!< Reset Pattern enable */ +#define I3C_CFGR_EXITPTRN_Pos (4UL) +#define I3C_CFGR_EXITPTRN_Msk (0x1UL << I3C_CFGR_EXITPTRN_Pos) /*!< 0x00000010 */ +#define I3C_CFGR_EXITPTRN I3C_CFGR_EXITPTRN_Msk /*!< Exit Pattern enable */ +#define I3C_CFGR_HKSDAEN_Pos (5UL) +#define I3C_CFGR_HKSDAEN_Msk (0x1UL << I3C_CFGR_HKSDAEN_Pos) /*!< 0x00000020 */ +#define I3C_CFGR_HKSDAEN I3C_CFGR_HKSDAEN_Msk /*!< High-Keeper on SDA Enable */ +#define I3C_CFGR_HJACK_Pos (7UL) +#define I3C_CFGR_HJACK_Msk (0x1UL << I3C_CFGR_HJACK_Pos) /*!< 0x00000080 */ +#define I3C_CFGR_HJACK I3C_CFGR_HJACK_Msk /*!< Hot Join Acknowledgment */ +#define I3C_CFGR_RXDMAEN_Pos (8UL) +#define I3C_CFGR_RXDMAEN_Msk (0x1UL << I3C_CFGR_RXDMAEN_Pos) /*!< 0x00000100 */ +#define I3C_CFGR_RXDMAEN I3C_CFGR_RXDMAEN_Msk /*!< RX FIFO DMA mode Enable */ +#define I3C_CFGR_RXFLUSH_Pos (9UL) +#define I3C_CFGR_RXFLUSH_Msk (0x1UL << I3C_CFGR_RXFLUSH_Pos) /*!< 0x00000200 */ +#define I3C_CFGR_RXFLUSH I3C_CFGR_RXFLUSH_Msk /*!< RX FIFO Flush */ +#define I3C_CFGR_RXTHRES_Pos (10UL) +#define I3C_CFGR_RXTHRES_Msk (0x1UL << I3C_CFGR_RXTHRES_Pos) /*!< 0x00000400 */ +#define I3C_CFGR_RXTHRES I3C_CFGR_RXTHRES_Msk /*!< RX FIFO Threshold */ +#define I3C_CFGR_TXDMAEN_Pos (12UL) +#define I3C_CFGR_TXDMAEN_Msk (0x1UL << I3C_CFGR_TXDMAEN_Pos) /*!< 0x00001000 */ +#define I3C_CFGR_TXDMAEN I3C_CFGR_TXDMAEN_Msk /*!< TX FIFO DMA mode Enable */ +#define I3C_CFGR_TXFLUSH_Pos (13UL) +#define I3C_CFGR_TXFLUSH_Msk (0x1UL << I3C_CFGR_TXFLUSH_Pos) /*!< 0x00002000 */ +#define I3C_CFGR_TXFLUSH I3C_CFGR_TXFLUSH_Msk /*!< TX FIFO Flush */ +#define I3C_CFGR_TXTHRES_Pos (14UL) +#define I3C_CFGR_TXTHRES_Msk (0x1UL << I3C_CFGR_TXTHRES_Pos) /*!< 0x00004000 */ +#define I3C_CFGR_TXTHRES I3C_CFGR_TXTHRES_Msk /*!< TX FIFO Threshold */ +#define I3C_CFGR_SDMAEN_Pos (16UL) +#define I3C_CFGR_SDMAEN_Msk (0x1UL << I3C_CFGR_SDMAEN_Pos) /*!< 0x00010000 */ +#define I3C_CFGR_SDMAEN I3C_CFGR_SDMAEN_Msk /*!< Status FIFO DMA mode Enable */ +#define I3C_CFGR_SFLUSH_Pos (17UL) +#define I3C_CFGR_SFLUSH_Msk (0x1UL << I3C_CFGR_SFLUSH_Pos) /*!< 0x00020000 */ +#define I3C_CFGR_SFLUSH I3C_CFGR_SFLUSH_Msk /*!< Status FIFO Flush */ +#define I3C_CFGR_SMODE_Pos (18UL) +#define I3C_CFGR_SMODE_Msk (0x1UL << I3C_CFGR_SMODE_Pos) /*!< 0x00040000 */ +#define I3C_CFGR_SMODE I3C_CFGR_SMODE_Msk /*!< Status FIFO mode Enable */ +#define I3C_CFGR_TMODE_Pos (19UL) +#define I3C_CFGR_TMODE_Msk (0x1UL << I3C_CFGR_TMODE_Pos) /*!< 0x00080000 */ +#define I3C_CFGR_TMODE I3C_CFGR_TMODE_Msk /*!< Control FIFO mode Enable */ +#define I3C_CFGR_CDMAEN_Pos (20UL) +#define I3C_CFGR_CDMAEN_Msk (0x1UL << I3C_CFGR_CDMAEN_Pos) /*!< 0x00100000 */ +#define I3C_CFGR_CDMAEN I3C_CFGR_CDMAEN_Msk /*!< Control FIFO DMA mode Enable */ +#define I3C_CFGR_CFLUSH_Pos (21UL) +#define I3C_CFGR_CFLUSH_Msk (0x1UL << I3C_CFGR_CFLUSH_Pos) /*!< 0x00200000 */ +#define I3C_CFGR_CFLUSH I3C_CFGR_CFLUSH_Msk /*!< Control FIFO Flush */ +#define I3C_CFGR_FCFDIS_Pos (23UL) +#define I3C_CFGR_FCFDIS_Msk (0x1UL << I3C_CFGR_FCFDIS_Pos) /*!< 0x00800000 */ +#define I3C_CFGR_FCFDIS I3C_CFGR_FCFDIS_Msk /*!< FCF generation disable */ +#define I3C_CFGR_TRIGSEL_Pos (24UL) +#define I3C_CFGR_TRIGSEL_Msk (0xFUL << I3C_CFGR_TRIGSEL_Pos) /*!< 0x0F000000 */ +#define I3C_CFGR_TRIGSEL I3C_CFGR_TRIGSEL_Msk /*!< Trigger selection */ +#define I3C_CFGR_TRIGPOL_Pos (28UL) +#define I3C_CFGR_TRIGPOL_Msk (0x1UL << I3C_CFGR_TRIGPOL_Pos) /*!< 0x10000000 */ +#define I3C_CFGR_TRIGPOL I3C_CFGR_TRIGPOL_Msk /*!< Trigger polarity */ +#define I3C_CFGR_TRIGHWEN_Pos (29UL) +#define I3C_CFGR_TRIGHWEN_Msk (0x1UL << I3C_CFGR_TRIGHWEN_Pos) /*!< 0x20000000 */ +#define I3C_CFGR_TRIGHWEN I3C_CFGR_TRIGHWEN_Msk /*!< Trigger enable */ +#define I3C_CFGR_TSFSET_Pos (30UL) +#define I3C_CFGR_TSFSET_Msk (0x1UL << I3C_CFGR_TSFSET_Pos) /*!< 0x40000000 */ +#define I3C_CFGR_TSFSET I3C_CFGR_TSFSET_Msk /*!< Transfer Set */ + +/******************* Bit definition for I3C_RDR register ********************/ +#define I3C_RDR_RDB0_Pos (0UL) +#define I3C_RDR_RDB0_Msk (0xFFUL << I3C_RDR_RDB0_Pos) /*!< 0x000000FF */ +#define I3C_RDR_RDB0 I3C_RDR_RDB0_Msk /*!< Receive Data Byte */ + +/****************** Bit definition for I3C_RDWR register ********************/ +#define I3C_RDWR_RDBx_Pos (0UL) +#define I3C_RDWR_RDBx_Msk (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_RDWR_RDBx I3C_RDWR_RDBx_Msk /*!< Receive Data Byte, full double word */ +#define I3C_RDWR_RDB0_Pos (0UL) +#define I3C_RDWR_RDB0_Msk (0xFFUL << I3C_RDWR_RDB0_Pos) /*!< 0x000000FF */ +#define I3C_RDWR_RDB0 I3C_RDWR_RDB0_Msk /*!< Receive Data Byte 0 */ +#define I3C_RDWR_RDB1_Pos (8UL) +#define I3C_RDWR_RDB1_Msk (0xFFUL << I3C_RDWR_RDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_RDWR_RDB1 I3C_RDWR_RDB1_Msk /*!< Receive Data Byte 1 */ +#define I3C_RDWR_RDB2_Pos (16UL) +#define I3C_RDWR_RDB2_Msk (0xFFUL << I3C_RDWR_RDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_RDWR_RDB2 I3C_RDWR_RDB2_Msk /*!< Receive Data Byte 2 */ +#define I3C_RDWR_RDB3_Pos (24UL) +#define I3C_RDWR_RDB3_Msk (0xFFUL << I3C_RDWR_RDB3_Pos) /*!< 0xFF000000 */ +#define I3C_RDWR_RDB3 I3C_RDWR_RDB3_Msk /*!< Receive Data Byte 3 */ + +/******************* Bit definition for I3C_TDR register ********************/ +#define I3C_TDR_TDB0_Pos (0UL) +#define I3C_TDR_TDB0_Msk (0xFFUL << I3C_TDR_TDB0_Pos) /*!< 0x000000FF */ +#define I3C_TDR_TDB0 I3C_TDR_TDB0_Msk /*!< Transmit Data Byte */ + +/****************** Bit definition for I3C_TDWR register ********************/ +#define I3C_TDWR_TDBx_Pos (0UL) +#define I3C_TDWR_TDBx_Msk (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_TDWR_TDBx I3C_TDWR_TDBx_Msk /*!< Transmit Data Byte, full double word */ +#define I3C_TDWR_TDB0_Pos (0UL) +#define I3C_TDWR_TDB0_Msk (0xFFUL << I3C_TDWR_TDB0_Pos) /*!< 0x000000FF */ +#define I3C_TDWR_TDB0 I3C_TDWR_TDB0_Msk /*!< Transmit Data Byte 0 */ +#define I3C_TDWR_TDB1_Pos (8UL) +#define I3C_TDWR_TDB1_Msk (0xFFUL << I3C_TDWR_TDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_TDWR_TDB1 I3C_TDWR_TDB1_Msk /*!< Transmit Data Byte 1 */ +#define I3C_TDWR_TDB2_Pos (16UL) +#define I3C_TDWR_TDB2_Msk (0xFFUL << I3C_TDWR_TDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_TDWR_TDB2 I3C_TDWR_TDB2_Msk /*!< Transmit Data Byte 2 */ +#define I3C_TDWR_TDB3_Pos (24UL) +#define I3C_TDWR_TDB3_Msk (0xFFUL << I3C_TDWR_TDB3_Pos) /*!< 0xFF000000 */ +#define I3C_TDWR_TDB3 I3C_TDWR_TDB3_Msk /*!< Transmit Data Byte 3 */ + +/******************* Bit definition for I3C_IBIDR register ******************/ +#define I3C_IBIDR_IBIDBx_Pos (0UL) +#define I3C_IBIDR_IBIDBx_Msk (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_IBIDR_IBIDBx I3C_IBIDR_IBIDBx_Msk /*!< IBI Data Byte, full double word */ +#define I3C_IBIDR_IBIDB0_Pos (0UL) +#define I3C_IBIDR_IBIDB0_Msk (0xFFUL << I3C_IBIDR_IBIDB0_Pos) /*!< 0x000000FF */ +#define I3C_IBIDR_IBIDB0 I3C_IBIDR_IBIDB0_Msk /*!< IBI Data Byte 0 */ +#define I3C_IBIDR_IBIDB1_Pos (8UL) +#define I3C_IBIDR_IBIDB1_Msk (0xFFUL << I3C_IBIDR_IBIDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_IBIDR_IBIDB1 I3C_IBIDR_IBIDB1_Msk /*!< IBI Data Byte 1 */ +#define I3C_IBIDR_IBIDB2_Pos (16UL) +#define I3C_IBIDR_IBIDB2_Msk (0xFFUL << I3C_IBIDR_IBIDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_IBIDR_IBIDB2 I3C_IBIDR_IBIDB2_Msk /*!< IBI Data Byte 2 */ +#define I3C_IBIDR_IBIDB3_Pos (24UL) +#define I3C_IBIDR_IBIDB3_Msk (0xFFUL << I3C_IBIDR_IBIDB3_Pos) /*!< 0xFF000000 */ +#define I3C_IBIDR_IBIDB3 I3C_IBIDR_IBIDB3_Msk /*!< IBI Data Byte 3 */ + +/****************** Bit definition for I3C_TGTTDR register ******************/ +#define I3C_TGTTDR_TGTTDCNT_Pos (0UL) +#define I3C_TGTTDR_TGTTDCNT_Msk (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_TGTTDR_TGTTDCNT I3C_TGTTDR_TGTTDCNT_Msk /*!< Target Transmit Data Counter */ +#define I3C_TGTTDR_PRELOAD_Pos (16UL) +#define I3C_TGTTDR_PRELOAD_Msk (0x1UL << I3C_TGTTDR_PRELOAD_Pos) /*!< 0x00010000 */ +#define I3C_TGTTDR_PRELOAD I3C_TGTTDR_PRELOAD_Msk /*!< Transmit FIFO Preload Enable/Status */ + +/******************* Bit definition for I3C_SR register *********************/ +#define I3C_SR_XDCNT_Pos (0UL) +#define I3C_SR_XDCNT_Msk (0xFFFFUL << I3C_SR_XDCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_SR_XDCNT I3C_SR_XDCNT_Msk /*!< Transfer Data Byte Count status */ +#define I3C_SR_ABT_Pos (17UL) +#define I3C_SR_ABT_Msk (0x1UL << I3C_SR_ABT_Pos) /*!< 0x00020000 */ +#define I3C_SR_ABT I3C_SR_ABT_Msk /*!< Target Abort Indication */ +#define I3C_SR_DIR_Pos (18UL) +#define I3C_SR_DIR_Msk (0x1UL << I3C_SR_DIR_Pos) /*!< 0x00040000 */ +#define I3C_SR_DIR I3C_SR_DIR_Msk /*!< Message Direction */ +#define I3C_SR_MID_Pos (24UL) +#define I3C_SR_MID_Msk (0xFFUL << I3C_SR_MID_Pos) /*!< 0xFF000000 */ +#define I3C_SR_MID I3C_SR_MID_Msk /*!< Message Identifier */ + +/******************* Bit definition for I3C_SER register ********************/ +#define I3C_SER_CODERR_Pos (0UL) +#define I3C_SER_CODERR_Msk (0xFUL << I3C_SER_CODERR_Pos) /*!< 0x0000000F */ +#define I3C_SER_CODERR I3C_SER_CODERR_Msk /*!< Protocol Error Code */ +#define I3C_SER_CODERR_0 (0x1UL << I3C_SER_CODERR_Pos) /*!< 0x00000001 */ +#define I3C_SER_CODERR_1 (0x2UL << I3C_SER_CODERR_Pos) /*!< 0x00000002 */ +#define I3C_SER_CODERR_2 (0x4UL << I3C_SER_CODERR_Pos) /*!< 0x00000004 */ +#define I3C_SER_CODERR_3 (0x8UL << I3C_SER_CODERR_Pos) /*!< 0x00000008 */ +#define I3C_SER_PERR_Pos (4UL) +#define I3C_SER_PERR_Msk (0x1UL << I3C_SER_PERR_Pos) /*!< 0x00000010 */ +#define I3C_SER_PERR I3C_SER_PERR_Msk /*!< Protocol Error */ +#define I3C_SER_STALL_Pos (5UL) +#define I3C_SER_STALL_Msk (0x1UL << I3C_SER_STALL_Pos) /*!< 0x00000020 */ +#define I3C_SER_STALL I3C_SER_STALL_Msk /*!< SCL Stall Error */ +#define I3C_SER_DOVR_Pos (6UL) +#define I3C_SER_DOVR_Msk (0x1UL << I3C_SER_DOVR_Pos) /*!< 0x00000040 */ +#define I3C_SER_DOVR I3C_SER_DOVR_Msk /*!< RX/TX FIFO Overrun */ +#define I3C_SER_COVR_Pos (7UL) +#define I3C_SER_COVR_Msk (0x1UL << I3C_SER_COVR_Pos) /*!< 0x00000080 */ +#define I3C_SER_COVR I3C_SER_COVR_Msk /*!< Status/Control FIFO Overrun */ +#define I3C_SER_ANACK_Pos (8UL) +#define I3C_SER_ANACK_Msk (0x1UL << I3C_SER_ANACK_Pos) /*!< 0x00000100 */ +#define I3C_SER_ANACK I3C_SER_ANACK_Msk /*!< Address Not Acknowledged */ +#define I3C_SER_DNACK_Pos (9UL) +#define I3C_SER_DNACK_Msk (0x1UL << I3C_SER_DNACK_Pos) /*!< 0x00000200 */ +#define I3C_SER_DNACK I3C_SER_DNACK_Msk /*!< Data Not Acknowledged */ +#define I3C_SER_DERR_Pos (10UL) +#define I3C_SER_DERR_Msk (0x1UL << I3C_SER_DERR_Pos) /*!< 0x00000400 */ +#define I3C_SER_DERR I3C_SER_DERR_Msk /*!< Data Error during the controller-role hand-off procedure */ + +/******************* Bit definition for I3C_RMR register ********************/ +#define I3C_RMR_IBIRDCNT_Pos (0UL) +#define I3C_RMR_IBIRDCNT_Msk (0x7UL << I3C_RMR_IBIRDCNT_Pos) /*!< 0x00000007 */ +#define I3C_RMR_IBIRDCNT I3C_RMR_IBIRDCNT_Msk /*!< Data Count when reading IBI data */ +#define I3C_RMR_RCODE_Pos (8UL) +#define I3C_RMR_RCODE_Msk (0xFFUL << I3C_RMR_RCODE_Pos) /*!< 0x0000FF00 */ +#define I3C_RMR_RCODE I3C_RMR_RCODE_Msk /*!< CCC code of received command */ +#define I3C_RMR_RADD_Pos (17UL) +#define I3C_RMR_RADD_Msk (0x7FUL << I3C_RMR_RADD_Pos) /*!< 0x00FE0000 */ +#define I3C_RMR_RADD I3C_RMR_RADD_Msk /*!< Target Address Received during accepted IBI or Controller-role request */ + +/******************* Bit definition for I3C_EVR register ********************/ +#define I3C_EVR_CFEF_Pos (0UL) +#define I3C_EVR_CFEF_Msk (0x1UL << I3C_EVR_CFEF_Pos) /*!< 0x00000001 */ +#define I3C_EVR_CFEF I3C_EVR_CFEF_Msk /*!< Control FIFO Empty Flag */ +#define I3C_EVR_TXFEF_Pos (1UL) +#define I3C_EVR_TXFEF_Msk (0x1UL << I3C_EVR_TXFEF_Pos) /*!< 0x00000002 */ +#define I3C_EVR_TXFEF I3C_EVR_TXFEF_Msk /*!< TX FIFO Empty Flag */ +#define I3C_EVR_CFNFF_Pos (2UL) +#define I3C_EVR_CFNFF_Msk (0x1UL << I3C_EVR_CFNFF_Pos) /*!< 0x00000004 */ +#define I3C_EVR_CFNFF I3C_EVR_CFNFF_Msk /*!< Control FIFO Not Full Flag */ +#define I3C_EVR_SFNEF_Pos (3UL) +#define I3C_EVR_SFNEF_Msk (0x1UL << I3C_EVR_SFNEF_Pos) /*!< 0x00000008 */ +#define I3C_EVR_SFNEF I3C_EVR_SFNEF_Msk /*!< Status FIFO Not Empty Flag */ +#define I3C_EVR_TXFNFF_Pos (4UL) +#define I3C_EVR_TXFNFF_Msk (0x1UL << I3C_EVR_TXFNFF_Pos) /*!< 0x00000010 */ +#define I3C_EVR_TXFNFF I3C_EVR_TXFNFF_Msk /*!< TX FIFO Not Full Flag */ +#define I3C_EVR_RXFNEF_Pos (5UL) +#define I3C_EVR_RXFNEF_Msk (0x1UL << I3C_EVR_RXFNEF_Pos) /*!< 0x00000020 */ +#define I3C_EVR_RXFNEF I3C_EVR_RXFNEF_Msk /*!< RX FIFO Not Empty Flag */ +#define I3C_EVR_TXLASTF_Pos (6UL) +#define I3C_EVR_TXLASTF_Msk (0x1UL << I3C_EVR_TXLASTF_Pos) /*!< 0x00000040 */ +#define I3C_EVR_TXLASTF I3C_EVR_TXLASTF_Msk /*!< Last TX byte available in FIFO */ +#define I3C_EVR_RXLASTF_Pos (7UL) +#define I3C_EVR_RXLASTF_Msk (0x1UL << I3C_EVR_RXLASTF_Pos) /*!< 0x00000080 */ +#define I3C_EVR_RXLASTF I3C_EVR_RXLASTF_Msk /*!< Last RX byte read from FIFO */ +#define I3C_EVR_FCF_Pos (9UL) +#define I3C_EVR_FCF_Msk (0x1UL << I3C_EVR_FCF_Pos) /*!< 0x00000200 */ +#define I3C_EVR_FCF I3C_EVR_FCF_Msk /*!< Frame Complete Flag */ +#define I3C_EVR_RXTGTENDF_Pos (10UL) +#define I3C_EVR_RXTGTENDF_Msk (0x1UL << I3C_EVR_RXTGTENDF_Pos) /*!< 0x00000400 */ +#define I3C_EVR_RXTGTENDF I3C_EVR_RXTGTENDF_Msk /*!< Reception Target End Flag */ +#define I3C_EVR_ERRF_Pos (11UL) +#define I3C_EVR_ERRF_Msk (0x1UL << I3C_EVR_ERRF_Pos) /*!< 0x00000800 */ +#define I3C_EVR_ERRF I3C_EVR_ERRF_Msk /*!< Error Flag */ +#define I3C_EVR_IBIF_Pos (15UL) +#define I3C_EVR_IBIF_Msk (0x1UL << I3C_EVR_IBIF_Pos) /*!< 0x00008000 */ +#define I3C_EVR_IBIF I3C_EVR_IBIF_Msk /*!< IBI Flag */ +#define I3C_EVR_IBIENDF_Pos (16UL) +#define I3C_EVR_IBIENDF_Msk (0x1UL << I3C_EVR_IBIENDF_Pos) /*!< 0x00010000 */ +#define I3C_EVR_IBIENDF I3C_EVR_IBIENDF_Msk /*!< IBI End Flag */ +#define I3C_EVR_CRF_Pos (17UL) +#define I3C_EVR_CRF_Msk (0x1UL << I3C_EVR_CRF_Pos) /*!< 0x00020000 */ +#define I3C_EVR_CRF I3C_EVR_CRF_Msk /*!< Controller-role Request Flag */ +#define I3C_EVR_CRUPDF_Pos (18UL) +#define I3C_EVR_CRUPDF_Msk (0x1UL << I3C_EVR_CRUPDF_Pos) /*!< 0x00040000 */ +#define I3C_EVR_CRUPDF I3C_EVR_CRUPDF_Msk /*!< Controller-role Update Flag */ +#define I3C_EVR_HJF_Pos (19UL) +#define I3C_EVR_HJF_Msk (0x1UL << I3C_EVR_HJF_Pos) /*!< 0x00080000 */ +#define I3C_EVR_HJF I3C_EVR_HJF_Msk /*!< Hot Join Flag */ +#define I3C_EVR_WKPF_Pos (21UL) +#define I3C_EVR_WKPF_Msk (0x1UL << I3C_EVR_WKPF_Pos) /*!< 0x00200000 */ +#define I3C_EVR_WKPF I3C_EVR_WKPF_Msk /*!< Wake Up Flag */ +#define I3C_EVR_GETF_Pos (22UL) +#define I3C_EVR_GETF_Msk (0x1UL << I3C_EVR_GETF_Pos) /*!< 0x00400000 */ +#define I3C_EVR_GETF I3C_EVR_GETF_Msk /*!< Get type CCC received Flag */ +#define I3C_EVR_STAF_Pos (23UL) +#define I3C_EVR_STAF_Msk (0x1UL << I3C_EVR_STAF_Pos) /*!< 0x00800000 */ +#define I3C_EVR_STAF I3C_EVR_STAF_Msk /*!< Get Status Flag */ +#define I3C_EVR_DAUPDF_Pos (24UL) +#define I3C_EVR_DAUPDF_Msk (0x1UL << I3C_EVR_DAUPDF_Pos) /*!< 0x01000000 */ +#define I3C_EVR_DAUPDF I3C_EVR_DAUPDF_Msk /*!< Dynamic Address Update Flag */ +#define I3C_EVR_MWLUPDF_Pos (25UL) +#define I3C_EVR_MWLUPDF_Msk (0x1UL << I3C_EVR_MWLUPDF_Pos) /*!< 0x02000000 */ +#define I3C_EVR_MWLUPDF I3C_EVR_MWLUPDF_Msk /*!< Max Write Length Update Flag */ +#define I3C_EVR_MRLUPDF_Pos (26UL) +#define I3C_EVR_MRLUPDF_Msk (0x1UL << I3C_EVR_MRLUPDF_Pos) /*!< 0x04000000 */ +#define I3C_EVR_MRLUPDF I3C_EVR_MRLUPDF_Msk /*!< Max Read Length Update Flag */ +#define I3C_EVR_RSTF_Pos (27UL) +#define I3C_EVR_RSTF_Msk (0x1UL << I3C_EVR_RSTF_Pos) /*!< 0x08000000 */ +#define I3C_EVR_RSTF I3C_EVR_RSTF_Msk /*!< Reset Flag, due to Reset pattern received */ +#define I3C_EVR_ASUPDF_Pos (28UL) +#define I3C_EVR_ASUPDF_Msk (0x1UL << I3C_EVR_ASUPDF_Pos) /*!< 0x10000000 */ +#define I3C_EVR_ASUPDF I3C_EVR_ASUPDF_Msk /*!< Activity State Flag */ +#define I3C_EVR_INTUPDF_Pos (29UL) +#define I3C_EVR_INTUPDF_Msk (0x1UL << I3C_EVR_INTUPDF_Pos) /*!< 0x20000000 */ +#define I3C_EVR_INTUPDF I3C_EVR_INTUPDF_Msk /*!< Interrupt Update Flag */ +#define I3C_EVR_DEFF_Pos (30UL) +#define I3C_EVR_DEFF_Msk (0x1UL << I3C_EVR_DEFF_Pos) /*!< 0x40000000 */ +#define I3C_EVR_DEFF I3C_EVR_DEFF_Msk /*!< List of Targets Command Received Flag */ +#define I3C_EVR_GRPF_Pos (31UL) +#define I3C_EVR_GRPF_Msk (0x1UL << I3C_EVR_GRPF_Pos) /*!< 0x80000000 */ +#define I3C_EVR_GRPF I3C_EVR_GRPF_Msk /*!< List of Group Addresses Command Received Flag */ + +/******************* Bit definition for I3C_IER register ********************/ +#define I3C_IER_CFNFIE_Pos (2UL) +#define I3C_IER_CFNFIE_Msk (0x1UL << I3C_IER_CFNFIE_Pos) /*!< 0x00000004 */ +#define I3C_IER_CFNFIE I3C_IER_CFNFIE_Msk /*!< Control FIFO Not Full Interrupt Enable */ +#define I3C_IER_SFNEIE_Pos (3UL) +#define I3C_IER_SFNEIE_Msk (0x1UL << I3C_IER_SFNEIE_Pos) /*!< 0x00000008 */ +#define I3C_IER_SFNEIE I3C_IER_SFNEIE_Msk /*!< Status FIFO Not Empty Interrupt Enable */ +#define I3C_IER_TXFNFIE_Pos (4UL) +#define I3C_IER_TXFNFIE_Msk (0x1UL << I3C_IER_TXFNFIE_Pos) /*!< 0x00000010 */ +#define I3C_IER_TXFNFIE I3C_IER_TXFNFIE_Msk /*!< TX FIFO Not Full Interrupt Enable */ +#define I3C_IER_RXFNEIE_Pos (5UL) +#define I3C_IER_RXFNEIE_Msk (0x1UL << I3C_IER_RXFNEIE_Pos) /*!< 0x00000020 */ +#define I3C_IER_RXFNEIE I3C_IER_RXFNEIE_Msk /*!< RX FIFO Not Empty Interrupt Enable */ +#define I3C_IER_FCIE_Pos (9UL) +#define I3C_IER_FCIE_Msk (0x1UL << I3C_IER_FCIE_Pos) /*!< 0x00000200 */ +#define I3C_IER_FCIE I3C_IER_FCIE_Msk /*!< Frame Complete Interrupt Enable */ +#define I3C_IER_RXTGTENDIE_Pos (10UL) +#define I3C_IER_RXTGTENDIE_Msk (0x1UL << I3C_IER_RXTGTENDIE_Pos) /*!< 0x00000400 */ +#define I3C_IER_RXTGTENDIE I3C_IER_RXTGTENDIE_Msk /*!< Reception Target End Interrupt Enable */ +#define I3C_IER_ERRIE_Pos (11UL) +#define I3C_IER_ERRIE_Msk (0x1UL << I3C_IER_ERRIE_Pos) /*!< 0x00000800 */ +#define I3C_IER_ERRIE I3C_IER_ERRIE_Msk /*!< Error Interrupt Enable */ +#define I3C_IER_IBIIE_Pos (15UL) +#define I3C_IER_IBIIE_Msk (0x1UL << I3C_IER_IBIIE_Pos) /*!< 0x00008000 */ +#define I3C_IER_IBIIE I3C_IER_IBIIE_Msk /*!< IBI Interrupt Enable */ +#define I3C_IER_IBIENDIE_Pos (16UL) +#define I3C_IER_IBIENDIE_Msk (0x1UL << I3C_IER_IBIENDIE_Pos) /*!< 0x00010000 */ +#define I3C_IER_IBIENDIE I3C_IER_IBIENDIE_Msk /*!< IBI End Interrupt Enable */ +#define I3C_IER_CRIE_Pos (17UL) +#define I3C_IER_CRIE_Msk (0x1UL << I3C_IER_CRIE_Pos) /*!< 0x00020000 */ +#define I3C_IER_CRIE I3C_IER_CRIE_Msk /*!< Controller-role Interrupt Enable */ +#define I3C_IER_CRUPDIE_Pos (18UL) +#define I3C_IER_CRUPDIE_Msk (0x1UL << I3C_IER_CRUPDIE_Pos) /*!< 0x00040000 */ +#define I3C_IER_CRUPDIE I3C_IER_CRUPDIE_Msk /*!< Controller-role Update Interrupt Enable */ +#define I3C_IER_HJIE_Pos (19UL) +#define I3C_IER_HJIE_Msk (0x1UL << I3C_IER_HJIE_Pos) /*!< 0x00080000 */ +#define I3C_IER_HJIE I3C_IER_HJIE_Msk /*!< Hot Join Interrupt Enable */ +#define I3C_IER_WKPIE_Pos (21UL) +#define I3C_IER_WKPIE_Msk (0x1UL << I3C_IER_WKPIE_Pos) /*!< 0x00200000 */ +#define I3C_IER_WKPIE I3C_IER_WKPIE_Msk /*!< Wake Up Interrupt Enable */ +#define I3C_IER_GETIE_Pos (22UL) +#define I3C_IER_GETIE_Msk (0x1UL << I3C_IER_GETIE_Pos) /*!< 0x00400000 */ +#define I3C_IER_GETIE I3C_IER_GETIE_Msk /*!< Get type CCC received Interrupt Enable */ +#define I3C_IER_STAIE_Pos (23UL) +#define I3C_IER_STAIE_Msk (0x1UL << I3C_IER_STAIE_Pos) /*!< 0x00800000 */ +#define I3C_IER_STAIE I3C_IER_STAIE_Msk /*!< Get Status Interrupt Enable */ +#define I3C_IER_DAUPDIE_Pos (24UL) +#define I3C_IER_DAUPDIE_Msk (0x1UL << I3C_IER_DAUPDIE_Pos) /*!< 0x01000000 */ +#define I3C_IER_DAUPDIE I3C_IER_DAUPDIE_Msk /*!< Dynamic Address Update Interrupt Enable */ +#define I3C_IER_MWLUPDIE_Pos (25UL) +#define I3C_IER_MWLUPDIE_Msk (0x1UL << I3C_IER_MWLUPDIE_Pos) /*!< 0x02000000 */ +#define I3C_IER_MWLUPDIE I3C_IER_MWLUPDIE_Msk /*!< Max Write Length Update Interrupt Enable */ +#define I3C_IER_MRLUPDIE_Pos (26UL) +#define I3C_IER_MRLUPDIE_Msk (0x1UL << I3C_IER_MRLUPDIE_Pos) /*!< 0x04000000 */ +#define I3C_IER_MRLUPDIE I3C_IER_MRLUPDIE_Msk /*!< Max Read Length Update Interrupt Enable */ +#define I3C_IER_RSTIE_Pos (27UL) +#define I3C_IER_RSTIE_Msk (0x1UL << I3C_IER_RSTIE_Pos) /*!< 0x08000000 */ +#define I3C_IER_RSTIE I3C_IER_RSTIE_Msk /*!< Reset Interrupt Enabled, due to Reset pattern received */ +#define I3C_IER_ASUPDIE_Pos (28UL) +#define I3C_IER_ASUPDIE_Msk (0x1UL << I3C_IER_ASUPDIE_Pos) /*!< 0x10000000 */ +#define I3C_IER_ASUPDIE I3C_IER_ASUPDIE_Msk /*!< Activity State Interrupt Enable */ +#define I3C_IER_INTUPDIE_Pos (29UL) +#define I3C_IER_INTUPDIE_Msk (0x1UL << I3C_IER_INTUPDIE_Pos) /*!< 0x20000000 */ +#define I3C_IER_INTUPDIE I3C_IER_INTUPDIE_Msk /*!< Interrupt Update Interrupt Enable */ +#define I3C_IER_DEFIE_Pos (30UL) +#define I3C_IER_DEFIE_Msk (0x1UL << I3C_IER_DEFIE_Pos) /*!< 0x40000000 */ +#define I3C_IER_DEFIE I3C_IER_DEFIE_Msk /*!< List of Targets Command Received Interrupt Enable */ +#define I3C_IER_GRPIE_Pos (31UL) +#define I3C_IER_GRPIE_Msk (0x1UL << I3C_IER_GRPIE_Pos) /*!< 0x80000000 */ +#define I3C_IER_GRPIE I3C_IER_GRPIE_Msk /*!< List of Group Addresses Command Received Interrupt Enable */ + +/******************* Bit definition for I3C_CEVR register *******************/ +#define I3C_CEVR_CFCF_Pos (9UL) +#define I3C_CEVR_CFCF_Msk (0x1UL << I3C_CEVR_CFCF_Pos) /*!< 0x00000200 */ +#define I3C_CEVR_CFCF I3C_CEVR_CFCF_Msk /*!< Frame Complete Clear Flag */ +#define I3C_CEVR_CRXTGTENDF_Pos (10UL) +#define I3C_CEVR_CRXTGTENDF_Msk (0x1UL << I3C_CEVR_CRXTGTENDF_Pos) /*!< 0x00000400 */ +#define I3C_CEVR_CRXTGTENDF I3C_CEVR_CRXTGTENDF_Msk /*!< Reception Target End Clear Flag */ +#define I3C_CEVR_CERRF_Pos (11UL) +#define I3C_CEVR_CERRF_Msk (0x1UL << I3C_CEVR_CERRF_Pos) /*!< 0x00000800 */ +#define I3C_CEVR_CERRF I3C_CEVR_CERRF_Msk /*!< Error Clear Flag */ +#define I3C_CEVR_CIBIF_Pos (15UL) +#define I3C_CEVR_CIBIF_Msk (0x1UL << I3C_CEVR_CIBIF_Pos) /*!< 0x00008000 */ +#define I3C_CEVR_CIBIF I3C_CEVR_CIBIF_Msk /*!< IBI Clear Flag */ +#define I3C_CEVR_CIBIENDF_Pos (16UL) +#define I3C_CEVR_CIBIENDF_Msk (0x1UL << I3C_CEVR_CIBIENDF_Pos) /*!< 0x00010000 */ +#define I3C_CEVR_CIBIENDF I3C_CEVR_CIBIENDF_Msk /*!< IBI End Clear Flag */ +#define I3C_CEVR_CCRF_Pos (17UL) +#define I3C_CEVR_CCRF_Msk (0x1UL << I3C_CEVR_CCRF_Pos) /*!< 0x00020000 */ +#define I3C_CEVR_CCRF I3C_CEVR_CCRF_Msk /*!< Controller-role Clear Flag */ +#define I3C_CEVR_CCRUPDF_Pos (18UL) +#define I3C_CEVR_CCRUPDF_Msk (0x1UL << I3C_CEVR_CCRUPDF_Pos) /*!< 0x00040000 */ +#define I3C_CEVR_CCRUPDF I3C_CEVR_CCRUPDF_Msk /*!< Controller-role Update Clear Flag */ +#define I3C_CEVR_CHJF_Pos (19UL) +#define I3C_CEVR_CHJF_Msk (0x1UL << I3C_CEVR_CHJF_Pos) /*!< 0x00080000 */ +#define I3C_CEVR_CHJF I3C_CEVR_CHJF_Msk /*!< Hot Join Clear Flag */ +#define I3C_CEVR_CWKPF_Pos (21UL) +#define I3C_CEVR_CWKPF_Msk (0x1UL << I3C_CEVR_CWKPF_Pos) /*!< 0x00200000 */ +#define I3C_CEVR_CWKPF I3C_CEVR_CWKPF_Msk /*!< Wake Up Clear Flag */ +#define I3C_CEVR_CGETF_Pos (22UL) +#define I3C_CEVR_CGETF_Msk (0x1UL << I3C_CEVR_CGETF_Pos) /*!< 0x00400000 */ +#define I3C_CEVR_CGETF I3C_CEVR_CGETF_Msk /*!< Get type CCC received Clear Flag */ +#define I3C_CEVR_CSTAF_Pos (23UL) +#define I3C_CEVR_CSTAF_Msk (0x1UL << I3C_CEVR_CSTAF_Pos) /*!< 0x00800000 */ +#define I3C_CEVR_CSTAF I3C_CEVR_CSTAF_Msk /*!< Get Status Clear Flag */ +#define I3C_CEVR_CDAUPDF_Pos (24UL) +#define I3C_CEVR_CDAUPDF_Msk (0x1UL << I3C_CEVR_CDAUPDF_Pos) /*!< 0x01000000 */ +#define I3C_CEVR_CDAUPDF I3C_CEVR_CDAUPDF_Msk /*!< Dynamic Address Update Clear Flag */ +#define I3C_CEVR_CMWLUPDF_Pos (25UL) +#define I3C_CEVR_CMWLUPDF_Msk (0x1UL << I3C_CEVR_CMWLUPDF_Pos) /*!< 0x02000000 */ +#define I3C_CEVR_CMWLUPDF I3C_CEVR_CMWLUPDF_Msk /*!< Max Write Length Update Clear Flag */ +#define I3C_CEVR_CMRLUPDF_Pos (26UL) +#define I3C_CEVR_CMRLUPDF_Msk (0x1UL << I3C_CEVR_CMRLUPDF_Pos) /*!< 0x04000000 */ +#define I3C_CEVR_CMRLUPDF I3C_CEVR_CMRLUPDF_Msk /*!< Max Read Length Update Clear Flag */ +#define I3C_CEVR_CRSTF_Pos (27UL) +#define I3C_CEVR_CRSTF_Msk (0x1UL << I3C_CEVR_CRSTF_Pos) /*!< 0x08000000 */ +#define I3C_CEVR_CRSTF I3C_CEVR_CRSTF_Msk /*!< Reset Flag, due to Reset pattern received */ +#define I3C_CEVR_CASUPDF_Pos (28UL) +#define I3C_CEVR_CASUPDF_Msk (0x1UL << I3C_CEVR_CASUPDF_Pos) /*!< 0x10000000 */ +#define I3C_CEVR_CASUPDF I3C_CEVR_CASUPDF_Msk /*!< Activity State Clear Flag */ +#define I3C_CEVR_CINTUPDF_Pos (29UL) +#define I3C_CEVR_CINTUPDF_Msk (0x1UL << I3C_CEVR_CINTUPDF_Pos) /*!< 0x20000000 */ +#define I3C_CEVR_CINTUPDF I3C_CEVR_CINTUPDF_Msk /*!< Interrupt Update Clear Flag */ +#define I3C_CEVR_CDEFF_Pos (30UL) +#define I3C_CEVR_CDEFF_Msk (0x1UL << I3C_CEVR_CDEFF_Pos) /*!< 0x40000000 */ +#define I3C_CEVR_CDEFF I3C_CEVR_CDEFF_Msk /*!< List of Targets Command Received Clear Flag */ +#define I3C_CEVR_CGRPF_Pos (31UL) +#define I3C_CEVR_CGRPF_Msk (0x1UL << I3C_CEVR_CGRPF_Pos) /*!< 0x80000000 */ +#define I3C_CEVR_CGRPF I3C_CEVR_CGRPF_Msk /*!< List of Group Addresses Command Received Clear Flag */ + +/******************* Bit definition for I3C_MISR register *******************/ +#define I3C_MISR_CFNFMIS_Pos (2UL) +#define I3C_MISR_CFNFMIS_Msk (0x1UL << I3C_MISR_CFNFMIS_Pos) /*!< 0x00000004 */ +#define I3C_MISR_CFNFMIS I3C_MISR_CFNFMIS_Msk /*!< Control FIFO Not Full Mask Interrupt Status */ +#define I3C_MISR_SFNEMIS_Pos (3UL) +#define I3C_MISR_SFNEMIS_Msk (0x1UL << I3C_MISR_SFNEMIS_Pos) /*!< 0x00000008 */ +#define I3C_MISR_SFNEMIS I3C_MISR_SFNEMIS_Msk /*!< Status FIFO Not Empty Mask Interrupt Status */ +#define I3C_MISR_TXFNFMIS_Pos (4UL) +#define I3C_MISR_TXFNFMIS_Msk (0x1UL << I3C_MISR_TXFNFMIS_Pos) /*!< 0x00000010 */ +#define I3C_MISR_TXFNFMIS I3C_MISR_TXFNFMIS_Msk /*!< TX FIFO Not Full Mask Interrupt Status */ +#define I3C_MISR_RXFNEMIS_Pos (5UL) +#define I3C_MISR_RXFNEMIS_Msk (0x1UL << I3C_MISR_RXFNEMIS_Pos) /*!< 0x00000020 */ +#define I3C_MISR_RXFNEMIS I3C_MISR_RXFNEMIS_Msk /*!< RX FIFO Not Empty Mask Interrupt Status */ +#define I3C_MISR_FCMIS_Pos (9UL) +#define I3C_MISR_FCMIS_Msk (0x1UL << I3C_MISR_FCMIS_Pos) /*!< 0x00000200 */ +#define I3C_MISR_FCMIS I3C_MISR_FCMIS_Msk /*!< Frame Complete Mask Interrupt Status */ +#define I3C_MISR_RXTGTENDMIS_Pos (10UL) +#define I3C_MISR_RXTGTENDMIS_Msk (0x1UL << I3C_MISR_RXTGTENDMIS_Pos) /*!< 0x00000400 */ +#define I3C_MISR_RXTGTENDMIS I3C_MISR_RXTGTENDMIS_Msk /*!< Reception Target End Mask Interrupt Status */ +#define I3C_MISR_ERRMIS_Pos (11UL) +#define I3C_MISR_ERRMIS_Msk (0x1UL << I3C_MISR_ERRMIS_Pos) /*!< 0x00000800 */ +#define I3C_MISR_ERRMIS I3C_MISR_ERRMIS_Msk /*!< Error Mask Interrupt Status */ +#define I3C_MISR_IBIMIS_Pos (15UL) +#define I3C_MISR_IBIMIS_Msk (0x1UL << I3C_MISR_IBIMIS_Pos) /*!< 0x00008000 */ +#define I3C_MISR_IBIMIS I3C_MISR_IBIMIS_Msk /*!< IBI Mask Interrupt Status */ +#define I3C_MISR_IBIENDMIS_Pos (16UL) +#define I3C_MISR_IBIENDMIS_Msk (0x1UL << I3C_MISR_IBIENDMIS_Pos) /*!< 0x00010000 */ +#define I3C_MISR_IBIENDMIS I3C_MISR_IBIENDMIS_Msk /*!< IBI End Mask Interrupt Status */ +#define I3C_MISR_CRMIS_Pos (17UL) +#define I3C_MISR_CRMIS_Msk (0x1UL << I3C_MISR_CRMIS_Pos) /*!< 0x00020000 */ +#define I3C_MISR_CRMIS I3C_MISR_CRMIS_Msk /*!< Controller-role Mask Interrupt Status */ +#define I3C_MISR_CRUPDMIS_Pos (18UL) +#define I3C_MISR_CRUPDMIS_Msk (0x1UL << I3C_MISR_CRUPDMIS_Pos) /*!< 0x00040000 */ +#define I3C_MISR_CRUPDMIS I3C_MISR_CRUPDMIS_Msk /*!< Controller-role Update Mask Interrupt Status */ +#define I3C_MISR_HJMIS_Pos (19UL) +#define I3C_MISR_HJMIS_Msk (0x1UL << I3C_MISR_HJMIS_Pos) /*!< 0x00080000 */ +#define I3C_MISR_HJMIS I3C_MISR_HJMIS_Msk /*!< Hot Join Mask Interrupt Status */ +#define I3C_MISR_WKPMIS_Pos (21UL) +#define I3C_MISR_WKPMIS_Msk (0x1UL << I3C_MISR_WKPMIS_Pos) /*!< 0x00200000 */ +#define I3C_MISR_WKPMIS I3C_MISR_WKPMIS_Msk /*!< Wake Up Mask Interrupt Status */ +#define I3C_MISR_GETMIS_Pos (22UL) +#define I3C_MISR_GETMIS_Msk (0x1UL << I3C_MISR_GETMIS_Pos) /*!< 0x00400000 */ +#define I3C_MISR_GETMIS I3C_MISR_GETMIS_Msk /*!< Get type CCC received Mask Interrupt Status */ +#define I3C_MISR_STAMIS_Pos (23UL) +#define I3C_MISR_STAMIS_Msk (0x1UL << I3C_MISR_STAMIS_Pos) /*!< 0x00800000 */ +#define I3C_MISR_STAMIS I3C_MISR_STAMIS_Msk /*!< Get Status Mask Interrupt Status */ +#define I3C_MISR_DAUPDMIS_Pos (24UL) +#define I3C_MISR_DAUPDMIS_Msk (0x1UL << I3C_MISR_DAUPDMIS_Pos) /*!< 0x01000000 */ +#define I3C_MISR_DAUPDMIS I3C_MISR_DAUPDMIS_Msk /*!< Dynamic Address Update Mask Interrupt Status */ +#define I3C_MISR_MWLUPDMIS_Pos (25UL) +#define I3C_MISR_MWLUPDMIS_Msk (0x1UL << I3C_MISR_MWLUPDMIS_Pos) /*!< 0x02000000 */ +#define I3C_MISR_MWLUPDMIS I3C_MISR_MWLUPDMIS_Msk /*!< Max Write Length Update Mask Interrupt Status */ +#define I3C_MISR_MRLUPDMIS_Pos (26UL) +#define I3C_MISR_MRLUPDMIS_Msk (0x1UL << I3C_MISR_MRLUPDMIS_Pos) /*!< 0x04000000 */ +#define I3C_MISR_MRLUPDMIS I3C_MISR_MRLUPDMIS_Msk /*!< Max Read Length Update Mask Interrupt Status */ +#define I3C_MISR_RSTMIS_Pos (27UL) +#define I3C_MISR_RSTMIS_Msk (0x1UL << I3C_MISR_RSTMIS_Pos) /*!< 0x08000000 */ +#define I3C_MISR_RSTMIS I3C_MISR_RSTMIS_Msk /*!< Reset Mask Interrupt Status, due to Reset pattern received */ +#define I3C_MISR_ASUPDMIS_Pos (28UL) +#define I3C_MISR_ASUPDMIS_Msk (0x1UL << I3C_MISR_ASUPDMIS_Pos) /*!< 0x10000000 */ +#define I3C_MISR_ASUPDMIS I3C_MISR_ASUPDMIS_Msk /*!< Activity State Mask Interrupt Status */ +#define I3C_MISR_INTUPDMIS_Pos (29UL) +#define I3C_MISR_INTUPDMIS_Msk (0x1UL << I3C_MISR_INTUPDMIS_Pos) /*!< 0x20000000 */ +#define I3C_MISR_INTUPDMIS I3C_MISR_INTUPDMIS_Msk /*!< Interrupt Update Mask Interrupt Status */ +#define I3C_MISR_DEFMIS_Pos (30UL) +#define I3C_MISR_DEFMIS_Msk (0x1UL << I3C_MISR_DEFMIS_Pos) /*!< 0x40000000 */ +#define I3C_MISR_DEFMIS I3C_MISR_DEFMIS_Msk /*!< List of Targets Command Received Mask Interrupt Status */ +#define I3C_MISR_GRPMIS_Pos (31UL) +#define I3C_MISR_GRPMIS_Msk (0x1UL << I3C_MISR_GRPMIS_Pos) /*!< 0x80000000 */ +#define I3C_MISR_GRPMIS I3C_MISR_GRPMIS_Msk /*!< List of Group Addresses Command Received Mask Interrupt Status */ + +/****************** Bit definition for I3C_DEVR0 register *******************/ +#define I3C_DEVR0_DAVAL_Pos (0UL) +#define I3C_DEVR0_DAVAL_Msk (0x1UL << I3C_DEVR0_DAVAL_Pos) /*!< 0x00000001 */ +#define I3C_DEVR0_DAVAL I3C_DEVR0_DAVAL_Msk /*!< Dynamic Address Validity */ +#define I3C_DEVR0_DA_Pos (1UL) +#define I3C_DEVR0_DA_Msk (0x7FUL << I3C_DEVR0_DA_Pos) /*!< 0x000000FE */ +#define I3C_DEVR0_DA I3C_DEVR0_DA_Msk /*!< Own Target Device Address */ +#define I3C_DEVR0_IBIEN_Pos (16UL) +#define I3C_DEVR0_IBIEN_Msk (0x1UL << I3C_DEVR0_IBIEN_Pos) /*!< 0x00010000 */ +#define I3C_DEVR0_IBIEN I3C_DEVR0_IBIEN_Msk /*!< IBI Enable */ +#define I3C_DEVR0_CREN_Pos (17UL) +#define I3C_DEVR0_CREN_Msk (0x1UL << I3C_DEVR0_CREN_Pos) /*!< 0x00020000 */ +#define I3C_DEVR0_CREN I3C_DEVR0_CREN_Msk /*!< Controller-role Enable */ +#define I3C_DEVR0_HJEN_Pos (19UL) +#define I3C_DEVR0_HJEN_Msk (0x1UL << I3C_DEVR0_HJEN_Pos) /*!< 0x00080000 */ +#define I3C_DEVR0_HJEN I3C_DEVR0_HJEN_Msk /*!< Hot Join Enable */ +#define I3C_DEVR0_AS_Pos (20UL) +#define I3C_DEVR0_AS_Msk (0x3UL << I3C_DEVR0_AS_Pos) /*!< 0x00300000 */ +#define I3C_DEVR0_AS I3C_DEVR0_AS_Msk /*!< Activity State value update after ENTAx received */ +#define I3C_DEVR0_AS_0 (0x1UL << I3C_DEVR0_AS_Pos) /*!< 0x00100000 */ +#define I3C_DEVR0_AS_1 (0x2UL << I3C_DEVR0_AS_Pos) /*!< 0x00200000 */ +#define I3C_DEVR0_RSTACT_Pos (22UL) +#define I3C_DEVR0_RSTACT_Msk (0x3UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00C000000 */ +#define I3C_DEVR0_RSTACT I3C_DEVR0_RSTACT_Msk /*!< Reset Action value update after RSTACT received */ +#define I3C_DEVR0_RSTACT_0 (0x1UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00400000 */ +#define I3C_DEVR0_RSTACT_1 (0x2UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00800000 */ +#define I3C_DEVR0_RSTVAL_Pos (24UL) +#define I3C_DEVR0_RSTVAL_Msk (0x1UL << I3C_DEVR0_RSTVAL_Pos) /*!< 0x01000000 */ +#define I3C_DEVR0_RSTVAL I3C_DEVR0_RSTVAL_Msk /*!< Reset Action Valid */ + +/****************** Bit definition for I3C_DEVRX register *******************/ +#define I3C_DEVRX_DA_Pos (1UL) +#define I3C_DEVRX_DA_Msk (0x7FUL << I3C_DEVRX_DA_Pos) /*!< 0x000000FE */ +#define I3C_DEVRX_DA I3C_DEVRX_DA_Msk /*!< Dynamic Address Target x */ +#define I3C_DEVRX_IBIACK_Pos (16UL) +#define I3C_DEVRX_IBIACK_Msk (0x1UL << I3C_DEVRX_IBIACK_Pos) /*!< 0x00010000 */ +#define I3C_DEVRX_IBIACK I3C_DEVRX_IBIACK_Msk /*!< IBI Acknowledge from Target x */ +#define I3C_DEVRX_CRACK_Pos (17UL) +#define I3C_DEVRX_CRACK_Msk (0x1UL << I3C_DEVRX_CRACK_Pos) /*!< 0x00020000 */ +#define I3C_DEVRX_CRACK I3C_DEVRX_CRACK_Msk /*!< Controller-role Acknowledge from Target x */ +#define I3C_DEVRX_IBIDEN_Pos (18UL) +#define I3C_DEVRX_IBIDEN_Msk (0x1UL << I3C_DEVRX_IBIDEN_Pos) /*!< 0x00040000 */ +#define I3C_DEVRX_IBIDEN I3C_DEVRX_IBIDEN_Msk /*!< IBI Additional Data Enable */ +#define I3C_DEVRX_SUSP_Pos (19UL) +#define I3C_DEVRX_SUSP_Msk (0x1UL << I3C_DEVRX_SUSP_Pos) /*!< 0x00080000 */ +#define I3C_DEVRX_SUSP I3C_DEVRX_SUSP_Msk /*!< Suspended Transfer */ +#define I3C_DEVRX_DIS_Pos (31UL) +#define I3C_DEVRX_DIS_Msk (0x1UL << I3C_DEVRX_DIS_Pos) /*!< 0x80000000 */ +#define I3C_DEVRX_DIS I3C_DEVRX_DIS_Msk /*!< Disable Register access */ + +/****************** Bit definition for I3C_MAXRLR register ******************/ +#define I3C_MAXRLR_MRL_Pos (0UL) +#define I3C_MAXRLR_MRL_Msk (0xFFFFUL << I3C_MAXRLR_MRL_Pos) /*!< 0x0000FFFF */ +#define I3C_MAXRLR_MRL I3C_MAXRLR_MRL_Msk /*!< Maximum Read Length */ +#define I3C_MAXRLR_IBIP_Pos (16UL) +#define I3C_MAXRLR_IBIP_Msk (0x7UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00070000 */ +#define I3C_MAXRLR_IBIP I3C_MAXRLR_IBIP_Msk /*!< IBI Payload size */ +#define I3C_MAXRLR_IBIP_0 (0x1UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00010000 */ +#define I3C_MAXRLR_IBIP_1 (0x2UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00020000 */ +#define I3C_MAXRLR_IBIP_2 (0x4UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00040000 */ + +/****************** Bit definition for I3C_MAXWLR register ******************/ +#define I3C_MAXWLR_MWL_Pos (0UL) +#define I3C_MAXWLR_MWL_Msk (0xFFFFUL << I3C_MAXWLR_MWL_Pos) /*!< 0x0000FFFF */ +#define I3C_MAXWLR_MWL I3C_MAXWLR_MWL_Msk /*!< Maximum Write Length */ + +/**************** Bit definition for I3C_TIMINGR0 register ******************/ +#define I3C_TIMINGR0_SCLL_PP_Pos (0UL) +#define I3C_TIMINGR0_SCLL_PP_Msk (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos) /*!< 0x000000FF */ +#define I3C_TIMINGR0_SCLL_PP I3C_TIMINGR0_SCLL_PP_Msk /*!< SCL Low duration during I3C Push-Pull phases */ +#define I3C_TIMINGR0_SCLH_I3C_Pos (8UL) +#define I3C_TIMINGR0_SCLH_I3C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos) /*!< 0x0000FF00 */ +#define I3C_TIMINGR0_SCLH_I3C I3C_TIMINGR0_SCLH_I3C_Msk /*!< SCL High duration during I3C Open-drain and Push-Pull phases */ +#define I3C_TIMINGR0_SCLL_OD_Pos (16UL) +#define I3C_TIMINGR0_SCLL_OD_Msk (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos) /*!< 0x00FF0000 */ +#define I3C_TIMINGR0_SCLL_OD I3C_TIMINGR0_SCLL_OD_Msk /*!< SCL Low duration during I3C Open-drain phases and I2C transfer */ +#define I3C_TIMINGR0_SCLH_I2C_Pos (24UL) +#define I3C_TIMINGR0_SCLH_I2C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos) /*!< 0xFF000000 */ +#define I3C_TIMINGR0_SCLH_I2C I3C_TIMINGR0_SCLH_I2C_Msk /*!< SCL High duration during I2C transfer */ + +/**************** Bit definition for I3C_TIMINGR1 register ******************/ +#define I3C_TIMINGR1_AVAL_Pos (0UL) +#define I3C_TIMINGR1_AVAL_Msk (0xFFUL << I3C_TIMINGR1_AVAL_Pos) /*!< 0x000000FF */ +#define I3C_TIMINGR1_AVAL I3C_TIMINGR1_AVAL_Msk /*!< Timing for I3C Bus Idle or Available condition */ +#define I3C_TIMINGR1_ASNCR_Pos (8UL) +#define I3C_TIMINGR1_ASNCR_Msk (0x3UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000300 */ +#define I3C_TIMINGR1_ASNCR I3C_TIMINGR1_ASNCR_Msk /*!< Activity State of the New Controller */ +#define I3C_TIMINGR1_ASNCR_0 (0x1UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000100 */ +#define I3C_TIMINGR1_ASNCR_1 (0x2UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000200 */ +#define I3C_TIMINGR1_FREE_Pos (16UL) +#define I3C_TIMINGR1_FREE_Msk (0x7FUL << I3C_TIMINGR1_FREE_Pos) /*!< 0x007F0000 */ +#define I3C_TIMINGR1_FREE I3C_TIMINGR1_FREE_Msk /*!< Timing for I3C Bus Free condition */ +#define I3C_TIMINGR1_SDA_HD_Pos (28UL) +#define I3C_TIMINGR1_SDA_HD_Msk (0x3UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x30000000 */ +#define I3C_TIMINGR1_SDA_HD I3C_TIMINGR1_SDA_HD_Msk /*!< SDA Hold Duration */ +#define I3C_TIMINGR1_SDA_HD_0 (0x1UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x10000000 */ +#define I3C_TIMINGR1_SDA_HD_1 (0x2UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for I3C_TIMINGR2 register ******************/ +#define I3C_TIMINGR2_STALLT_Pos (0UL) +#define I3C_TIMINGR2_STALLT_Msk (0x1UL << I3C_TIMINGR2_STALLT_Pos) /*!< 0x00000001 */ +#define I3C_TIMINGR2_STALLT I3C_TIMINGR2_STALLT_Msk /*!< Stall on T bit */ +#define I3C_TIMINGR2_STALLD_Pos (1UL) +#define I3C_TIMINGR2_STALLD_Msk (0x1UL << I3C_TIMINGR2_STALLD_Pos) /*!< 0x00000002 */ +#define I3C_TIMINGR2_STALLD I3C_TIMINGR2_STALLD_Msk /*!< Stall on PAR bit of data bytes */ +#define I3C_TIMINGR2_STALLC_Pos (2UL) +#define I3C_TIMINGR2_STALLC_Msk (0x1UL << I3C_TIMINGR2_STALLC_Pos) /*!< 0x00000004 */ +#define I3C_TIMINGR2_STALLC I3C_TIMINGR2_STALLC_Msk /*!< Stall on PAR bit of CCC byte */ +#define I3C_TIMINGR2_STALLA_Pos (3UL) +#define I3C_TIMINGR2_STALLA_Msk (0x1UL << I3C_TIMINGR2_STALLA_Pos) /*!< 0x00000008 */ +#define I3C_TIMINGR2_STALLA I3C_TIMINGR2_STALLA_Msk /*!< Stall on ACK bit */ +#define I3C_TIMINGR2_STALLR_Pos (4UL) +#define I3C_TIMINGR2_STALLR_Msk (0x1UL << I3C_TIMINGR2_STALLR_Pos) /*!< 0x00000010 */ +#define I3C_TIMINGR2_STALLR I3C_TIMINGR2_STALLR_Msk /*!< Stall on I2C Read ACK bit */ +#define I3C_TIMINGR2_STALLS_Pos (5UL) +#define I3C_TIMINGR2_STALLS_Msk (0x1UL << I3C_TIMINGR2_STALLS_Pos) /*!< 0x00000020 */ +#define I3C_TIMINGR2_STALLS I3C_TIMINGR2_STALLS_Msk /*!< Stall on I2C Write ACK bit */ +#define I3C_TIMINGR2_STALLL_Pos (6UL) +#define I3C_TIMINGR2_STALLL_Msk (0x1UL << I3C_TIMINGR2_STALLL_Pos) /*!< 0x00000040 */ +#define I3C_TIMINGR2_STALLL I3C_TIMINGR2_STALLL_Msk /*!< Stall on I2C Address ACK bit */ +#define I3C_TIMINGR2_STALL_Pos (8UL) +#define I3C_TIMINGR2_STALL_Msk (0xFFUL << I3C_TIMINGR2_STALL_Pos) /*!< 0x0000FF00 */ +#define I3C_TIMINGR2_STALL I3C_TIMINGR2_STALL_Msk /*!< Controller Stall duration */ + +/******************* Bit definition for I3C_BCR register ********************/ +#define I3C_BCR_BCR_Pos (0UL) +#define I3C_BCR_BCR_Msk (0xFFUL << I3C_BCR_BCR_Pos) /*!< 0x000000FF */ +#define I3C_BCR_BCR I3C_BCR_BCR_Msk /*!< Bus Characteristics */ +#define I3C_BCR_BCR0_Pos (0UL) +#define I3C_BCR_BCR0_Msk (0x1UL << I3C_BCR_BCR0_Pos) /*!< 0x00000001 */ +#define I3C_BCR_BCR0 I3C_BCR_BCR0_Msk /*!< Max Data Speed Limitation */ +#define I3C_BCR_BCR1_Pos (1UL) +#define I3C_BCR_BCR1_Msk (0x1UL << I3C_BCR_BCR1_Pos) /*!< 0x00000002 */ +#define I3C_BCR_BCR1 I3C_BCR_BCR1_Msk /*!< IBI Request capable */ +#define I3C_BCR_BCR2_Pos (2UL) +#define I3C_BCR_BCR2_Msk (0x1UL << I3C_BCR_BCR2_Pos) /*!< 0x00000004 */ +#define I3C_BCR_BCR2 I3C_BCR_BCR2_Msk /*!< IBI Payload additional Mandatory Data Byte */ +#define I3C_BCR_BCR3_Pos (3UL) +#define I3C_BCR_BCR3_Msk (0x1UL << I3C_BCR_BCR3_Pos) /*!< 0x00000008 */ +#define I3C_BCR_BCR3 I3C_BCR_BCR3_Msk /*!< Offline capable */ +#define I3C_BCR_BCR4_Pos (4UL) +#define I3C_BCR_BCR4_Msk (0x1UL << I3C_BCR_BCR4_Pos) /*!< 0x00000010 */ +#define I3C_BCR_BCR4 I3C_BCR_BCR4_Msk /*!< Virtual target support */ +#define I3C_BCR_BCR5_Pos (5UL) +#define I3C_BCR_BCR5_Msk (0x1UL << I3C_BCR_BCR5_Pos) /*!< 0x00000020 */ +#define I3C_BCR_BCR5 I3C_BCR_BCR5_Msk /*!< Advanced capabilities */ +#define I3C_BCR_BCR6_Pos (6UL) +#define I3C_BCR_BCR6_Msk (0x1UL << I3C_BCR_BCR6_Pos) /*!< 0x00000040 */ +#define I3C_BCR_BCR6 I3C_BCR_BCR6_Msk /*!< Device Role shared during Dynamic Address Assignment */ + +/******************* Bit definition for I3C_DCR register ********************/ +#define I3C_DCR_DCR_Pos (0UL) +#define I3C_DCR_DCR_Msk (0xFFUL << I3C_DCR_DCR_Pos) /*!< 0x000000FF */ +#define I3C_DCR_DCR I3C_DCR_DCR_Msk /*!< Devices Characteristics */ + +/***************** Bit definition for I3C_GETCAPR register ******************/ +#define I3C_GETCAPR_CAPPEND_Pos (14UL) +#define I3C_GETCAPR_CAPPEND_Msk (0x1UL << I3C_GETCAPR_CAPPEND_Pos) /*!< 0x00004000 */ +#define I3C_GETCAPR_CAPPEND I3C_GETCAPR_CAPPEND_Msk /*!< IBI Request with Mandatory Data Byte */ + +/***************** Bit definition for I3C_CRCAPR register *******************/ +#define I3C_CRCAPR_CAPDHOFF_Pos (3UL) +#define I3C_CRCAPR_CAPDHOFF_Msk (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos) /*!< 0x00000008 */ +#define I3C_CRCAPR_CAPDHOFF I3C_CRCAPR_CAPDHOFF_Msk /*!< Controller-role handoff needed */ +#define I3C_CRCAPR_CAPGRP_Pos (9UL) +#define I3C_CRCAPR_CAPGRP_Msk (0x1UL << I3C_CRCAPR_CAPGRP_Pos) /*!< 0x00000200 */ +#define I3C_CRCAPR_CAPGRP I3C_CRCAPR_CAPGRP_Msk /*!< Group Address handoff supported */ + +/**************** Bit definition for I3C_GETMXDSR register ******************/ +#define I3C_GETMXDSR_HOFFAS_Pos (0UL) +#define I3C_GETMXDSR_HOFFAS_Msk (0x3UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000003 */ +#define I3C_GETMXDSR_HOFFAS I3C_GETMXDSR_HOFFAS_Msk /*!< Handoff Activity State */ +#define I3C_GETMXDSR_HOFFAS_0 (0x1UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000001 */ +#define I3C_GETMXDSR_HOFFAS_1 (0x2UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000002 */ +#define I3C_GETMXDSR_FMT_Pos (8UL) +#define I3C_GETMXDSR_FMT_Msk (0x3UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000300 */ +#define I3C_GETMXDSR_FMT I3C_GETMXDSR_FMT_Msk /*!< Get Max Data Speed response in format 2 */ +#define I3C_GETMXDSR_FMT_0 (0x1UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000100 */ +#define I3C_GETMXDSR_FMT_1 (0x2UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000200 */ +#define I3C_GETMXDSR_RDTURN_Pos (16UL) +#define I3C_GETMXDSR_RDTURN_Msk (0xFFUL << I3C_GETMXDSR_RDTURN_Pos) /*!< 0x00FF0000 */ +#define I3C_GETMXDSR_RDTURN I3C_GETMXDSR_RDTURN_Msk /*!< Max Read Turnaround Middle Byte */ +#define I3C_GETMXDSR_TSCO_Pos (24UL) +#define I3C_GETMXDSR_TSCO_Msk (0x1UL << I3C_GETMXDSR_TSCO_Pos) /*!< 0x01000000 */ +#define I3C_GETMXDSR_TSCO I3C_GETMXDSR_TSCO_Msk /*!< Clock-to-data Turnaround time */ + +/****************** Bit definition for I3C_EPIDR register *******************/ +#define I3C_EPIDR_MIPIID_Pos (12UL) +#define I3C_EPIDR_MIPIID_Msk (0xFUL << I3C_EPIDR_MIPIID_Pos) /*!< 0x0000F000 */ +#define I3C_EPIDR_MIPIID I3C_EPIDR_MIPIID_Msk /*!< MIPI Instance ID */ +#define I3C_EPIDR_IDTSEL_Pos (16UL) +#define I3C_EPIDR_IDTSEL_Msk (0x1UL << I3C_EPIDR_IDTSEL_Pos) /*!< 0x00010000 */ +#define I3C_EPIDR_IDTSEL I3C_EPIDR_IDTSEL_Msk /*!< ID Type Selector */ +#define I3C_EPIDR_MIPIMID_Pos (17UL) +#define I3C_EPIDR_MIPIMID_Msk (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos) /*!< 0xFFFE0000 */ +#define I3C_EPIDR_MIPIMID I3C_EPIDR_MIPIMID_Msk /*!< MIPI Manufacturer ID */ + +/******************************************************************************/ +/* */ +/* ICACHE */ +/* */ +/******************************************************************************/ +/****************** Bit definition for ICACHE_CR register *******************/ +#define ICACHE_CR_EN_Pos (0UL) +#define ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) /*!< 0x00000001 */ +#define ICACHE_CR_EN ICACHE_CR_EN_Msk /*!< Enable */ +#define ICACHE_CR_CACHEINV_Pos (1UL) +#define ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ +#define ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk /*!< Cache invalidation */ +#define ICACHE_CR_WAYSEL_Pos (2UL) +#define ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) /*!< 0x00000004 */ +#define ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk /*!< Ways selection */ +#define ICACHE_CR_HITMEN_Pos (16UL) +#define ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) /*!< 0x00010000 */ +#define ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk /*!< Hit monitor enable */ +#define ICACHE_CR_MISSMEN_Pos (17UL) +#define ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) /*!< 0x00020000 */ +#define ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk /*!< Miss monitor enable */ +#define ICACHE_CR_HITMRST_Pos (18UL) +#define ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) /*!< 0x00040000 */ +#define ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk /*!< Hit monitor reset */ +#define ICACHE_CR_MISSMRST_Pos (19UL) +#define ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) /*!< 0x00080000 */ +#define ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk /*!< Miss monitor reset */ + +/****************** Bit definition for ICACHE_SR register *******************/ +#define ICACHE_SR_BUSYF_Pos (0UL) +#define ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk /*!< Busy flag */ +#define ICACHE_SR_BSYENDF_Pos (1UL) +#define ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk /*!< Busy end flag */ +#define ICACHE_SR_ERRF_Pos (2UL) +#define ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk /*!< Cache error flag */ + +/****************** Bit definition for ICACHE_IER register ******************/ +#define ICACHE_IER_BSYENDIE_Pos (1UL) +#define ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */ +#define ICACHE_IER_ERRIE_Pos (2UL) +#define ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk /*!< Cache error interrupt enable */ + +/****************** Bit definition for ICACHE_FCR register ******************/ +#define ICACHE_FCR_CBSYENDF_Pos (1UL) +#define ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk /*!< Busy end flag clear */ +#define ICACHE_FCR_CERRF_Pos (2UL) +#define ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_FCR_CERRF ICACHE_FCR_CERRF_Msk /*!< Cache error flag clear */ + +/****************** Bit definition for ICACHE_HMONR register ****************/ +#define ICACHE_HMONR_HITMON_Pos (0UL) +#define ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */ +#define ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk /*!< Cache hit monitor register */ + +/****************** Bit definition for ICACHE_MMONR register ****************/ +#define ICACHE_MMONR_MISSMON_Pos (0UL) +#define ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */ +#define ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk /*!< Cache miss monitor register */ + +/****************** Bit definition for ICACHE_CRRx register *****************/ +#define ICACHE_CRRx_BASEADDR_Pos (0UL) +#define ICACHE_CRRx_BASEADDR_Msk (0xFFUL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x000000FF */ +#define ICACHE_CRRx_BASEADDR ICACHE_CRRx_BASEADDR_Msk /*!< Base address of region X to remap */ +#define ICACHE_CRRx_RSIZE_Pos (9UL) +#define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00 */ +#define ICACHE_CRRx_RSIZE ICACHE_CRRx_RSIZE_Msk /*!< Region X size */ +#define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200 */ +#define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400 */ +#define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800 */ +#define ICACHE_CRRx_REN_Pos (15UL) +#define ICACHE_CRRx_REN_Msk (0x1UL << ICACHE_CRRx_REN_Pos) /*!< 0x00008000 */ +#define ICACHE_CRRx_REN ICACHE_CRRx_REN_Msk /*!< Region X enable */ +#define ICACHE_CRRx_REMAPADDR_Pos (16UL) +#define ICACHE_CRRx_REMAPADDR_Msk (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x07FF0000 */ +#define ICACHE_CRRx_REMAPADDR ICACHE_CRRx_REMAPADDR_Msk /*!< Remap address of Region X to be remapped */ +#define ICACHE_CRRx_MSTSEL_Pos (28UL) +#define ICACHE_CRRx_MSTSEL_Msk (0x1UL << ICACHE_CRRx_MSTSEL_Pos) /*!< 0x10000000 */ +#define ICACHE_CRRx_MSTSEL ICACHE_CRRx_MSTSEL_Msk /*!< Region X AHB cache master selection */ +#define ICACHE_CRRx_HBURST_Pos (31UL) +#define ICACHE_CRRx_HBURST_Msk (0x1UL << ICACHE_CRRx_HBURST_Pos) /*!< 0x80000000 */ +#define ICACHE_CRRx_HBURST ICACHE_CRRx_HBURST_Msk /*!< Region X output burst type */ + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG */ +/* */ +/******************************************************************************/ +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY_Pos (0UL) +#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ +#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0UL) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4UL) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7UL) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8UL) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12UL) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15UL) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16UL) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20UL) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22UL) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23UL) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24UL) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28UL) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30UL) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31UL) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0UL) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24UL) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31UL) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0UL) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4UL) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7UL) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8UL) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12UL) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15UL) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16UL) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20UL) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22UL) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23UL) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24UL) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28UL) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30UL) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31UL) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0UL) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0UL) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1UL) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2UL) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3UL) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4UL) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5UL) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6UL) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0UL) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1UL) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2UL) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3UL) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4UL) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5UL) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6UL) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0UL) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1UL) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2UL) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3UL) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4UL) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5UL) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6UL) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0UL) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1UL) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2UL) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3UL) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4UL) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5UL) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6UL) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_TAMPTSCR register ******************/ +#define RTC_TAMPTSCR_TAMP1TS_Pos (0UL) +#define RTC_TAMPTSCR_TAMP1TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP1TS_Pos) /*!< 0x00000001 */ +#define RTC_TAMPTSCR_TAMP1TS RTC_TAMPTSCR_TAMP1TS_Msk +#define RTC_TAMPTSCR_TAMP2TS_Pos (1UL) +#define RTC_TAMPTSCR_TAMP2TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP2TS_Pos) /*!< 0x00000002 */ +#define RTC_TAMPTSCR_TAMP2TS RTC_TAMPTSCR_TAMP2TS_Msk +#define RTC_TAMPTSCR_TAMP3TS_Pos (2UL) +#define RTC_TAMPTSCR_TAMP3TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP3TS_Pos) /*!< 0x00000004 */ +#define RTC_TAMPTSCR_TAMP3TS RTC_TAMPTSCR_TAMP3TS_Msk +#define RTC_TAMPTSCR_TAMP4TS_Pos (3UL) +#define RTC_TAMPTSCR_TAMP4TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP4TS_Pos) /*!< 0x00000008 */ +#define RTC_TAMPTSCR_TAMP4TS RTC_TAMPTSCR_TAMP4TS_Msk +#define RTC_TAMPTSCR_TAMP5TS_Pos (4UL) +#define RTC_TAMPTSCR_TAMP5TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP5TS_Pos) /*!< 0x00000010 */ +#define RTC_TAMPTSCR_TAMP5TS RTC_TAMPTSCR_TAMP5TS_Msk +#define RTC_TAMPTSCR_ITAMPTS_Pos (16UL) +#define RTC_TAMPTSCR_ITAMPTS_Msk (0x1UL << RTC_TAMPTSCR_ITAMPTS_Pos) /*!< 0x00010000 */ +#define RTC_TAMPTSCR_ITAMPTS RTC_TAMPTSCR_ITAMPTS_Msk + +/******************** Bits definition for RTC_TSIDR register ******************/ +#define RTC_TSIDR_TSID_Pos (0UL) +#define RTC_TSIDR_TSID_Msk (0x3FUL << RTC_TSIDR_TSID_Pos) /*!< 0x0000003F */ +#define RTC_TSIDR_TSID RTC_TSIDR_TSID_Msk +#define RTC_TSIDR_TSID_0 (0x1UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000001 */ +#define RTC_TSIDR_TSID_1 (0x2UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000002 */ +#define RTC_TSIDR_TSID_2 (0x4UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000004 */ +#define RTC_TSIDR_TSID_3 (0x8UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000008 */ +#define RTC_TSIDR_TSID_4 (0x10UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000010 */ +#define RTC_TSIDR_TSID_5 (0x20UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000020 */ + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0UL) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0UL) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Serial Audio Interface */ +/* */ +/******************************************************************************/ +/******************* Bit definition for SAI_xCR1 register *******************/ +#define SAI_xCR1_MODE_Pos (0UL) +#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ +#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/******************************************************************************/ +/* */ +/* VREFBUF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for VREFBUF_CSR register ****************/ +#define VREFBUF_CSR_ENVR_Pos (0UL) +#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ +#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*! 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + /** * @brief Power Control */ @@ -1625,6 +1646,8 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; #define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0400UL) #define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0710UL) #define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0800UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A2400UL) #define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A8000UL) #define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A8400UL) #define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0x000AF000UL) @@ -1755,6 +1778,8 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; #define HASH_BASE_S (AHB2PERIPH_BASE_S + 0x000A0400UL) #define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0x000A0710UL) #define RNG_BASE_S (AHB2PERIPH_BASE_S + 0x000A0800UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0x000A2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0x000A2400UL) #define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0x000A8000UL) #define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0x000A8400UL) #define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0x000AF000UL) @@ -1770,7 +1795,6 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; /*!< USB PMA SIZE */ #define USB_DRD_PMA_SIZE (2048U) /*!< USB PMA Size 2Kbyte */ -#if defined (CPU_IN_SECURE_STATE) /*!< Root Secure Service Library */ /************ RSSLIB SAU system Flash region definition constants *************/ #define RSSLIB_SYS_FLASH_NS_PFUNC_START 0x0BF99040UL @@ -1785,11 +1809,11 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; #define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) /*!< HDP Area constant definition */ -#define RSSLIB_HDP_AREA_Pos 0U +#define RSSLIB_HDP_AREA_Pos 0UL #define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) -#define RSSLIB_HDP_AREA1_Pos 0U +#define RSSLIB_HDP_AREA1_Pos 0UL #define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) -#define RSSLIB_HDP_AREA2_Pos 1U +#define RSSLIB_HDP_AREA2_Pos 1UL #define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) #define RSSLIB_HDPEXT_CLOSE_BOUNDARY_OPEN 0xC9C9C9C9UL /* Access to HDPx extension area and HDPx area denied but HDPx_EXT (in FLASH_HDPEXTR) increment allowed at any time */ #define RSSLIB_HDPEXT_CLOSE_BOUNDARY_LOCK 0xD6D6D6D6UL /* Access to HDPx extension area and HDPx area denied. Update of HDPx_EXT size is not possible anymore */ @@ -1849,7 +1873,6 @@ typedef struct NSC_pFuncTypeDef NSC; S_pFuncTypeDef S; }RSSLIB_pFunc_TypeDef; -#endif /* CPU_IN_SECURE_STATE */ /* * Certificate address description @@ -1948,6 +1971,7 @@ typedef struct #define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) #define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) #define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) #define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) #define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) #define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) @@ -2056,6 +2080,7 @@ typedef struct #define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) #define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) #define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) #define PWR_S ((PWR_TypeDef *) PWR_BASE_S) #define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) #define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) @@ -2086,7 +2111,7 @@ typedef struct #define TSC_S ((TSC_TypeDef *) TSC_BASE_S) #define UART4_S ((USART_TypeDef *) UART4_BASE_S) #define UART5_S ((USART_TypeDef *) UART5_BASE_S) -#define TIM8_S ((TIM_TypeDef *) TIM18_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) #define USART1_S ((USART_TypeDef *) USART1_BASE_S) #define USART2_S ((USART_TypeDef *) USART2_BASE_S) #define USART3_S ((USART_TypeDef *) USART3_BASE_S) @@ -2234,6 +2259,9 @@ typedef struct #define OPAMP2_BASE OPAMP2_BASE_S #define OPAMP12_COMMON OPAMP12_COMMON_S #define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S #define PWR PWR_S #define PWR_BASE PWR_BASE_S #define RAMCFG_SRAM1 RAMCFG_SRAM1_S @@ -2449,6 +2477,9 @@ typedef struct #define OPAMP2_BASE OPAMP2_BASE_NS #define OPAMP12_COMMON OPAMP12_COMMON_NS #define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS #define PWR PWR_NS #define PWR_BASE PWR_BASE_NS #define RAMCFG_SRAM1 RAMCFG_SRAM1_NS @@ -2554,124 +2585,124 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register *******************/ -#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Pos (0UL) #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ -#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Pos (1UL) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ -#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Pos (2UL) #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ -#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Pos (3UL) #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ -#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Pos (4UL) #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ -#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Pos (5UL) #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ -#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Pos (6UL) #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ -#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Pos (7UL) #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ -#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Pos (8UL) #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ -#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Pos (9UL) #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ -#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Pos (10UL) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ -#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Pos (12UL) #define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ #define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC internal voltage regulator output ready flag */ /******************** Bit definition for ADC_IER register *******************/ -#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Pos (0UL) #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ -#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Pos (1UL) #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ -#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Pos (2UL) #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ -#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Pos (3UL) #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ -#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Pos (4UL) #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ -#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Pos (5UL) #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ -#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Pos (6UL) #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ -#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Pos (7UL) #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ -#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Pos (8UL) #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ -#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Pos (9UL) #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ -#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Pos (10UL) #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ -#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Pos (12UL) #define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ #define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC internal voltage regulator interrupt*/ /******************** Bit definition for ADC_CR register ********************/ -#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Pos (0UL) #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ -#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Pos (1UL) #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ -#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Pos (2UL) #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ -#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Pos (3UL) #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ -#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Pos (4UL) #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ -#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Pos (5UL) #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ -#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Pos (28UL) #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC internal voltage regulator */ -#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Pos (29UL) #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ -#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Pos (31UL) #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR1 register ******************/ -#define ADC_CFGR1_DMNGT_Pos (0U) +#define ADC_CFGR1_DMNGT_Pos (0UL) #define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ #define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC data management configuration */ #define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ #define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ -#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Pos (2UL) #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ #define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ #define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ -#define ADC_CFGR1_EXTSEL_Pos (5U) +#define ADC_CFGR1_EXTSEL_Pos (5UL) #define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ #define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ @@ -2680,55 +2711,55 @@ typedef struct #define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ -#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Pos (10UL) #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ -#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Pos (12UL) #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ -#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Pos (13UL) #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ -#define ADC_CFGR1_AUTDLY_Pos (14U) +#define ADC_CFGR1_AUTDLY_Pos (14UL) #define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC low power auto wait */ -#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Pos (16UL) #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ -#define ADC_CFGR1_DISCNUM_Pos (17U) +#define ADC_CFGR1_DISCNUM_Pos (17UL) #define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ #define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ #define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ #define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ -#define ADC_CFGR1_JDISCEN_Pos (20U) +#define ADC_CFGR1_JDISCEN_Pos (20UL) #define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ -#define ADC_CFGR1_JQM_Pos (21U) +#define ADC_CFGR1_JQM_Pos (21UL) #define ADC_CFGR1_JQM_Msk (0x1UL << ADC_CFGR1_JQM_Pos) /*!< 0x00200000 */ #define ADC_CFGR1_JQM ADC_CFGR1_JQM_Msk /*!< ADC group injected contexts queue mode */ -#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Pos (22UL) #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ -#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Pos (23UL) #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ -#define ADC_CFGR1_JAWD1EN_Pos (24U) +#define ADC_CFGR1_JAWD1EN_Pos (24UL) #define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ -#define ADC_CFGR1_JAUTO_Pos (25U) +#define ADC_CFGR1_JAUTO_Pos (25UL) #define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ -#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Pos (26UL) #define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ #define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ @@ -2737,19 +2768,19 @@ typedef struct #define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ #define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ -#define ADC_CFGR1_JQDIS_Pos (31U) +#define ADC_CFGR1_JQDIS_Pos (31UL) #define ADC_CFGR1_JQDIS_Msk (0x1UL << ADC_CFGR1_JQDIS_Pos) /*!< 0x80000000 */ #define ADC_CFGR1_JQDIS ADC_CFGR1_JQDIS_Msk /*!< ADC group injected contexts queue disable */ /******************** Bit definition for ADC_CFGR2 register *****************/ -#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Pos (0UL) #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ -#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Pos (1UL) #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ -#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Pos (5UL) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ @@ -2757,26 +2788,26 @@ typedef struct #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ -#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Pos (9UL) #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ -#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Pos (10UL) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ -#define ADC_CFGR2_BULB_Pos (13U) +#define ADC_CFGR2_BULB_Pos (13UL) #define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ #define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC bulb sampling mode */ -#define ADC_CFGR2_SWTRIG_Pos (14U) +#define ADC_CFGR2_SWTRIG_Pos (14UL) #define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC software trigger bit for sampling time control trigger mode */ -#define ADC_CFGR2_SMPTRIG_Pos (15U) +#define ADC_CFGR2_SMPTRIG_Pos (15UL) #define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ #define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC sampling time control trigger mode */ -#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Pos (16UL) #define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ #define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ @@ -2790,11 +2821,11 @@ typedef struct #define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ #define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ -#define ADC_CFGR2_LFTRIG_Pos (27U) +#define ADC_CFGR2_LFTRIG_Pos (27UL) #define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ #define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low-frequency trigge */ -#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Pos (28UL) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ #define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC left shift factor */ #define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ @@ -2803,70 +2834,70 @@ typedef struct #define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_SMPR1 register *****************/ -#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Pos (0UL) #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ -#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Pos (3UL) #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ -#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Pos (6UL) #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ -#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Pos (9UL) #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ -#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Pos (12UL) #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ -#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Pos (15UL) #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ -#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Pos (18UL) #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ -#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Pos (21UL) #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ -#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Pos (24UL) #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ -#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Pos (27UL) #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ @@ -2874,70 +2905,70 @@ typedef struct #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ /******************** Bit definition for ADC_SMPR2 register *****************/ -#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Pos (0UL) #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ -#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Pos (3UL) #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ -#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Pos (6UL) #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ -#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Pos (9UL) #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ -#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Pos (12UL) #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ -#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Pos (15UL) #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ -#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Pos (18UL) #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ -#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Pos (21UL) #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ -#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Pos (24UL) #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ -#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Pos (27UL) #define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ #define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ #define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ @@ -2945,7 +2976,7 @@ typedef struct #define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ /******************** Bit definition for ADC_PCSEL register *****************/ -#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Pos (0UL) #define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ #define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC channel preselection */ #define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ @@ -2969,7 +3000,7 @@ typedef struct #define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_SQR1 register ******************/ -#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Pos (0UL) #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ @@ -2977,7 +3008,7 @@ typedef struct #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ -#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Pos (6UL) #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ @@ -2986,7 +3017,7 @@ typedef struct #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ -#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Pos (12UL) #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ @@ -2995,7 +3026,7 @@ typedef struct #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ -#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Pos (18UL) #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ @@ -3004,7 +3035,7 @@ typedef struct #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ #define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ -#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Pos (24UL) #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ @@ -3014,7 +3045,7 @@ typedef struct #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ******************/ -#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Pos (0UL) #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ @@ -3023,7 +3054,7 @@ typedef struct #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ -#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Pos (6UL) #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ @@ -3032,7 +3063,7 @@ typedef struct #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ -#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Pos (12UL) #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ @@ -3041,7 +3072,7 @@ typedef struct #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ -#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Pos (18UL) #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ @@ -3050,7 +3081,7 @@ typedef struct #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ -#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Pos (24UL) #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ @@ -3060,7 +3091,7 @@ typedef struct #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ******************/ -#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Pos (0UL) #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ @@ -3069,7 +3100,7 @@ typedef struct #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ -#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Pos (6UL) #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ @@ -3078,7 +3109,7 @@ typedef struct #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ -#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Pos (12UL) #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ @@ -3087,7 +3118,7 @@ typedef struct #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ -#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Pos (18UL) #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ @@ -3096,7 +3127,7 @@ typedef struct #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ -#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Pos (24UL) #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ @@ -3106,7 +3137,7 @@ typedef struct #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ******************/ -#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Pos (0UL) #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ @@ -3115,7 +3146,7 @@ typedef struct #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ -#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Pos (6UL) #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ @@ -3125,7 +3156,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Pos (0UL) #define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ #define ADC_DR_RDATA_0 (0x00000001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ @@ -3162,13 +3193,13 @@ typedef struct #define ADC_DR_RDATA_31 (0x80000000UL << ADC_DR_RDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JSQR register ******************/ -#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Pos (0UL) #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ -#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Pos (2UL) #define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ #define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ @@ -3177,13 +3208,13 @@ typedef struct #define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ -#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Pos (7UL) #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ -#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Pos (9UL) #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ @@ -3192,7 +3223,7 @@ typedef struct #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ -#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Pos (15UL) #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ @@ -3201,7 +3232,7 @@ typedef struct #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ -#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Pos (21UL) #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ @@ -3210,7 +3241,7 @@ typedef struct #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ -#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Pos (27UL) #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ @@ -3220,19 +3251,19 @@ typedef struct #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFCFGR1 register ***************/ -#define ADC_OFCFGR1_POSOFF_Pos (24U) +#define ADC_OFCFGR1_POSOFF_Pos (24UL) #define ADC_OFCFGR1_POSOFF_Msk (0x01UL << ADC_OFCFGR1_POSOFF_Pos) /*!< 0x01000000 */ #define ADC_OFCFGR1_POSOFF ADC_OFCFGR1_POSOFF_Msk /*!< ADC offset instance 1 positive offset enable */ -#define ADC_OFCFGR1_USAT_Pos (25U) +#define ADC_OFCFGR1_USAT_Pos (25UL) #define ADC_OFCFGR1_USAT_Msk (0x01UL << ADC_OFCFGR1_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFCFGR1_USAT ADC_OFCFGR1_USAT_Msk /*!< ADC offset instance 1 unsigned saturation value */ -#define ADC_OFCFGR1_SSAT_Pos (26U) +#define ADC_OFCFGR1_SSAT_Pos (26UL) #define ADC_OFCFGR1_SSAT_Msk (0x01UL << ADC_OFCFGR1_SSAT_Pos) /*!< 0x04000000 */ #define ADC_OFCFGR1_SSAT ADC_OFCFGR1_SSAT_Msk /*!< ADC offset instance 1 signed satuaration enable */ -#define ADC_OFCFGR1_OFFSET_CH_Pos (27U) +#define ADC_OFCFGR1_OFFSET_CH_Pos (27UL) #define ADC_OFCFGR1_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0xF8000000 */ #define ADC_OFCFGR1_OFFSET_CH ADC_OFCFGR1_OFFSET_CH_Msk /*!< ADC offset instance 1 channel selection */ #define ADC_OFCFGR1_OFFSET_CH_0 (0x01UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x08000000 */ @@ -3242,19 +3273,19 @@ typedef struct #define ADC_OFCFGR1_OFFSET_CH_4 (0x05UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFCFGR2 register ***************/ -#define ADC_OFCFGR2_POSOFF_Pos (24U) +#define ADC_OFCFGR2_POSOFF_Pos (24UL) #define ADC_OFCFGR2_POSOFF_Msk (0x01UL << ADC_OFCFGR2_POSOFF_Pos) /*!< 0x01000000 */ #define ADC_OFCFGR2_POSOFF ADC_OFCFGR2_POSOFF_Msk /*!< ADC offset instance 2 positive offset enable */ -#define ADC_OFCFGR2_USAT_Pos (25U) +#define ADC_OFCFGR2_USAT_Pos (25UL) #define ADC_OFCFGR2_USAT_Msk (0x01UL << ADC_OFCFGR2_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFCFGR2_USAT ADC_OFCFGR2_USAT_Msk /*!< ADC offset instance 2 unsigned saturation value */ -#define ADC_OFCFGR2_SSAT_Pos (26U) +#define ADC_OFCFGR2_SSAT_Pos (26UL) #define ADC_OFCFGR2_SSAT_Msk (0x01UL << ADC_OFCFGR2_SSAT_Pos) /*!< 0x04000000 */ #define ADC_OFCFGR2_SSAT ADC_OFCFGR2_SSAT_Msk /*!< ADC offset instance 2 signed satuaration enable */ -#define ADC_OFCFGR2_OFFSET_CH_Pos (27U) +#define ADC_OFCFGR2_OFFSET_CH_Pos (27UL) #define ADC_OFCFGR2_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0xF8000000 */ #define ADC_OFCFGR2_OFFSET_CH ADC_OFCFGR2_OFFSET_CH_Msk /*!< ADC offset instance 2 channel selection */ #define ADC_OFCFGR2_OFFSET_CH_0 (0x01UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x08000000 */ @@ -3264,19 +3295,19 @@ typedef struct #define ADC_OFCFGR2_OFFSET_CH_4 (0x05UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFCFGR3 register ***************/ -#define ADC_OFCFGR3_POSOFF_Pos (24U) +#define ADC_OFCFGR3_POSOFF_Pos (24UL) #define ADC_OFCFGR3_POSOFF_Msk (0x01UL << ADC_OFCFGR3_POSOFF_Pos) /*!< 0x01000000 */ #define ADC_OFCFGR3_POSOFF ADC_OFCFGR3_POSOFF_Msk /*!< ADC offset instance 3 positive offset enable */ -#define ADC_OFCFGR3_USAT_Pos (25U) +#define ADC_OFCFGR3_USAT_Pos (25UL) #define ADC_OFCFGR3_USAT_Msk (0x01UL << ADC_OFCFGR3_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFCFGR3_USAT ADC_OFCFGR3_USAT_Msk /*!< ADC offset instance 3 unsigned saturation value */ -#define ADC_OFCFGR3_SSAT_Pos (26U) +#define ADC_OFCFGR3_SSAT_Pos (26UL) #define ADC_OFCFGR3_SSAT_Msk (0x01UL << ADC_OFCFGR3_SSAT_Pos) /*!< 0x04000000 */ #define ADC_OFCFGR3_SSAT ADC_OFCFGR3_SSAT_Msk /*!< ADC offset instance 3 signed satuaration enable */ -#define ADC_OFCFGR3_OFFSET_CH_Pos (27U) +#define ADC_OFCFGR3_OFFSET_CH_Pos (27UL) #define ADC_OFCFGR3_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0xF8000000 */ #define ADC_OFCFGR3_OFFSET_CH ADC_OFCFGR3_OFFSET_CH_Msk /*!< ADC offset instance 3 channel selection for the data offset */ #define ADC_OFCFGR3_OFFSET_CH_0 (0x01UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x08000000 */ @@ -3286,19 +3317,19 @@ typedef struct #define ADC_OFCFGR3_OFFSET_CH_4 (0x05UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFCFGR4 register ***************/ -#define ADC_OFCFGR4_POSOFF_Pos (24U) +#define ADC_OFCFGR4_POSOFF_Pos (24UL) #define ADC_OFCFGR4_POSOFF_Msk (0x01UL << ADC_OFCFGR4_POSOFF_Pos) /*!< 0x01000000 */ #define ADC_OFCFGR4_POSOFF ADC_OFCFGR4_POSOFF_Msk /*!< ADC offset instance 4 positive offset enable */ -#define ADC_OFCFGR4_USAT_Pos (25U) +#define ADC_OFCFGR4_USAT_Pos (25UL) #define ADC_OFCFGR4_USAT_Msk (0x01UL << ADC_OFCFGR4_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFCFGR4_USAT ADC_OFCFGR4_USAT_Msk /*!< ADC offset instance 4 unsigned saturation value */ -#define ADC_OFCFGR4_SSAT_Pos (26U) +#define ADC_OFCFGR4_SSAT_Pos (26UL) #define ADC_OFCFGR4_SSAT_Msk (0x01UL << ADC_OFCFGR4_SSAT_Pos) /*!< 0x04000000 */ #define ADC_OFCFGR4_SSAT ADC_OFCFGR4_SSAT_Msk /*!< ADC offset instance 4 signed satuaration enable */ -#define ADC_OFCFGR4_OFFSET_CH_Pos (27U) +#define ADC_OFCFGR4_OFFSET_CH_Pos (27UL) #define ADC_OFCFGR4_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0xF8000000 */ #define ADC_OFCFGR4_OFFSET_CH ADC_OFCFGR4_OFFSET_CH_Msk /*!< ADC offset instance 4 channel selection for the data offset */ #define ADC_OFCFGR4_OFFSET_CH_0 (0x01UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x08000000 */ @@ -3308,7 +3339,7 @@ typedef struct #define ADC_OFCFGR4_OFFSET_CH_4 (0x05UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFR1 register ******************/ -#define ADC_OFR1_OFFSET_Pos (0U) +#define ADC_OFR1_OFFSET_Pos (0UL) #define ADC_OFR1_OFFSET_Msk (0x03FFFFFUL << ADC_OFR1_OFFSET_Pos) /*!< 0x003FFFFF */ #define ADC_OFR1_OFFSET ADC_OFR1_OFFSET_Msk /*!< ADC offset instance 1 offset level */ #define ADC_OFR1_OFFSET_0 (0x0000001UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000001 */ @@ -3335,7 +3366,7 @@ typedef struct #define ADC_OFR1_OFFSET_21 (0x0200000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00200000 */ /******************** Bit definition for ADC_OFR2 register ******************/ -#define ADC_OFR2_OFFSET_Pos (0U) +#define ADC_OFR2_OFFSET_Pos (0UL) #define ADC_OFR2_OFFSET_Msk (0x03FFFFFUL << ADC_OFR2_OFFSET_Pos) /*!< 0x003FFFFF */ #define ADC_OFR2_OFFSET ADC_OFR2_OFFSET_Msk /*!< ADC offset instance 2 offset level */ #define ADC_OFR2_OFFSET_0 (0x0000001UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000001 */ @@ -3362,7 +3393,7 @@ typedef struct #define ADC_OFR2_OFFSET_21 (0x0200000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00200000 */ /******************** Bit definition for ADC_OFR3 register ******************/ -#define ADC_OFR3_OFFSET_Pos (0U) +#define ADC_OFR3_OFFSET_Pos (0UL) #define ADC_OFR3_OFFSET_Msk (0x03FFFFFUL << ADC_OFR3_OFFSET_Pos) /*!< 0x003FFFFF */ #define ADC_OFR3_OFFSET ADC_OFR3_OFFSET_Msk /*!< ADC offset instance 3 offset level */ #define ADC_OFR3_OFFSET_0 (0x0000001UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000001 */ @@ -3389,7 +3420,7 @@ typedef struct #define ADC_OFR3_OFFSET_21 (0x0200000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00200000 */ /******************** Bit definition for ADC_OFR4 register ******************/ -#define ADC_OFR4_OFFSET_Pos (0U) +#define ADC_OFR4_OFFSET_Pos (0UL) #define ADC_OFR4_OFFSET_Msk (0x03FFFFFUL << ADC_OFR4_OFFSET_Pos) /*!< 0x003FFFFF */ #define ADC_OFR4_OFFSET ADC_OFR4_OFFSET_Msk /*!< ADC offset instance 4 offset level */ #define ADC_OFR4_OFFSET_0 (0x0000001UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000001 */ @@ -3416,7 +3447,7 @@ typedef struct #define ADC_OFR4_OFFSET_21 (0x0200000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00200000 */ /******************** Bit definition for ADC_GCOMP register *****************/ -#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) #define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ #define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< Gain compensation coefficient */ #define ADC_GCOMP_GCOMPCOEFF_0 (0x0001UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000001 */ @@ -3434,12 +3465,12 @@ typedef struct #define ADC_GCOMP_GCOMPCOEFF_12 (0x1000UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00001000 */ #define ADC_GCOMP_GCOMPCOEFF_13 (0x2000UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00002000 */ -#define ADC_GCOMP_GCOMP_Pos (31U) +#define ADC_GCOMP_GCOMP_Pos (31UL) #define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x80000000 */ #define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< Gain compensation mode */ /******************** Bit definition for ADC_JDR1 register ******************/ -#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Pos (0UL) #define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ #define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ @@ -3476,7 +3507,7 @@ typedef struct #define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JDR2 register ********************/ -#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Pos (0UL) #define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ #define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ @@ -3513,7 +3544,7 @@ typedef struct #define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JDR3 register ********************/ -#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Pos (0UL) #define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ #define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ @@ -3550,7 +3581,7 @@ typedef struct #define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JDR4 register ********************/ -#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Pos (0UL) #define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ #define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ @@ -3587,7 +3618,7 @@ typedef struct #define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_AWD2CR register ****************/ -#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Pos (0UL) #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ @@ -3611,7 +3642,7 @@ typedef struct #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ -#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Pos (0UL) #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ @@ -3635,7 +3666,7 @@ typedef struct #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_AWD1TR_LT register *************/ -#define ADC_AWD1LTR_LTR_Pos (0U) +#define ADC_AWD1LTR_LTR_Pos (0UL) #define ADC_AWD1LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD1LTR_LTR_Pos) /*!< 0x007FFFFF */ #define ADC_AWD1LTR_LTR ADC_AWD1LTR_LTR_Msk /*!< ADC analog watchdog 1 threshold low */ #define ADC_AWD1LTR_LTR_0 (0x000001UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000001 */ @@ -3663,7 +3694,7 @@ typedef struct #define ADC_AWD1LTR_LTR_22 (0x400000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00400000 */ /******************** Bit definition for ADC_AWD1TR_HT register *******************/ -#define ADC_AWD1HTR_HTR_Pos (0U) +#define ADC_AWD1HTR_HTR_Pos (0UL) #define ADC_AWD1HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD1HTR_HTR_Pos) /*!< 0x007FFFFF */ #define ADC_AWD1HTR_HTR ADC_AWD1HTR_HTR_Msk /*!< ADC analog watchdog 1 threshold high */ #define ADC_AWD1HTR_HTR_0 (0x000001UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000001 */ @@ -3690,7 +3721,7 @@ typedef struct #define ADC_AWD1HTR_HTR_21 (0x200000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00200000 */ #define ADC_AWD1HTR_HTR_22 (0x400000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00400000 */ -#define ADC_AWD1HTR_AWDFILT_Pos (29U) +#define ADC_AWD1HTR_AWDFILT_Pos (29UL) #define ADC_AWD1HTR_AWDFILT_Msk (0x7UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000007 */ #define ADC_AWD1HTR_AWDFILT ADC_AWD1HTR_AWDFILT_Msk /*!< ADC analog watchdog 1 filtering */ #define ADC_AWD1HTR_AWDFILT_0 (0x000001UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000001 */ @@ -3698,7 +3729,7 @@ typedef struct #define ADC_AWD1HTR_AWDFILT_2 (0x000004UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000004 */ /******************** Bit definition for ADC_AWD2TR_LT register *******************/ -#define ADC_AWD2LTR_LTR_Pos (0U) +#define ADC_AWD2LTR_LTR_Pos (0UL) #define ADC_AWD2LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD2LTR_LTR_Pos) /*!< 0x007FFFFF */ #define ADC_AWD2LTR_LTR ADC_AWD2LTR_LTR_Msk /*!< ADC analog watchdog 2 threshold low */ #define ADC_AWD2LTR_LTR_0 (0x000001UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000001 */ @@ -3726,7 +3757,7 @@ typedef struct #define ADC_AWD2LTR_LTR_22 (0x400000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00400000 */ /******************** Bit definition for ADC_AWD2TR_HT register *******************/ -#define ADC_AWD2HTR_HTR_Pos (0U) +#define ADC_AWD2HTR_HTR_Pos (0UL) #define ADC_AWD2HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD2HTR_HTR_Pos) /*!< 0x007FFFFF */ #define ADC_AWD2HTR_HTR ADC_AWD2HTR_HTR_Msk /*!< ADC analog watchdog 2 threshold high */ #define ADC_AWD2HTR_HTR_0 (0x000001UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000001 */ @@ -3754,7 +3785,7 @@ typedef struct #define ADC_AWD2HTR_HTR_22 (0x400000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00400000 */ /******************** Bit definition for ADC_AWD3TR_LT register *******************/ -#define ADC_AWD3LTR_LTR_Pos (0U) +#define ADC_AWD3LTR_LTR_Pos (0UL) #define ADC_AWD3LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD3LTR_LTR_Pos) /*!< 0x007FFFFF */ #define ADC_AWD3LTR_LTR ADC_AWD3LTR_LTR_Msk /*!< ADC analog watchdog 3 threshold low */ #define ADC_AWD3LTR_LTR_0 (0x000001UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000001 */ @@ -3782,7 +3813,7 @@ typedef struct #define ADC_AWD3LTR_LTR_22 (0x400000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00400000 */ /******************** Bit definition for ADC_AWD3TR_HT register *******************/ -#define ADC_AWD3HTR_HTR_Pos (0U) +#define ADC_AWD3HTR_HTR_Pos (0UL) #define ADC_AWD3HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD3HTR_HTR_Pos) /*!< 0x007FFFFF */ #define ADC_AWD3HTR_HTR ADC_AWD3HTR_HTR_Msk /*!< ADC analog watchdog 3 threshold high */ #define ADC_AWD3HTR_HTR_0 (0x000001UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000001 */ @@ -3809,34 +3840,9 @@ typedef struct #define ADC_AWD3HTR_HTR_21 (0x200000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00200000 */ #define ADC_AWD3HTR_HTR_22 (0x400000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00400000 */ -/******************** Bit definition for ADC_DIFSEL register ****************/ -#define ADC_DIFSEL_DIFSEL_Pos (0U) -#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ -#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode selection */ -#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ -#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ -#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ -#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ -#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ -#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ -#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ -#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ -#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ -#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ -#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ -#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ -#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ -#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ -#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ -#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ -#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ -#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ -#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ -#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ - /******************** Bit definition for ADC_CALFACT register ***************/ -#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Pos (0UL) #define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ #define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ #define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ @@ -3852,88 +3858,88 @@ typedef struct /******************** Bit definition for ADC_OR option register ***************/ -#define ADC_OR_VDDCOREEN_Pos (0U) +#define ADC_OR_VDDCOREEN_Pos (0UL) #define ADC_OR_VDDCOREEN_Msk (0x1UL << ADC_OR_VDDCOREEN_Pos) /*!< 0x00000004 */ #define ADC_OR_VDDCOREEN ADC_OR_VDDCOREEN_Msk /*!< ADC internal path to VDDCORE */ /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register *******************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Pos (0UL) #define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ -#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Pos (1UL) #define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ -#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Pos (2UL) #define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ -#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Pos (3UL) #define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ -#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Pos (4UL) #define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ -#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Pos (5UL) #define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ -#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Pos (6UL) #define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ -#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Pos (7UL) #define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ -#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Pos (8UL) #define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ -#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Pos (9UL) #define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ -#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Pos (10UL) #define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ -#define ADC_CSR_LDORDY_MST_Pos (12U) +#define ADC_CSR_LDORDY_MST_Pos (12UL) #define ADC_CSR_LDORDY_MST_Msk (0x1UL << ADC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ #define ADC_CSR_LDORDY_MST ADC_CSR_LDORDY_MST_Msk /*!< ADC multimode master internal voltage regulator output ready flag */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Pos (16UL) #define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Pos (17UL) #define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ -#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Pos (18UL) #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ -#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Pos (19UL) #define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ -#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Pos (20UL) #define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ -#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Pos (21UL) #define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ -#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Pos (22UL) #define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ -#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Pos (23UL) #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ -#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Pos (24UL) #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ -#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Pos (25UL) #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Pos (26UL) #define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ -#define ADC_CSR_LDORDY_SLV_Pos (28U) +#define ADC_CSR_LDORDY_SLV_Pos (28UL) #define ADC_CSR_LDORDY_SLV_Msk (0x1UL << ADC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ #define ADC_CSR_LDORDY_SLV ADC_CSR_LDORDY_SLV_Msk /*!< ADC multimode slave internal voltage regulator output ready flag */ /******************** Bit definition for ADC_CCR register *******************/ -#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Pos (0UL) #define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ #define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ @@ -3942,7 +3948,7 @@ typedef struct #define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ #define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ -#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Pos (8UL) #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ @@ -3950,13 +3956,13 @@ typedef struct #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ -#define ADC_CCR_DAMDF_Pos (14U) +#define ADC_CCR_DAMDF_Pos (14UL) #define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ #define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< ADC multimode data format */ #define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ #define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ -#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Pos (18UL) #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler */ #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ @@ -3964,29 +3970,29 @@ typedef struct #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ -#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Pos (22UL) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ -#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Pos (23UL) #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to Temperature sensor voltage enable */ -#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Pos (24UL) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ /******************** Bit definition for ADC_CDR register *******************/ -#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Pos (0UL) #define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ -#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Pos (16UL) #define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ /******************** Bit definition for ADC_CDR2 register ******************/ -#define ADC_CDR2_RDATA_ALT_Pos (0U) +#define ADC_CDR2_RDATA_ALT_Pos (0UL) #define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ #define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< ADC multimode master or slave (alternated) group regular conversion data */ @@ -3996,48 +4002,48 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Pos (0UL) #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Pos (0UL) #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ /******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Pos (0UL) #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ -#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Pos (3UL) #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ -#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Pos (5UL) #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ -#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Pos (7UL) #define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ #define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ #define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ -#define CRC_CR_RTYPE_IN_Pos (9U) +#define CRC_CR_RTYPE_IN_Pos (9UL) #define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ #define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< RTYPE_IN Reverse Type Input bit */ -#define CRC_CR_RTYPE_OUT_Pos (10U) +#define CRC_CR_RTYPE_OUT_Pos (10UL) #define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ #define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< RTYPE_OUT Reverse Type Output bit */ /******************* Bit definition for CRC_INIT register *******************/ -#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Pos (0UL) #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ /******************* Bit definition for CRC_POL register ********************/ -#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Pos (0UL) #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ @@ -4046,93 +4052,93 @@ typedef struct /* CRS Clock Recovery System */ /******************************************************************************/ /******************* Bit definition for CRS_CR register *********************/ -#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Pos (0UL) #define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ -#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Pos (1UL) #define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ -#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Pos (2UL) #define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ -#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Pos (3UL) #define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ -#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Pos (5UL) #define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ -#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Pos (6UL) #define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ -#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Pos (7UL) #define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ -#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Pos (8UL) #define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ -#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Pos (0UL) #define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ -#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Pos (16UL) #define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ -#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Pos (24UL) #define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ #define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ #define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ #define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ -#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Pos (28UL) #define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ #define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ #define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ -#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Pos (31UL) #define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ /******************* Bit definition for CRS_ISR register *********************/ -#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Pos (0UL) #define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ -#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Pos (1UL) #define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ -#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Pos (2UL) #define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ -#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Pos (3UL) #define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ -#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Pos (8UL) #define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ -#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Pos (9UL) #define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ -#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Pos (10UL) #define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ -#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Pos (15UL) #define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ -#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Pos (16UL) #define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ /******************* Bit definition for CRS_ICR register *********************/ -#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Pos (0UL) #define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ -#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Pos (1UL) #define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ -#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Pos (2UL) #define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ -#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Pos (3UL) #define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ @@ -4142,41 +4148,41 @@ typedef struct /* */ /******************************************************************************/ /*!< ****************** Bit definition for COMPx_CSR register ********************/ -#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Pos (0UL) #define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ #define COMP_CSR_EN COMP_CSR_EN_Msk /*!< COMPx enable bit */ -#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Pos (4UL) #define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00070000 */ #define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< COMPx input minus selection bit */ #define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00010000 */ #define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00020000 */ #define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00040000 */ #define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00080000 */ -#define COMP_CSR_INPSEL_Pos (8U) +#define COMP_CSR_INPSEL_Pos (8UL) #define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00100000 */ #define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< COMPx input plus selection bit */ #define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) #define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) -#define COMP_CSR_WINMODE_Pos (11U) +#define COMP_CSR_WINMODE_Pos (11UL) #define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000010 */ #define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< COMPx Windows mode selection bit */ -#define COMP_CSR_WINOUT_Pos (14U) +#define COMP_CSR_WINOUT_Pos (14UL) #define COMP_CSR_WINOUT_Msk (0x1UL << COMP_CSR_WINOUT_Pos) /*!< 0x00000008 */ #define COMP_CSR_WINOUT COMP_CSR_WINOUT_Msk /*!< COMPx polarity selection bit */ -#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Pos (15UL) #define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00000008 */ #define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< COMPx polarity selection bit */ -#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Pos (16UL) #define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00000300 */ #define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< COMPx hysteresis selection bits */ #define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00000100 */ #define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00000200 */ -#define COMP_CSR_PWRMODE_Pos (18U) +#define COMP_CSR_PWRMODE_Pos (18UL) #define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00003000 */ #define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< COMPx Power Mode of the comparator */ #define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00001000 */ #define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00002000 */ -#define COMP_CSR_BLANKSEL_Pos (20U) +#define COMP_CSR_BLANKSEL_Pos (20UL) #define COMP_CSR_BLANKSEL_Msk (0x1FUL << COMP_CSR_BLANKSEL_Pos) /*!< 0x0F000000 */ #define COMP_CSR_BLANKSEL COMP_CSR_BLANKSEL_Msk /*!< COMPx blanking source selection bits */ #define COMP_CSR_BLANKSEL_0 (0x1UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ @@ -4184,10 +4190,12 @@ typedef struct #define COMP_CSR_BLANKSEL_2 (0x4UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x04000000 */ #define COMP_CSR_BLANKSEL_3 (0x8UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x08000000 */ #define COMP_CSR_BLANKSEL_4 (0x10UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ -#define COMP_CSR_VALUE_Pos (30U) +#define COMP2_CSR_BLANKSEL_2 COMP_CSR_BLANKSEL_2 /*!< COMP2 blanking source selection bit 2 */ +#define COMP2_CSR_BLANKSEL_1 COMP_CSR_BLANKSEL_1 /*!< COMP2 blanking source selection bit 2 */ +#define COMP_CSR_VALUE_Pos (30UL) #define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x00000001 */ #define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< COMPx enable bit */ -#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Pos (31UL) #define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ #define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< COMPx Lock Bit */ @@ -4199,277 +4207,277 @@ typedef struct #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ /******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Pos (0UL) #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!(1)) */ -/*!< TRGOEN configuration */ -#define HSP_ITFENR_TRGOEN_Pos (12U) + +#define HSP_ITFENR_TRGOEN_Pos (12UL) #define HSP_ITFENR_TRGOEN_Msk (0x1UL << HSP_ITFENR_TRGOEN_Pos) /*!< 0x00001000 */ #define HSP_ITFENR_TRGOEN HSP_ITFENR_TRGOEN_Msk /*!< TRGOEN (TRGO enable bit (1)) */ -/*!< TRGI0EN configuration */ -#define HSP_ITFENR_TRGI0EN_Pos (16U) + +#define HSP_ITFENR_TRGI0EN_Pos (16UL) #define HSP_ITFENR_TRGI0EN_Msk (0x1UL << HSP_ITFENR_TRGI0EN_Pos) /*!< 0x00010000 */ #define HSP_ITFENR_TRGI0EN HSP_ITFENR_TRGI0EN_Msk /*!< TRGI0EN (TRGIN0 enable bit (1)) */ -/*!< TRGI1EN configuration */ -#define HSP_ITFENR_TRGI1EN_Pos (17U) + +#define HSP_ITFENR_TRGI1EN_Pos (17UL) #define HSP_ITFENR_TRGI1EN_Msk (0x1UL << HSP_ITFENR_TRGI1EN_Pos) /*!< 0x00020000 */ #define HSP_ITFENR_TRGI1EN HSP_ITFENR_TRGI1EN_Msk /*!< TRGI1EN (TRGIN1 enable bit (1)) */ -/*!< TRGI2EN configuration */ -#define HSP_ITFENR_TRGI2EN_Pos (18U) + +#define HSP_ITFENR_TRGI2EN_Pos (18UL) #define HSP_ITFENR_TRGI2EN_Msk (0x1UL << HSP_ITFENR_TRGI2EN_Pos) /*!< 0x00040000 */ #define HSP_ITFENR_TRGI2EN HSP_ITFENR_TRGI2EN_Msk /*!< TRGI2EN (TRGIN2 enable bit (1)) */ -/*!< TRGI3EN configuration */ -#define HSP_ITFENR_TRGI3EN_Pos (19U) + +#define HSP_ITFENR_TRGI3EN_Pos (19UL) #define HSP_ITFENR_TRGI3EN_Msk (0x1UL << HSP_ITFENR_TRGI3EN_Pos) /*!< 0x00080000 */ #define HSP_ITFENR_TRGI3EN HSP_ITFENR_TRGI3EN_Msk /*!< TRGI3EN (TRGIN3 enable bit (1)) */ -/*!< TRGI4EN configuration */ -#define HSP_ITFENR_TRGI4EN_Pos (20U) + +#define HSP_ITFENR_TRGI4EN_Pos (20UL) #define HSP_ITFENR_TRGI4EN_Msk (0x1UL << HSP_ITFENR_TRGI4EN_Pos) /*!< 0x00100000 */ #define HSP_ITFENR_TRGI4EN HSP_ITFENR_TRGI4EN_Msk /*!< TRGI4EN (TRGIN4 enable bit (1)) */ -/*!< TRGI5EN configuration */ -#define HSP_ITFENR_TRGI5EN_Pos (21U) + +#define HSP_ITFENR_TRGI5EN_Pos (21UL) #define HSP_ITFENR_TRGI5EN_Msk (0x1UL << HSP_ITFENR_TRGI5EN_Pos) /*!< 0x00200000 */ #define HSP_ITFENR_TRGI5EN HSP_ITFENR_TRGI5EN_Msk /*!< TRGI5EN (TRGIN5 enable bit (1)) */ -/*!< TRGI6EN configuration */ -#define HSP_ITFENR_TRGI6EN_Pos (22U) + +#define HSP_ITFENR_TRGI6EN_Pos (22UL) #define HSP_ITFENR_TRGI6EN_Msk (0x1UL << HSP_ITFENR_TRGI6EN_Pos) /*!< 0x00400000 */ #define HSP_ITFENR_TRGI6EN HSP_ITFENR_TRGI6EN_Msk /*!< TRGI6EN (TRGIN6 enable bit (1)) */ -/*!< TRGI7EN configuration */ -#define HSP_ITFENR_TRGI7EN_Pos (23U) + +#define HSP_ITFENR_TRGI7EN_Pos (23UL) #define HSP_ITFENR_TRGI7EN_Msk (0x1UL << HSP_ITFENR_TRGI7EN_Pos) /*!< 0x00800000 */ #define HSP_ITFENR_TRGI7EN HSP_ITFENR_TRGI7EN_Msk /*!< TRGI7EN (TRGIN7 enable bit (1)) */ -/*!< TRGI8EN configuration */ -#define HSP_ITFENR_TRGI8EN_Pos (24U) + +#define HSP_ITFENR_TRGI8EN_Pos (24UL) #define HSP_ITFENR_TRGI8EN_Msk (0x1UL << HSP_ITFENR_TRGI8EN_Pos) /*!< 0x01000000 */ #define HSP_ITFENR_TRGI8EN HSP_ITFENR_TRGI8EN_Msk /*!< TRGI8EN (TRGIN8 enable bit (1)) */ -/*!< TRGI9EN configuration */ -#define HSP_ITFENR_TRGI9EN_Pos (25U) + +#define HSP_ITFENR_TRGI9EN_Pos (25UL) #define HSP_ITFENR_TRGI9EN_Msk (0x1UL << HSP_ITFENR_TRGI9EN_Pos) /*!< 0x02000000 */ #define HSP_ITFENR_TRGI9EN HSP_ITFENR_TRGI9EN_Msk /*!< TRGI9EN (TRGIN9 enable bit (1)) */ -/*!< DCMDDIS configuration */ -#define HSP_ITFENR_DCMDDIS_Pos (27U) + +#define HSP_ITFENR_DCMDDIS_Pos (27UL) #define HSP_ITFENR_DCMDDIS_Msk (0x1UL << HSP_ITFENR_DCMDDIS_Pos) /*!< 0x08000000 */ #define HSP_ITFENR_DCMDDIS HSP_ITFENR_DCMDDIS_Msk /*!< DCMDDIS (Direct command interface disable bit ) */ -/*!< CSEGEN configuration */ -#define HSP_ITFENR_CSEGEN_Pos (28U) + +#define HSP_ITFENR_CSEGEN_Pos (28UL) #define HSP_ITFENR_CSEGEN_Msk (0x1UL << HSP_ITFENR_CSEGEN_Pos) /*!< 0x10000000 */ #define HSP_ITFENR_CSEGEN HSP_ITFENR_CSEGEN_Msk /*!< CSEGEN (CSEG interface enable bit (1)) */ -/*!< CDEGEN configuration */ -#define HSP_ITFENR_CDEGEN_Pos (29U) + +#define HSP_ITFENR_CDEGEN_Pos (29UL) #define HSP_ITFENR_CDEGEN_Msk (0x1UL << HSP_ITFENR_CDEGEN_Pos) /*!< 0x20000000 */ #define HSP_ITFENR_CDEGEN HSP_ITFENR_CDEGEN_Msk /*!< CDEGEN (CDEG interface enable bit ) */ -/*!< HSEGEN configuration */ -#define HSP_ITFENR_HSEGEN_Pos (30U) + +#define HSP_ITFENR_HSEGEN_Pos (30UL) #define HSP_ITFENR_HSEGEN_Msk (0x1UL << HSP_ITFENR_HSEGEN_Pos) /*!< 0x40000000 */ #define HSP_ITFENR_HSEGEN HSP_ITFENR_HSEGEN_Msk /*!< HSEGEN (HSEG interface enable bit ) */ -/*!< HDEGEN configuration */ -#define HSP_ITFENR_HDEGEN_Pos (31U) + +#define HSP_ITFENR_HDEGEN_Pos (31UL) #define HSP_ITFENR_HDEGEN_Msk (0x1UL << HSP_ITFENR_HDEGEN_Pos) /*!< 0x80000000 */ #define HSP_ITFENR_HDEGEN HSP_ITFENR_HDEGEN_Msk /*!< HDEGEN (HDEG interface enable bit ) */ /******************** Bit definition for HSP_EVTSRC0R register ********************/ -/*!< EVT1SRC configuration */ -#define HSP_EVTSRC0R_EVT1SRC_Pos (0U) +#define HSP_EVTSRC0R_EVT1SRC_Pos (0UL) #define HSP_EVTSRC0R_EVT1SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT1SRC_Pos) /*!< 0x00000007 */ #define HSP_EVTSRC0R_EVT1SRC HSP_EVTSRC0R_EVT1SRC_Msk /*!< EVT1SRC[2:0] bits (Event source selection for priority encoder input 1) */ #define HSP_EVTSRC0R_EVT1SRC_0 (0x1UL << HSP_EVTSRC0R_EVT1SRC_Pos) /*!< 0x00000001 */ #define HSP_EVTSRC0R_EVT1SRC_1 (0x2UL << HSP_EVTSRC0R_EVT1SRC_Pos) /*!< 0x00000002 */ #define HSP_EVTSRC0R_EVT1SRC_2 (0x4UL << HSP_EVTSRC0R_EVT1SRC_Pos) /*!< 0x00000004 */ -/*!< EVT2SRC configuration */ -#define HSP_EVTSRC0R_EVT2SRC_Pos (4U) + +#define HSP_EVTSRC0R_EVT2SRC_Pos (4UL) #define HSP_EVTSRC0R_EVT2SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT2SRC_Pos) /*!< 0x00000070 */ #define HSP_EVTSRC0R_EVT2SRC HSP_EVTSRC0R_EVT2SRC_Msk /*!< EVT2SRC[2:0] bits (Event source selection for priority encoder input 2) */ #define HSP_EVTSRC0R_EVT2SRC_0 (0x1UL << HSP_EVTSRC0R_EVT2SRC_Pos) /*!< 0x00000010 */ #define HSP_EVTSRC0R_EVT2SRC_1 (0x2UL << HSP_EVTSRC0R_EVT2SRC_Pos) /*!< 0x00000020 */ #define HSP_EVTSRC0R_EVT2SRC_2 (0x4UL << HSP_EVTSRC0R_EVT2SRC_Pos) /*!< 0x00000040 */ -/*!< EVT3SRC configuration */ -#define HSP_EVTSRC0R_EVT3SRC_Pos (8U) + +#define HSP_EVTSRC0R_EVT3SRC_Pos (8UL) #define HSP_EVTSRC0R_EVT3SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT3SRC_Pos) /*!< 0x00000700 */ #define HSP_EVTSRC0R_EVT3SRC HSP_EVTSRC0R_EVT3SRC_Msk /*!< EVT3SRC[2:0] bits (Event source selection for priority encoder input 3) */ #define HSP_EVTSRC0R_EVT3SRC_0 (0x1UL << HSP_EVTSRC0R_EVT3SRC_Pos) /*!< 0x00000100 */ #define HSP_EVTSRC0R_EVT3SRC_1 (0x2UL << HSP_EVTSRC0R_EVT3SRC_Pos) /*!< 0x00000200 */ #define HSP_EVTSRC0R_EVT3SRC_2 (0x4UL << HSP_EVTSRC0R_EVT3SRC_Pos) /*!< 0x00000400 */ -/*!< EVT4SRC configuration */ -#define HSP_EVTSRC0R_EVT4SRC_Pos (12U) + +#define HSP_EVTSRC0R_EVT4SRC_Pos (12UL) #define HSP_EVTSRC0R_EVT4SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT4SRC_Pos) /*!< 0x00007000 */ #define HSP_EVTSRC0R_EVT4SRC HSP_EVTSRC0R_EVT4SRC_Msk /*!< EVT4SRC[2:0] bits (Event source selection for priority encoder input 4) */ #define HSP_EVTSRC0R_EVT4SRC_0 (0x1UL << HSP_EVTSRC0R_EVT4SRC_Pos) /*!< 0x00001000 */ #define HSP_EVTSRC0R_EVT4SRC_1 (0x2UL << HSP_EVTSRC0R_EVT4SRC_Pos) /*!< 0x00002000 */ #define HSP_EVTSRC0R_EVT4SRC_2 (0x4UL << HSP_EVTSRC0R_EVT4SRC_Pos) /*!< 0x00004000 */ -/*!< EVT5SRC configuration */ -#define HSP_EVTSRC0R_EVT5SRC_Pos (16U) + +#define HSP_EVTSRC0R_EVT5SRC_Pos (16UL) #define HSP_EVTSRC0R_EVT5SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT5SRC_Pos) /*!< 0x00070000 */ #define HSP_EVTSRC0R_EVT5SRC HSP_EVTSRC0R_EVT5SRC_Msk /*!< EVT5SRC[2:0] bits (Event source selection for priority encoder input 5) */ #define HSP_EVTSRC0R_EVT5SRC_0 (0x1UL << HSP_EVTSRC0R_EVT5SRC_Pos) /*!< 0x00010000 */ #define HSP_EVTSRC0R_EVT5SRC_1 (0x2UL << HSP_EVTSRC0R_EVT5SRC_Pos) /*!< 0x00020000 */ #define HSP_EVTSRC0R_EVT5SRC_2 (0x4UL << HSP_EVTSRC0R_EVT5SRC_Pos) /*!< 0x00040000 */ -/*!< EVT6SRC configuration */ -#define HSP_EVTSRC0R_EVT6SRC_Pos (20U) + +#define HSP_EVTSRC0R_EVT6SRC_Pos (20UL) #define HSP_EVTSRC0R_EVT6SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT6SRC_Pos) /*!< 0x00700000 */ #define HSP_EVTSRC0R_EVT6SRC HSP_EVTSRC0R_EVT6SRC_Msk /*!< EVT6SRC[2:0] bits (Event source selection for priority encoder input 6) */ #define HSP_EVTSRC0R_EVT6SRC_0 (0x1UL << HSP_EVTSRC0R_EVT6SRC_Pos) /*!< 0x00100000 */ #define HSP_EVTSRC0R_EVT6SRC_1 (0x2UL << HSP_EVTSRC0R_EVT6SRC_Pos) /*!< 0x00200000 */ #define HSP_EVTSRC0R_EVT6SRC_2 (0x4UL << HSP_EVTSRC0R_EVT6SRC_Pos) /*!< 0x00400000 */ -/*!< EVT7SRC configuration */ -#define HSP_EVTSRC0R_EVT7SRC_Pos (24U) + +#define HSP_EVTSRC0R_EVT7SRC_Pos (24UL) #define HSP_EVTSRC0R_EVT7SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT7SRC_Pos) /*!< 0x07000000 */ #define HSP_EVTSRC0R_EVT7SRC HSP_EVTSRC0R_EVT7SRC_Msk /*!< EVT7SRC[2:0] bits (Event source selection for priority encoder input 7) */ #define HSP_EVTSRC0R_EVT7SRC_0 (0x1UL << HSP_EVTSRC0R_EVT7SRC_Pos) /*!< 0x01000000 */ #define HSP_EVTSRC0R_EVT7SRC_1 (0x2UL << HSP_EVTSRC0R_EVT7SRC_Pos) /*!< 0x02000000 */ #define HSP_EVTSRC0R_EVT7SRC_2 (0x4UL << HSP_EVTSRC0R_EVT7SRC_Pos) /*!< 0x04000000 */ -/*!< EVT8SRC configuration */ -#define HSP_EVTSRC0R_EVT8SRC_Pos (28U) + +#define HSP_EVTSRC0R_EVT8SRC_Pos (28UL) #define HSP_EVTSRC0R_EVT8SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT8SRC_Pos) /*!< 0x70000000 */ #define HSP_EVTSRC0R_EVT8SRC HSP_EVTSRC0R_EVT8SRC_Msk /*!< EVT8SRC[2:0] bits (Event source selection for priority encoder input 8) */ #define HSP_EVTSRC0R_EVT8SRC_0 (0x1UL << HSP_EVTSRC0R_EVT8SRC_Pos) /*!< 0x10000000 */ @@ -11226,57 +12726,56 @@ typedef struct #define HSP_EVTSRC0R_EVT8SRC_2 (0x4UL << HSP_EVTSRC0R_EVT8SRC_Pos) /*!< 0x40000000 */ /******************** Bit definition for HSP_EVTSRC1R register ********************/ -/*!< EVT9SRC configuration */ -#define HSP_EVTSRC1R_EVT9SRC_Pos (0U) +#define HSP_EVTSRC1R_EVT9SRC_Pos (0UL) #define HSP_EVTSRC1R_EVT9SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT9SRC_Pos) /*!< 0x00000007 */ #define HSP_EVTSRC1R_EVT9SRC HSP_EVTSRC1R_EVT9SRC_Msk /*!< EVT9SRC[2:0] bits (Event source selection for priority encoder input 9) */ #define HSP_EVTSRC1R_EVT9SRC_0 (0x1UL << HSP_EVTSRC1R_EVT9SRC_Pos) /*!< 0x00000001 */ #define HSP_EVTSRC1R_EVT9SRC_1 (0x2UL << HSP_EVTSRC1R_EVT9SRC_Pos) /*!< 0x00000002 */ #define HSP_EVTSRC1R_EVT9SRC_2 (0x4UL << HSP_EVTSRC1R_EVT9SRC_Pos) /*!< 0x00000004 */ -/*!< EVT10SRC configuration */ -#define HSP_EVTSRC1R_EVT10SRC_Pos (4U) + +#define HSP_EVTSRC1R_EVT10SRC_Pos (4UL) #define HSP_EVTSRC1R_EVT10SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT10SRC_Pos) /*!< 0x00000070 */ #define HSP_EVTSRC1R_EVT10SRC HSP_EVTSRC1R_EVT10SRC_Msk /*!< EVT10SRC[2:0] bits (Event source selection for priority encoder input 10) */ #define HSP_EVTSRC1R_EVT10SRC_0 (0x1UL << HSP_EVTSRC1R_EVT10SRC_Pos) /*!< 0x00000010 */ #define HSP_EVTSRC1R_EVT10SRC_1 (0x2UL << HSP_EVTSRC1R_EVT10SRC_Pos) /*!< 0x00000020 */ #define HSP_EVTSRC1R_EVT10SRC_2 (0x4UL << HSP_EVTSRC1R_EVT10SRC_Pos) /*!< 0x00000040 */ -/*!< EVT11SRC configuration */ -#define HSP_EVTSRC1R_EVT11SRC_Pos (8U) + +#define HSP_EVTSRC1R_EVT11SRC_Pos (8UL) #define HSP_EVTSRC1R_EVT11SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT11SRC_Pos) /*!< 0x00000700 */ #define HSP_EVTSRC1R_EVT11SRC HSP_EVTSRC1R_EVT11SRC_Msk /*!< EVT11SRC[2:0] bits (Event source selection for priority encoder input 11) */ #define HSP_EVTSRC1R_EVT11SRC_0 (0x1UL << HSP_EVTSRC1R_EVT11SRC_Pos) /*!< 0x00000100 */ #define HSP_EVTSRC1R_EVT11SRC_1 (0x2UL << HSP_EVTSRC1R_EVT11SRC_Pos) /*!< 0x00000200 */ #define HSP_EVTSRC1R_EVT11SRC_2 (0x4UL << HSP_EVTSRC1R_EVT11SRC_Pos) /*!< 0x00000400 */ -/*!< EVT12SRC configuration */ -#define HSP_EVTSRC1R_EVT12SRC_Pos (12U) + +#define HSP_EVTSRC1R_EVT12SRC_Pos (12UL) #define HSP_EVTSRC1R_EVT12SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT12SRC_Pos) /*!< 0x00007000 */ #define HSP_EVTSRC1R_EVT12SRC HSP_EVTSRC1R_EVT12SRC_Msk /*!< EVT12SRC[2:0] bits (Event source selection for priority encoder input 12) */ #define HSP_EVTSRC1R_EVT12SRC_0 (0x1UL << HSP_EVTSRC1R_EVT12SRC_Pos) /*!< 0x00001000 */ #define HSP_EVTSRC1R_EVT12SRC_1 (0x2UL << HSP_EVTSRC1R_EVT12SRC_Pos) /*!< 0x00002000 */ #define HSP_EVTSRC1R_EVT12SRC_2 (0x4UL << HSP_EVTSRC1R_EVT12SRC_Pos) /*!< 0x00004000 */ -/*!< EVT13SRC configuration */ -#define HSP_EVTSRC1R_EVT13SRC_Pos (16U) + +#define HSP_EVTSRC1R_EVT13SRC_Pos (16UL) #define HSP_EVTSRC1R_EVT13SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT13SRC_Pos) /*!< 0x00070000 */ #define HSP_EVTSRC1R_EVT13SRC HSP_EVTSRC1R_EVT13SRC_Msk /*!< EVT13SRC[2:0] bits (Event source selection for priority encoder input 13) */ #define HSP_EVTSRC1R_EVT13SRC_0 (0x1UL << HSP_EVTSRC1R_EVT13SRC_Pos) /*!< 0x00010000 */ #define HSP_EVTSRC1R_EVT13SRC_1 (0x2UL << HSP_EVTSRC1R_EVT13SRC_Pos) /*!< 0x00020000 */ #define HSP_EVTSRC1R_EVT13SRC_2 (0x4UL << HSP_EVTSRC1R_EVT13SRC_Pos) /*!< 0x00040000 */ -/*!< EVT14SRC configuration */ -#define HSP_EVTSRC1R_EVT14SRC_Pos (20U) + +#define HSP_EVTSRC1R_EVT14SRC_Pos (20UL) #define HSP_EVTSRC1R_EVT14SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT14SRC_Pos) /*!< 0x00700000 */ #define HSP_EVTSRC1R_EVT14SRC HSP_EVTSRC1R_EVT14SRC_Msk /*!< EVT14SRC[2:0] bits (Event source selection for priority encoder input 14) */ #define HSP_EVTSRC1R_EVT14SRC_0 (0x1UL << HSP_EVTSRC1R_EVT14SRC_Pos) /*!< 0x00100000 */ #define HSP_EVTSRC1R_EVT14SRC_1 (0x2UL << HSP_EVTSRC1R_EVT14SRC_Pos) /*!< 0x00200000 */ #define HSP_EVTSRC1R_EVT14SRC_2 (0x4UL << HSP_EVTSRC1R_EVT14SRC_Pos) /*!< 0x00400000 */ -/*!< EVT15SRC configuration */ -#define HSP_EVTSRC1R_EVT15SRC_Pos (24U) + +#define HSP_EVTSRC1R_EVT15SRC_Pos (24UL) #define HSP_EVTSRC1R_EVT15SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT15SRC_Pos) /*!< 0x07000000 */ #define HSP_EVTSRC1R_EVT15SRC HSP_EVTSRC1R_EVT15SRC_Msk /*!< EVT15SRC[2:0] bits (Event source selection for priority encoder input 15) */ #define HSP_EVTSRC1R_EVT15SRC_0 (0x1UL << HSP_EVTSRC1R_EVT15SRC_Pos) /*!< 0x01000000 */ #define HSP_EVTSRC1R_EVT15SRC_1 (0x2UL << HSP_EVTSRC1R_EVT15SRC_Pos) /*!< 0x02000000 */ #define HSP_EVTSRC1R_EVT15SRC_2 (0x4UL << HSP_EVTSRC1R_EVT15SRC_Pos) /*!< 0x04000000 */ -/*!< EVT16SRC configuration */ -#define HSP_EVTSRC1R_EVT16SRC_Pos (28U) + +#define HSP_EVTSRC1R_EVT16SRC_Pos (28UL) #define HSP_EVTSRC1R_EVT16SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT16SRC_Pos) /*!< 0x70000000 */ #define HSP_EVTSRC1R_EVT16SRC HSP_EVTSRC1R_EVT16SRC_Msk /*!< EVT16SRC[2:0] bits (Event source selection for priority encoder input 16) */ #define HSP_EVTSRC1R_EVT16SRC_0 (0x1UL << HSP_EVTSRC1R_EVT16SRC_Pos) /*!< 0x10000000 */ @@ -11284,43 +12783,42 @@ typedef struct #define HSP_EVTSRC1R_EVT16SRC_2 (0x4UL << HSP_EVTSRC1R_EVT16SRC_Pos) /*!< 0x40000000 */ /******************** Bit definition for HSP_EVTSRC2R register ********************/ -/*!< EVT17SRC configuration */ -#define HSP_EVTSRC2R_EVT17SRC_Pos (0U) +#define HSP_EVTSRC2R_EVT17SRC_Pos (0UL) #define HSP_EVTSRC2R_EVT17SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT17SRC_Pos) /*!< 0x00000007 */ #define HSP_EVTSRC2R_EVT17SRC HSP_EVTSRC2R_EVT17SRC_Msk /*!< EVT17SRC[2:0] bits (Event source selection for priority encoder input 17) */ #define HSP_EVTSRC2R_EVT17SRC_0 (0x1UL << HSP_EVTSRC2R_EVT17SRC_Pos) /*!< 0x00000001 */ #define HSP_EVTSRC2R_EVT17SRC_1 (0x2UL << HSP_EVTSRC2R_EVT17SRC_Pos) /*!< 0x00000002 */ #define HSP_EVTSRC2R_EVT17SRC_2 (0x4UL << HSP_EVTSRC2R_EVT17SRC_Pos) /*!< 0x00000004 */ -/*!< EVT18SRC configuration */ -#define HSP_EVTSRC2R_EVT18SRC_Pos (4U) + +#define HSP_EVTSRC2R_EVT18SRC_Pos (4UL) #define HSP_EVTSRC2R_EVT18SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT18SRC_Pos) /*!< 0x00000070 */ #define HSP_EVTSRC2R_EVT18SRC HSP_EVTSRC2R_EVT18SRC_Msk /*!< EVT18SRC[2:0] bits (Event source selection for priority encoder input 18) */ #define HSP_EVTSRC2R_EVT18SRC_0 (0x1UL << HSP_EVTSRC2R_EVT18SRC_Pos) /*!< 0x00000010 */ #define HSP_EVTSRC2R_EVT18SRC_1 (0x2UL << HSP_EVTSRC2R_EVT18SRC_Pos) /*!< 0x00000020 */ #define HSP_EVTSRC2R_EVT18SRC_2 (0x4UL << HSP_EVTSRC2R_EVT18SRC_Pos) /*!< 0x00000040 */ -/*!< EVT19SRC configuration */ -#define HSP_EVTSRC2R_EVT19SRC_Pos (8U) + +#define HSP_EVTSRC2R_EVT19SRC_Pos (8UL) #define HSP_EVTSRC2R_EVT19SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT19SRC_Pos) /*!< 0x00000700 */ #define HSP_EVTSRC2R_EVT19SRC HSP_EVTSRC2R_EVT19SRC_Msk /*!< EVT19SRC[2:0] bits (Event source selection for priority encoder input 19) */ #define HSP_EVTSRC2R_EVT19SRC_0 (0x1UL << HSP_EVTSRC2R_EVT19SRC_Pos) /*!< 0x00000100 */ #define HSP_EVTSRC2R_EVT19SRC_1 (0x2UL << HSP_EVTSRC2R_EVT19SRC_Pos) /*!< 0x00000200 */ #define HSP_EVTSRC2R_EVT19SRC_2 (0x4UL << HSP_EVTSRC2R_EVT19SRC_Pos) /*!< 0x00000400 */ -/*!< EVT20SRC configuration */ -#define HSP_EVTSRC2R_EVT20SRC_Pos (12U) + +#define HSP_EVTSRC2R_EVT20SRC_Pos (12UL) #define HSP_EVTSRC2R_EVT20SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT20SRC_Pos) /*!< 0x00007000 */ #define HSP_EVTSRC2R_EVT20SRC HSP_EVTSRC2R_EVT20SRC_Msk /*!< EVT20SRC[2:0] bits (Event source selection for priority encoder input 20) */ #define HSP_EVTSRC2R_EVT20SRC_0 (0x1UL << HSP_EVTSRC2R_EVT20SRC_Pos) /*!< 0x00001000 */ #define HSP_EVTSRC2R_EVT20SRC_1 (0x2UL << HSP_EVTSRC2R_EVT20SRC_Pos) /*!< 0x00002000 */ #define HSP_EVTSRC2R_EVT20SRC_2 (0x4UL << HSP_EVTSRC2R_EVT20SRC_Pos) /*!< 0x00004000 */ -/*!< EVT21SRC configuration */ -#define HSP_EVTSRC2R_EVT21SRC_Pos (16U) + +#define HSP_EVTSRC2R_EVT21SRC_Pos (16UL) #define HSP_EVTSRC2R_EVT21SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT21SRC_Pos) /*!< 0x00070000 */ #define HSP_EVTSRC2R_EVT21SRC HSP_EVTSRC2R_EVT21SRC_Msk /*!< EVT21SRC[2:0] bits (Event source selection for priority encoder input 21) */ #define HSP_EVTSRC2R_EVT21SRC_0 (0x1UL << HSP_EVTSRC2R_EVT21SRC_Pos) /*!< 0x00010000 */ #define HSP_EVTSRC2R_EVT21SRC_1 (0x2UL << HSP_EVTSRC2R_EVT21SRC_Pos) /*!< 0x00020000 */ #define HSP_EVTSRC2R_EVT21SRC_2 (0x4UL << HSP_EVTSRC2R_EVT21SRC_Pos) /*!< 0x00040000 */ -/*!< EVT22SRC configuration */ -#define HSP_EVTSRC2R_EVT22SRC_Pos (20U) + +#define HSP_EVTSRC2R_EVT22SRC_Pos (20UL) #define HSP_EVTSRC2R_EVT22SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT22SRC_Pos) /*!< 0x00700000 */ #define HSP_EVTSRC2R_EVT22SRC HSP_EVTSRC2R_EVT22SRC_Msk /*!< EVT22SRC[2:0] bits (Event source selection for priority encoder input 22) */ #define HSP_EVTSRC2R_EVT22SRC_0 (0x1UL << HSP_EVTSRC2R_EVT22SRC_Pos) /*!< 0x00100000 */ @@ -11328,262 +12826,111 @@ typedef struct #define HSP_EVTSRC2R_EVT22SRC_2 (0x4UL << HSP_EVTSRC2R_EVT22SRC_Pos) /*!< 0x00400000 */ /******************** Bit definition for HSP_BUFFCFGR register ********************/ -/*!< BUFF0DIR configuration */ -#define HSP_BUFFCFGR_BUFF0DIR_Pos (0U) +#define HSP_BUFFCFGR_BUFF0DIR_Pos (0UL) #define HSP_BUFFCFGR_BUFF0DIR_Msk (0x1UL << HSP_BUFFCFGR_BUFF0DIR_Pos) /*!< 0x00000001 */ #define HSP_BUFFCFGR_BUFF0DIR HSP_BUFFCFGR_BUFF0DIR_Msk /*!< BUFF0DIR (Direction selection of BUFF0 (1)) */ -/*!< BUFF1DIR configuration */ -#define HSP_BUFFCFGR_BUFF1DIR_Pos (1U) + +#define HSP_BUFFCFGR_BUFF1DIR_Pos (1UL) #define HSP_BUFFCFGR_BUFF1DIR_Msk (0x1UL << HSP_BUFFCFGR_BUFF1DIR_Pos) /*!< 0x00000002 */ #define HSP_BUFFCFGR_BUFF1DIR HSP_BUFFCFGR_BUFF1DIR_Msk /*!< BUFF1DIR (Direction selection of BUFF1 (1)) */ -/*!< BUFF2DIR configuration */ -#define HSP_BUFFCFGR_BUFF2DIR_Pos (2U) + +#define HSP_BUFFCFGR_BUFF2DIR_Pos (2UL) #define HSP_BUFFCFGR_BUFF2DIR_Msk (0x1UL << HSP_BUFFCFGR_BUFF2DIR_Pos) /*!< 0x00000004 */ #define HSP_BUFFCFGR_BUFF2DIR HSP_BUFFCFGR_BUFF2DIR_Msk /*!< BUFF2DIR (Direction selection of BUFF2 (1)) */ -/*!< BUFF3DIR configuration */ -#define HSP_BUFFCFGR_BUFF3DIR_Pos (3U) + +#define HSP_BUFFCFGR_BUFF3DIR_Pos (3UL) #define HSP_BUFFCFGR_BUFF3DIR_Msk (0x1UL << HSP_BUFFCFGR_BUFF3DIR_Pos) /*!< 0x00000008 */ #define HSP_BUFFCFGR_BUFF3DIR HSP_BUFFCFGR_BUFF3DIR_Msk /*!< BUFF3DIR (Direction selection of BUFF3 (1)) */ -/*!< I2FEN configuration */ -#define HSP_BUFFCFGR_I2FEN_Pos (8U) + +#define HSP_BUFFCFGR_I2FEN_Pos (8UL) #define HSP_BUFFCFGR_I2FEN_Msk (0x1UL << HSP_BUFFCFGR_I2FEN_Pos) /*!< 0x00000100 */ #define HSP_BUFFCFGR_I2FEN HSP_BUFFCFGR_I2FEN_Msk /*!< I2FEN (integer to float32 conversion (1)) */ -/*!< COMB0 configuration */ -#define HSP_BUFFCFGR_COMB0_Pos (16U) + +#define HSP_BUFFCFGR_COMB0_Pos (16UL) #define HSP_BUFFCFGR_COMB0_Msk (0x1UL << HSP_BUFFCFGR_COMB0_Pos) /*!< 0x00010000 */ #define HSP_BUFFCFGR_COMB0 HSP_BUFFCFGR_COMB0_Msk /*!< COMB0 (BUFCMB control for buff_evt[0] (1)) */ -/*!< COMB1 configuration */ -#define HSP_BUFFCFGR_COMB1_Pos (17U) + +#define HSP_BUFFCFGR_COMB1_Pos (17UL) #define HSP_BUFFCFGR_COMB1_Msk (0x1UL << HSP_BUFFCFGR_COMB1_Pos) /*!< 0x00020000 */ #define HSP_BUFFCFGR_COMB1 HSP_BUFFCFGR_COMB1_Msk /*!< COMB1 (BUFCMB control for buff_evt[1] (1)) */ -/*!< COMB2 configuration */ -#define HSP_BUFFCFGR_COMB2_Pos (18U) + +#define HSP_BUFFCFGR_COMB2_Pos (18UL) #define HSP_BUFFCFGR_COMB2_Msk (0x1UL << HSP_BUFFCFGR_COMB2_Pos) /*!< 0x00040000 */ #define HSP_BUFFCFGR_COMB2 HSP_BUFFCFGR_COMB2_Msk /*!< COMB2 (BUFCMB control for buff_evt[2] ) */ -/******************** Bit definition for HSP_BUFF0DR register ********************/ -/*!< BUFFDAT configuration */ -#define HSP_BUFF0DR_BUFFDAT_Pos (0U) -#define HSP_BUFF0DR_BUFFDAT_Msk (0xFFFFFFFFUL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0xFFFFFFFF */ -#define HSP_BUFF0DR_BUFFDAT HSP_BUFF0DR_BUFFDAT_Msk /*!< BUFFDAT[31:0] bits (Data buffer) */ -#define HSP_BUFF0DR_BUFFDAT_0 (0x00001UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00000001 */ -#define HSP_BUFF0DR_BUFFDAT_1 (0x00002UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00000002 */ -#define HSP_BUFF0DR_BUFFDAT_2 (0x00004UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00000004 */ -#define HSP_BUFF0DR_BUFFDAT_3 (0x00008UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00000008 */ -#define HSP_BUFF0DR_BUFFDAT_4 (0x00010UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00000010 */ -#define HSP_BUFF0DR_BUFFDAT_5 (0x00020UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00000020 */ -#define HSP_BUFF0DR_BUFFDAT_6 (0x00040UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00000040 */ -#define HSP_BUFF0DR_BUFFDAT_7 (0x00080UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00000080 */ -#define HSP_BUFF0DR_BUFFDAT_8 (0x00100UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00000100 */ -#define HSP_BUFF0DR_BUFFDAT_9 (0x00200UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00000200 */ -#define HSP_BUFF0DR_BUFFDAT_10 (0x00400UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00000400 */ -#define HSP_BUFF0DR_BUFFDAT_11 (0x00800UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00000800 */ -#define HSP_BUFF0DR_BUFFDAT_12 (0x01000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00001000 */ -#define HSP_BUFF0DR_BUFFDAT_13 (0x02000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00002000 */ -#define HSP_BUFF0DR_BUFFDAT_14 (0x04000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00004000 */ -#define HSP_BUFF0DR_BUFFDAT_15 (0x08000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00008000 */ -#define HSP_BUFF0DR_BUFFDAT_16 (0x10000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00010000 */ -#define HSP_BUFF0DR_BUFFDAT_17 (0x20000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00020000 */ -#define HSP_BUFF0DR_BUFFDAT_18 (0x40000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00040000 */ -#define HSP_BUFF0DR_BUFFDAT_19 (0x80000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00080000 */ -#define HSP_BUFF0DR_BUFFDAT_20 (0x100000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00100000 */ -#define HSP_BUFF0DR_BUFFDAT_21 (0x200000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00200000 */ -#define HSP_BUFF0DR_BUFFDAT_22 (0x400000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00400000 */ -#define HSP_BUFF0DR_BUFFDAT_23 (0x800000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00800000 */ -#define HSP_BUFF0DR_BUFFDAT_24 (0x1000000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x01000000 */ -#define HSP_BUFF0DR_BUFFDAT_25 (0x2000000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x02000000 */ -#define HSP_BUFF0DR_BUFFDAT_26 (0x4000000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x04000000 */ -#define HSP_BUFF0DR_BUFFDAT_27 (0x8000000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x08000000 */ -#define HSP_BUFF0DR_BUFFDAT_28 (0x10000000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x10000000 */ -#define HSP_BUFF0DR_BUFFDAT_29 (0x20000000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x20000000 */ -#define HSP_BUFF0DR_BUFFDAT_30 (0x40000000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x40000000 */ -#define HSP_BUFF0DR_BUFFDAT_31 (0x80000000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for HSP_BUFF1DR register ********************/ -/*!< BUFFDAT configuration */ -#define HSP_BUFF1DR_BUFFDAT_Pos (0U) -#define HSP_BUFF1DR_BUFFDAT_Msk (0xFFFFFFFFUL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0xFFFFFFFF */ -#define HSP_BUFF1DR_BUFFDAT HSP_BUFF1DR_BUFFDAT_Msk /*!< BUFFDAT[31:0] bits (Data buffer) */ -#define HSP_BUFF1DR_BUFFDAT_0 (0x00001UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00000001 */ -#define HSP_BUFF1DR_BUFFDAT_1 (0x00002UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00000002 */ -#define HSP_BUFF1DR_BUFFDAT_2 (0x00004UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00000004 */ -#define HSP_BUFF1DR_BUFFDAT_3 (0x00008UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00000008 */ -#define HSP_BUFF1DR_BUFFDAT_4 (0x00010UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00000010 */ -#define HSP_BUFF1DR_BUFFDAT_5 (0x00020UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00000020 */ -#define HSP_BUFF1DR_BUFFDAT_6 (0x00040UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00000040 */ -#define HSP_BUFF1DR_BUFFDAT_7 (0x00080UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00000080 */ -#define HSP_BUFF1DR_BUFFDAT_8 (0x00100UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00000100 */ -#define HSP_BUFF1DR_BUFFDAT_9 (0x00200UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00000200 */ -#define HSP_BUFF1DR_BUFFDAT_10 (0x00400UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00000400 */ -#define HSP_BUFF1DR_BUFFDAT_11 (0x00800UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00000800 */ -#define HSP_BUFF1DR_BUFFDAT_12 (0x01000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00001000 */ -#define HSP_BUFF1DR_BUFFDAT_13 (0x02000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00002000 */ -#define HSP_BUFF1DR_BUFFDAT_14 (0x04000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00004000 */ -#define HSP_BUFF1DR_BUFFDAT_15 (0x08000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00008000 */ -#define HSP_BUFF1DR_BUFFDAT_16 (0x10000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00010000 */ -#define HSP_BUFF1DR_BUFFDAT_17 (0x20000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00020000 */ -#define HSP_BUFF1DR_BUFFDAT_18 (0x40000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00040000 */ -#define HSP_BUFF1DR_BUFFDAT_19 (0x80000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00080000 */ -#define HSP_BUFF1DR_BUFFDAT_20 (0x100000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00100000 */ -#define HSP_BUFF1DR_BUFFDAT_21 (0x200000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00200000 */ -#define HSP_BUFF1DR_BUFFDAT_22 (0x400000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00400000 */ -#define HSP_BUFF1DR_BUFFDAT_23 (0x800000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00800000 */ -#define HSP_BUFF1DR_BUFFDAT_24 (0x1000000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x01000000 */ -#define HSP_BUFF1DR_BUFFDAT_25 (0x2000000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x02000000 */ -#define HSP_BUFF1DR_BUFFDAT_26 (0x4000000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x04000000 */ -#define HSP_BUFF1DR_BUFFDAT_27 (0x8000000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x08000000 */ -#define HSP_BUFF1DR_BUFFDAT_28 (0x10000000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x10000000 */ -#define HSP_BUFF1DR_BUFFDAT_29 (0x20000000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x20000000 */ -#define HSP_BUFF1DR_BUFFDAT_30 (0x40000000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x40000000 */ -#define HSP_BUFF1DR_BUFFDAT_31 (0x80000000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for HSP_BUFF2DR register ********************/ -/*!< BUFFDAT configuration */ -#define HSP_BUFF2DR_BUFFDAT_Pos (0U) -#define HSP_BUFF2DR_BUFFDAT_Msk (0xFFFFFFFFUL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0xFFFFFFFF */ -#define HSP_BUFF2DR_BUFFDAT HSP_BUFF2DR_BUFFDAT_Msk /*!< BUFFDAT[31:0] bits (Data buffer) */ -#define HSP_BUFF2DR_BUFFDAT_0 (0x00001UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00000001 */ -#define HSP_BUFF2DR_BUFFDAT_1 (0x00002UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00000002 */ -#define HSP_BUFF2DR_BUFFDAT_2 (0x00004UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00000004 */ -#define HSP_BUFF2DR_BUFFDAT_3 (0x00008UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00000008 */ -#define HSP_BUFF2DR_BUFFDAT_4 (0x00010UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00000010 */ -#define HSP_BUFF2DR_BUFFDAT_5 (0x00020UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00000020 */ -#define HSP_BUFF2DR_BUFFDAT_6 (0x00040UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00000040 */ -#define HSP_BUFF2DR_BUFFDAT_7 (0x00080UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00000080 */ -#define HSP_BUFF2DR_BUFFDAT_8 (0x00100UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00000100 */ -#define HSP_BUFF2DR_BUFFDAT_9 (0x00200UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00000200 */ -#define HSP_BUFF2DR_BUFFDAT_10 (0x00400UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00000400 */ -#define HSP_BUFF2DR_BUFFDAT_11 (0x00800UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00000800 */ -#define HSP_BUFF2DR_BUFFDAT_12 (0x01000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00001000 */ -#define HSP_BUFF2DR_BUFFDAT_13 (0x02000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00002000 */ -#define HSP_BUFF2DR_BUFFDAT_14 (0x04000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00004000 */ -#define HSP_BUFF2DR_BUFFDAT_15 (0x08000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00008000 */ -#define HSP_BUFF2DR_BUFFDAT_16 (0x10000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00010000 */ -#define HSP_BUFF2DR_BUFFDAT_17 (0x20000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00020000 */ -#define HSP_BUFF2DR_BUFFDAT_18 (0x40000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00040000 */ -#define HSP_BUFF2DR_BUFFDAT_19 (0x80000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00080000 */ -#define HSP_BUFF2DR_BUFFDAT_20 (0x100000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00100000 */ -#define HSP_BUFF2DR_BUFFDAT_21 (0x200000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00200000 */ -#define HSP_BUFF2DR_BUFFDAT_22 (0x400000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00400000 */ -#define HSP_BUFF2DR_BUFFDAT_23 (0x800000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00800000 */ -#define HSP_BUFF2DR_BUFFDAT_24 (0x1000000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x01000000 */ -#define HSP_BUFF2DR_BUFFDAT_25 (0x2000000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x02000000 */ -#define HSP_BUFF2DR_BUFFDAT_26 (0x4000000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x04000000 */ -#define HSP_BUFF2DR_BUFFDAT_27 (0x8000000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x08000000 */ -#define HSP_BUFF2DR_BUFFDAT_28 (0x10000000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x10000000 */ -#define HSP_BUFF2DR_BUFFDAT_29 (0x20000000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x20000000 */ -#define HSP_BUFF2DR_BUFFDAT_30 (0x40000000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x40000000 */ -#define HSP_BUFF2DR_BUFFDAT_31 (0x80000000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for HSP_BUFF3DR register ********************/ -/*!< BUFFDAT configuration */ -#define HSP_BUFF3DR_BUFFDAT_Pos (0U) -#define HSP_BUFF3DR_BUFFDAT_Msk (0xFFFFFFFFUL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0xFFFFFFFF */ -#define HSP_BUFF3DR_BUFFDAT HSP_BUFF3DR_BUFFDAT_Msk /*!< BUFFDAT[31:0] bits (Data buffer) */ -#define HSP_BUFF3DR_BUFFDAT_0 (0x00001UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00000001 */ -#define HSP_BUFF3DR_BUFFDAT_1 (0x00002UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00000002 */ -#define HSP_BUFF3DR_BUFFDAT_2 (0x00004UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00000004 */ -#define HSP_BUFF3DR_BUFFDAT_3 (0x00008UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00000008 */ -#define HSP_BUFF3DR_BUFFDAT_4 (0x00010UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00000010 */ -#define HSP_BUFF3DR_BUFFDAT_5 (0x00020UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00000020 */ -#define HSP_BUFF3DR_BUFFDAT_6 (0x00040UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00000040 */ -#define HSP_BUFF3DR_BUFFDAT_7 (0x00080UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00000080 */ -#define HSP_BUFF3DR_BUFFDAT_8 (0x00100UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00000100 */ -#define HSP_BUFF3DR_BUFFDAT_9 (0x00200UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00000200 */ -#define HSP_BUFF3DR_BUFFDAT_10 (0x00400UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00000400 */ -#define HSP_BUFF3DR_BUFFDAT_11 (0x00800UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00000800 */ -#define HSP_BUFF3DR_BUFFDAT_12 (0x01000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00001000 */ -#define HSP_BUFF3DR_BUFFDAT_13 (0x02000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00002000 */ -#define HSP_BUFF3DR_BUFFDAT_14 (0x04000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00004000 */ -#define HSP_BUFF3DR_BUFFDAT_15 (0x08000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00008000 */ -#define HSP_BUFF3DR_BUFFDAT_16 (0x10000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00010000 */ -#define HSP_BUFF3DR_BUFFDAT_17 (0x20000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00020000 */ -#define HSP_BUFF3DR_BUFFDAT_18 (0x40000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00040000 */ -#define HSP_BUFF3DR_BUFFDAT_19 (0x80000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00080000 */ -#define HSP_BUFF3DR_BUFFDAT_20 (0x100000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00100000 */ -#define HSP_BUFF3DR_BUFFDAT_21 (0x200000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00200000 */ -#define HSP_BUFF3DR_BUFFDAT_22 (0x400000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00400000 */ -#define HSP_BUFF3DR_BUFFDAT_23 (0x800000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00800000 */ -#define HSP_BUFF3DR_BUFFDAT_24 (0x1000000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x01000000 */ -#define HSP_BUFF3DR_BUFFDAT_25 (0x2000000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x02000000 */ -#define HSP_BUFF3DR_BUFFDAT_26 (0x4000000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x04000000 */ -#define HSP_BUFF3DR_BUFFDAT_27 (0x8000000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x08000000 */ -#define HSP_BUFF3DR_BUFFDAT_28 (0x10000000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x10000000 */ -#define HSP_BUFF3DR_BUFFDAT_29 (0x20000000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x20000000 */ -#define HSP_BUFF3DR_BUFFDAT_30 (0x40000000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x40000000 */ -#define HSP_BUFF3DR_BUFFDAT_31 (0x80000000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x80000000 */ +/******************** Bit definition for HSP_BUFFxDR register ********************/ +#define HSP_BUFFDR_BUFFDAT_Pos (0UL) +#define HSP_BUFFDR_BUFFDAT_Msk (0xFFFFFFFFUL << HSP_BUFFDR_BUFFDAT_Pos) /*!< 0xFFFFFFFF */ +#define HSP_BUFFDR_BUFFDAT HSP_BUFFDR_BUFFDAT_Msk /*!< BUFFDAT[31:0] bits (Data buffer) */ /******************** Bit definition for HSP_TRGINCFGR register ********************/ -/*!< TRG0POL configuration */ -#define HSP_TRGINCFGR_TRG0POL_Pos (0U) +#define HSP_TRGINCFGR_TRG0POL_Pos (0UL) #define HSP_TRGINCFGR_TRG0POL_Msk (0x1UL << HSP_TRGINCFGR_TRG0POL_Pos) /*!< 0x00000001 */ #define HSP_TRGINCFGR_TRG0POL HSP_TRGINCFGR_TRG0POL_Msk /*!< TRG0POL (Polarity selection for TRGIN0) */ -/*!< TRG1POL configuration */ -#define HSP_TRGINCFGR_TRG1POL_Pos (1U) + +#define HSP_TRGINCFGR_TRG1POL_Pos (1UL) #define HSP_TRGINCFGR_TRG1POL_Msk (0x1UL << HSP_TRGINCFGR_TRG1POL_Pos) /*!< 0x00000002 */ #define HSP_TRGINCFGR_TRG1POL HSP_TRGINCFGR_TRG1POL_Msk /*!< TRG1POL (Polarity selection for TRGIN1) */ -/*!< TRG2POL configuration */ -#define HSP_TRGINCFGR_TRG2POL_Pos (2U) + +#define HSP_TRGINCFGR_TRG2POL_Pos (2UL) #define HSP_TRGINCFGR_TRG2POL_Msk (0x1UL << HSP_TRGINCFGR_TRG2POL_Pos) /*!< 0x00000004 */ #define HSP_TRGINCFGR_TRG2POL HSP_TRGINCFGR_TRG2POL_Msk /*!< TRG2POL (Polarity selection for TRGIN2) */ -/*!< TRG3POL configuration */ -#define HSP_TRGINCFGR_TRG3POL_Pos (3U) + +#define HSP_TRGINCFGR_TRG3POL_Pos (3UL) #define HSP_TRGINCFGR_TRG3POL_Msk (0x1UL << HSP_TRGINCFGR_TRG3POL_Pos) /*!< 0x00000008 */ #define HSP_TRGINCFGR_TRG3POL HSP_TRGINCFGR_TRG3POL_Msk /*!< TRG3POL (Polarity selection for TRGIN3) */ -/*!< TRG4POL configuration */ -#define HSP_TRGINCFGR_TRG4POL_Pos (4U) + +#define HSP_TRGINCFGR_TRG4POL_Pos (4UL) #define HSP_TRGINCFGR_TRG4POL_Msk (0x1UL << HSP_TRGINCFGR_TRG4POL_Pos) /*!< 0x00000010 */ #define HSP_TRGINCFGR_TRG4POL HSP_TRGINCFGR_TRG4POL_Msk /*!< TRG4POL (Polarity selection for TRGIN4) */ -/*!< TRG5POL configuration */ -#define HSP_TRGINCFGR_TRG5POL_Pos (5U) + +#define HSP_TRGINCFGR_TRG5POL_Pos (5UL) #define HSP_TRGINCFGR_TRG5POL_Msk (0x1UL << HSP_TRGINCFGR_TRG5POL_Pos) /*!< 0x00000020 */ #define HSP_TRGINCFGR_TRG5POL HSP_TRGINCFGR_TRG5POL_Msk /*!< TRG5POL (Polarity selection for TRGIN5) */ -/*!< TRG6POL configuration */ -#define HSP_TRGINCFGR_TRG6POL_Pos (6U) + +#define HSP_TRGINCFGR_TRG6POL_Pos (6UL) #define HSP_TRGINCFGR_TRG6POL_Msk (0x1UL << HSP_TRGINCFGR_TRG6POL_Pos) /*!< 0x00000040 */ #define HSP_TRGINCFGR_TRG6POL HSP_TRGINCFGR_TRG6POL_Msk /*!< TRG6POL (Polarity selection for TRGIN6) */ -/*!< TRG7POL configuration */ -#define HSP_TRGINCFGR_TRG7POL_Pos (7U) + +#define HSP_TRGINCFGR_TRG7POL_Pos (7UL) #define HSP_TRGINCFGR_TRG7POL_Msk (0x1UL << HSP_TRGINCFGR_TRG7POL_Pos) /*!< 0x00000080 */ #define HSP_TRGINCFGR_TRG7POL HSP_TRGINCFGR_TRG7POL_Msk /*!< TRG7POL (Polarity selection for TRGIN7) */ -/*!< TRG8POL configuration */ -#define HSP_TRGINCFGR_TRG8POL_Pos (8U) + +#define HSP_TRGINCFGR_TRG8POL_Pos (8UL) #define HSP_TRGINCFGR_TRG8POL_Msk (0x1UL << HSP_TRGINCFGR_TRG8POL_Pos) /*!< 0x00000100 */ #define HSP_TRGINCFGR_TRG8POL HSP_TRGINCFGR_TRG8POL_Msk /*!< TRG8POL (Polarity selection for TRGIN8) */ -/*!< TRG9POL configuration */ -#define HSP_TRGINCFGR_TRG9POL_Pos (9U) + +#define HSP_TRGINCFGR_TRG9POL_Pos (9UL) #define HSP_TRGINCFGR_TRG9POL_Msk (0x1UL << HSP_TRGINCFGR_TRG9POL_Pos) /*!< 0x00000200 */ #define HSP_TRGINCFGR_TRG9POL HSP_TRGINCFGR_TRG9POL_Msk /*!< TRG9POL (Polarity selection for TRGIN9) */ /******************** Bit definition for HSP_TRGOCFGR register ********************/ -/*!< TRGO0SRC configuration */ -#define HSP_TRGOCFGR_TRGO0SRC_Pos (0U) +#define HSP_TRGOCFGR_TRGO0SRC_Pos (0UL) #define HSP_TRGOCFGR_TRGO0SRC_Msk (0x3UL << HSP_TRGOCFGR_TRGO0SRC_Pos) /*!< 0x00000003 */ #define HSP_TRGOCFGR_TRGO0SRC HSP_TRGOCFGR_TRGO0SRC_Msk /*!< TRGO0SRC[1:0] bits (Trigger source selection for hsp_trg_out[0] (1)) */ #define HSP_TRGOCFGR_TRGO0SRC_0 (0x1UL << HSP_TRGOCFGR_TRGO0SRC_Pos) /*!< 0x00000001 */ #define HSP_TRGOCFGR_TRGO0SRC_1 (0x2UL << HSP_TRGOCFGR_TRGO0SRC_Pos) /*!< 0x00000002 */ -/*!< TRGO1SRC configuration */ -#define HSP_TRGOCFGR_TRGO1SRC_Pos (2U) + +#define HSP_TRGOCFGR_TRGO1SRC_Pos (2UL) #define HSP_TRGOCFGR_TRGO1SRC_Msk (0x3UL << HSP_TRGOCFGR_TRGO1SRC_Pos) /*!< 0x0000000C */ #define HSP_TRGOCFGR_TRGO1SRC HSP_TRGOCFGR_TRGO1SRC_Msk /*!< TRGO1SRC[1:0] bits (Trigger source selection for hsp_trg_out[1] (1)) */ #define HSP_TRGOCFGR_TRGO1SRC_0 (0x1UL << HSP_TRGOCFGR_TRGO1SRC_Pos) /*!< 0x00000004 */ #define HSP_TRGOCFGR_TRGO1SRC_1 (0x2UL << HSP_TRGOCFGR_TRGO1SRC_Pos) /*!< 0x00000008 */ -/*!< TRGO2SRC configuration */ -#define HSP_TRGOCFGR_TRGO2SRC_Pos (4U) + +#define HSP_TRGOCFGR_TRGO2SRC_Pos (4UL) #define HSP_TRGOCFGR_TRGO2SRC_Msk (0x3UL << HSP_TRGOCFGR_TRGO2SRC_Pos) /*!< 0x00000030 */ #define HSP_TRGOCFGR_TRGO2SRC HSP_TRGOCFGR_TRGO2SRC_Msk /*!< TRGO2SRC[1:0] bits (Trigger source selection for hsp_trg_out[2] (1)) */ #define HSP_TRGOCFGR_TRGO2SRC_0 (0x1UL << HSP_TRGOCFGR_TRGO2SRC_Pos) /*!< 0x00000010 */ #define HSP_TRGOCFGR_TRGO2SRC_1 (0x2UL << HSP_TRGOCFGR_TRGO2SRC_Pos) /*!< 0x00000020 */ -/*!< TRGO3SRC configuration */ -#define HSP_TRGOCFGR_TRGO3SRC_Pos (6U) + +#define HSP_TRGOCFGR_TRGO3SRC_Pos (6UL) #define HSP_TRGOCFGR_TRGO3SRC_Msk (0x3UL << HSP_TRGOCFGR_TRGO3SRC_Pos) /*!< 0x000000C0 */ #define HSP_TRGOCFGR_TRGO3SRC HSP_TRGOCFGR_TRGO3SRC_Msk /*!< TRGO3SRC[1:0] bits (Trigger source selection for hsp_trg_out[3] ) */ #define HSP_TRGOCFGR_TRGO3SRC_0 (0x1UL << HSP_TRGOCFGR_TRGO3SRC_Pos) /*!< 0x00000040 */ #define HSP_TRGOCFGR_TRGO3SRC_1 (0x2UL << HSP_TRGOCFGR_TRGO3SRC_Pos) /*!< 0x00000080 */ /******************** Bit definition for HSP_CSEGR register ********************/ -/*!< CSEVT configuration */ -#define HSP_CSEGR_CSEVT_Pos (1U) +#define HSP_CSEGR_CSEVT_Pos (1UL) #define HSP_CSEGR_CSEVT_Msk (0x3FFFFFUL << HSP_CSEGR_CSEVT_Pos) /*!< 0x007FFFFE */ #define HSP_CSEGR_CSEVT HSP_CSEGR_CSEVT_Msk /*!< CSEVT[21:0] bits (CPU Shared Software Event ) */ #define HSP_CSEGR_CSEVT_0 (0x0001UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000002 */ @@ -11610,24 +12957,16 @@ typedef struct #define HSP_CSEGR_CSEVT_21 (0x200000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00400000 */ /******************** Bit definition for HSP_CDEGR register ********************/ -/*!< CTSKN configuration */ -#define HSP_CDEGR_CTSKN_Pos (0U) +#define HSP_CDEGR_CTSKN_Pos (0UL) #define HSP_CDEGR_CTSKN_Msk (0x3FUL << HSP_CDEGR_CTSKN_Pos) /*!< 0x0000003F */ #define HSP_CDEGR_CTSKN HSP_CDEGR_CTSKN_Msk /*!< CTSKN[5:0] bits (CPU Task number) */ -#define HSP_CDEGR_CTSKN_0 (0x01UL << HSP_CDEGR_CTSKN_Pos) /*!< 0x00000001 */ -#define HSP_CDEGR_CTSKN_1 (0x02UL << HSP_CDEGR_CTSKN_Pos) /*!< 0x00000002 */ -#define HSP_CDEGR_CTSKN_2 (0x04UL << HSP_CDEGR_CTSKN_Pos) /*!< 0x00000004 */ -#define HSP_CDEGR_CTSKN_3 (0x08UL << HSP_CDEGR_CTSKN_Pos) /*!< 0x00000008 */ -#define HSP_CDEGR_CTSKN_4 (0x10UL << HSP_CDEGR_CTSKN_Pos) /*!< 0x00000010 */ -#define HSP_CDEGR_CTSKN_5 (0x20UL << HSP_CDEGR_CTSKN_Pos) /*!< 0x00000020 */ -/*!< CDEGBSY configuration */ -#define HSP_CDEGR_CDEGBSY_Pos (31U) + +#define HSP_CDEGR_CDEGBSY_Pos (31UL) #define HSP_CDEGR_CDEGBSY_Msk (0x1UL << HSP_CDEGR_CDEGBSY_Pos) /*!< 0x80000000 */ #define HSP_CDEGR_CDEGBSY HSP_CDEGR_CDEGBSY_Msk /*!< CDEGBSY (CPU dedicated event generator busy) */ /******************** Bit definition for HSP_TRGINSELR0 register ********************/ -/*!< TRG0SEL configuration */ -#define HSP_TRGINSELR0_TRG0SEL_Pos (0U) +#define HSP_TRGINSELR0_TRG0SEL_Pos (0UL) #define HSP_TRGINSELR0_TRG0SEL_Msk (0x3FUL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x0000003F */ #define HSP_TRGINSELR0_TRG0SEL HSP_TRGINSELR0_TRG0SEL_Msk /*!< TRG0SEL[5:0] bits (Input trigger selection for TRGIN0) */ #define HSP_TRGINSELR0_TRG0SEL_0 (0x01UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000001 */ @@ -11636,8 +12975,8 @@ typedef struct #define HSP_TRGINSELR0_TRG0SEL_3 (0x08UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000008 */ #define HSP_TRGINSELR0_TRG0SEL_4 (0x10UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000010 */ #define HSP_TRGINSELR0_TRG0SEL_5 (0x20UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000020 */ -/*!< TRG1SEL configuration */ -#define HSP_TRGINSELR0_TRG1SEL_Pos (8U) + +#define HSP_TRGINSELR0_TRG1SEL_Pos (8UL) #define HSP_TRGINSELR0_TRG1SEL_Msk (0x3FUL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00003F00 */ #define HSP_TRGINSELR0_TRG1SEL HSP_TRGINSELR0_TRG1SEL_Msk /*!< TRG1SEL[5:0] bits (Input trigger selection for TRGIN1) */ #define HSP_TRGINSELR0_TRG1SEL_0 (0x01UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00000100 */ @@ -11646,8 +12985,8 @@ typedef struct #define HSP_TRGINSELR0_TRG1SEL_3 (0x08UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00000800 */ #define HSP_TRGINSELR0_TRG1SEL_4 (0x10UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00001000 */ #define HSP_TRGINSELR0_TRG1SEL_5 (0x20UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00002000 */ -/*!< TRG2SEL configuration */ -#define HSP_TRGINSELR0_TRG2SEL_Pos (16U) + +#define HSP_TRGINSELR0_TRG2SEL_Pos (16UL) #define HSP_TRGINSELR0_TRG2SEL_Msk (0x3FUL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x003F0000 */ #define HSP_TRGINSELR0_TRG2SEL HSP_TRGINSELR0_TRG2SEL_Msk /*!< TRG2SEL[5:0] bits (Input trigger selection for TRGIN2) */ #define HSP_TRGINSELR0_TRG2SEL_0 (0x01UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00010000 */ @@ -11656,8 +12995,8 @@ typedef struct #define HSP_TRGINSELR0_TRG2SEL_3 (0x08UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00080000 */ #define HSP_TRGINSELR0_TRG2SEL_4 (0x10UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00100000 */ #define HSP_TRGINSELR0_TRG2SEL_5 (0x20UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00200000 */ -/*!< TRG3SEL configuration */ -#define HSP_TRGINSELR0_TRG3SEL_Pos (24U) + +#define HSP_TRGINSELR0_TRG3SEL_Pos (24UL) #define HSP_TRGINSELR0_TRG3SEL_Msk (0x3FUL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x3F000000 */ #define HSP_TRGINSELR0_TRG3SEL HSP_TRGINSELR0_TRG3SEL_Msk /*!< TRG3SEL[5:0] bits (Input trigger selection for TRGIN3) */ #define HSP_TRGINSELR0_TRG3SEL_0 (0x01UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x01000000 */ @@ -11668,8 +13007,7 @@ typedef struct #define HSP_TRGINSELR0_TRG3SEL_5 (0x20UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x20000000 */ /******************** Bit definition for HSP_TRGINSELR1 register ********************/ -/*!< TRG4SEL configuration */ -#define HSP_TRGINSELR1_TRG4SEL_Pos (0U) +#define HSP_TRGINSELR1_TRG4SEL_Pos (0UL) #define HSP_TRGINSELR1_TRG4SEL_Msk (0x3FUL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x0000003F */ #define HSP_TRGINSELR1_TRG4SEL HSP_TRGINSELR1_TRG4SEL_Msk /*!< TRG4SEL[5:0] bits (Input trigger selection for TRGIN4) */ #define HSP_TRGINSELR1_TRG4SEL_0 (0x01UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000001 */ @@ -11678,8 +13016,8 @@ typedef struct #define HSP_TRGINSELR1_TRG4SEL_3 (0x08UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000008 */ #define HSP_TRGINSELR1_TRG4SEL_4 (0x10UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000010 */ #define HSP_TRGINSELR1_TRG4SEL_5 (0x20UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000020 */ -/*!< TRG5SEL configuration */ -#define HSP_TRGINSELR1_TRG5SEL_Pos (8U) + +#define HSP_TRGINSELR1_TRG5SEL_Pos (8UL) #define HSP_TRGINSELR1_TRG5SEL_Msk (0x3FUL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00003F00 */ #define HSP_TRGINSELR1_TRG5SEL HSP_TRGINSELR1_TRG5SEL_Msk /*!< TRG5SEL[5:0] bits (Input trigger selection for TRGIN5) */ #define HSP_TRGINSELR1_TRG5SEL_0 (0x01UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00000100 */ @@ -11688,8 +13026,8 @@ typedef struct #define HSP_TRGINSELR1_TRG5SEL_3 (0x08UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00000800 */ #define HSP_TRGINSELR1_TRG5SEL_4 (0x10UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00001000 */ #define HSP_TRGINSELR1_TRG5SEL_5 (0x20UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00002000 */ -/*!< TRG6SEL configuration */ -#define HSP_TRGINSELR1_TRG6SEL_Pos (16U) + +#define HSP_TRGINSELR1_TRG6SEL_Pos (16UL) #define HSP_TRGINSELR1_TRG6SEL_Msk (0x3FUL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x003F0000 */ #define HSP_TRGINSELR1_TRG6SEL HSP_TRGINSELR1_TRG6SEL_Msk /*!< TRG6SEL[5:0] bits (Input trigger selection for TRGIN6) */ #define HSP_TRGINSELR1_TRG6SEL_0 (0x01UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00010000 */ @@ -11698,8 +13036,8 @@ typedef struct #define HSP_TRGINSELR1_TRG6SEL_3 (0x08UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00080000 */ #define HSP_TRGINSELR1_TRG6SEL_4 (0x10UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00100000 */ #define HSP_TRGINSELR1_TRG6SEL_5 (0x20UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00200000 */ -/*!< TRG7SEL configuration */ -#define HSP_TRGINSELR1_TRG7SEL_Pos (24U) + +#define HSP_TRGINSELR1_TRG7SEL_Pos (24UL) #define HSP_TRGINSELR1_TRG7SEL_Msk (0x3FUL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x3F000000 */ #define HSP_TRGINSELR1_TRG7SEL HSP_TRGINSELR1_TRG7SEL_Msk /*!< TRG7SEL[5:0] bits (Input trigger selection for TRGIN7) */ #define HSP_TRGINSELR1_TRG7SEL_0 (0x01UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x01000000 */ @@ -11710,8 +13048,7 @@ typedef struct #define HSP_TRGINSELR1_TRG7SEL_5 (0x20UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x20000000 */ /******************** Bit definition for HSP_TRGINSELR2 register ********************/ -/*!< TRG8SEL configuration */ -#define HSP_TRGINSELR2_TRG8SEL_Pos (0U) +#define HSP_TRGINSELR2_TRG8SEL_Pos (0UL) #define HSP_TRGINSELR2_TRG8SEL_Msk (0x3FUL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x0000003F */ #define HSP_TRGINSELR2_TRG8SEL HSP_TRGINSELR2_TRG8SEL_Msk /*!< TRG8SEL[5:0] bits (Input trigger selection for TRGIN8) */ #define HSP_TRGINSELR2_TRG8SEL_0 (0x01UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000001 */ @@ -11720,8 +13057,8 @@ typedef struct #define HSP_TRGINSELR2_TRG8SEL_3 (0x08UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000008 */ #define HSP_TRGINSELR2_TRG8SEL_4 (0x10UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000010 */ #define HSP_TRGINSELR2_TRG8SEL_5 (0x20UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000020 */ -/*!< TRG9SEL configuration */ -#define HSP_TRGINSELR2_TRG9SEL_Pos (8U) + +#define HSP_TRGINSELR2_TRG9SEL_Pos (8UL) #define HSP_TRGINSELR2_TRG9SEL_Msk (0x3FUL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00003F00 */ #define HSP_TRGINSELR2_TRG9SEL HSP_TRGINSELR2_TRG9SEL_Msk /*!< TRG9SEL[5:0] bits (Input trigger selection for TRGIN9) */ #define HSP_TRGINSELR2_TRG9SEL_0 (0x01UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00000100 */ @@ -11731,879 +13068,229 @@ typedef struct #define HSP_TRGINSELR2_TRG9SEL_4 (0x10UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00001000 */ #define HSP_TRGINSELR2_TRG9SEL_5 (0x20UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00002000 */ -/******************** Bit definition for HSP_BKO0CFGR register ********************/ -/*!< ACCEREN configuration */ -#define HSP_BKO0CFGR_ACCEREN_Pos (0U) -#define HSP_BKO0CFGR_ACCEREN_Msk (0x1UL << HSP_BKO0CFGR_ACCEREN_Pos) /*!< 0x00000001 */ -#define HSP_BKO0CFGR_ACCEREN HSP_BKO0CFGR_ACCEREN_Msk /*!< ACCEREN (Access error break enable for ACCERRF (1)) */ -/*!< FPUEREN configuration */ -#define HSP_BKO0CFGR_FPUEREN_Pos (1U) -#define HSP_BKO0CFGR_FPUEREN_Msk (0x1UL << HSP_BKO0CFGR_FPUEREN_Pos) /*!< 0x00000002 */ -#define HSP_BKO0CFGR_FPUEREN HSP_BKO0CFGR_FPUEREN_Msk /*!< FPUEREN (FPU error break enable for FPUERRF (1)) */ -/*!< OPCEREN configuration */ -#define HSP_BKO0CFGR_OPCEREN_Pos (2U) -#define HSP_BKO0CFGR_OPCEREN_Msk (0x1UL << HSP_BKO0CFGR_OPCEREN_Pos) /*!< 0x00000004 */ -#define HSP_BKO0CFGR_OPCEREN HSP_BKO0CFGR_OPCEREN_Msk /*!< OPCEREN (Opcode error break enable for OPCOERRF ) */ -/*!< PFCT28EN configuration */ -#define HSP_BKO0CFGR_PFCT28EN_Pos (4U) -#define HSP_BKO0CFGR_PFCT28EN_Msk (0x1UL << HSP_BKO0CFGR_PFCT28EN_Pos) /*!< 0x00000010 */ -#define HSP_BKO0CFGR_PFCT28EN HSP_BKO0CFGR_PFCT28EN_Msk /*!< PFCT28EN (Processing function flag break enable for PFCTF[28] (1)) */ -/*!< PFCT29EN configuration */ -#define HSP_BKO0CFGR_PFCT29EN_Pos (5U) -#define HSP_BKO0CFGR_PFCT29EN_Msk (0x1UL << HSP_BKO0CFGR_PFCT29EN_Pos) /*!< 0x00000020 */ -#define HSP_BKO0CFGR_PFCT29EN HSP_BKO0CFGR_PFCT29EN_Msk /*!< PFCT29EN (Processing function flag break enable for PFCTF[29] (1)) */ -/*!< PFCT30EN configuration */ -#define HSP_BKO0CFGR_PFCT30EN_Pos (6U) -#define HSP_BKO0CFGR_PFCT30EN_Msk (0x1UL << HSP_BKO0CFGR_PFCT30EN_Pos) /*!< 0x00000040 */ -#define HSP_BKO0CFGR_PFCT30EN HSP_BKO0CFGR_PFCT30EN_Msk /*!< PFCT30EN (Processing function flag break enable for PFCTF[30] (1)) */ -/*!< PFCT31EN configuration */ -#define HSP_BKO0CFGR_PFCT31EN_Pos (7U) -#define HSP_BKO0CFGR_PFCT31EN_Msk (0x1UL << HSP_BKO0CFGR_PFCT31EN_Pos) /*!< 0x00000080 */ -#define HSP_BKO0CFGR_PFCT31EN HSP_BKO0CFGR_PFCT31EN_Msk /*!< PFCT31EN (Processing function flag break enable for PFCTF[31] (1)) */ -/*!< FWEREN configuration */ -#define HSP_BKO0CFGR_FWEREN_Pos (12U) -#define HSP_BKO0CFGR_FWEREN_Msk (0x1UL << HSP_BKO0CFGR_FWEREN_Pos) /*!< 0x00001000 */ -#define HSP_BKO0CFGR_FWEREN HSP_BKO0CFGR_FWEREN_Msk /*!< FWEREN (Firmware error break enable for FWERRF (1)) */ -/*!< HDEGOVEN configuration */ -#define HSP_BKO0CFGR_HDEGOVEN_Pos (13U) -#define HSP_BKO0CFGR_HDEGOVEN_Msk (0x1UL << HSP_BKO0CFGR_HDEGOVEN_Pos) /*!< 0x00002000 */ -#define HSP_BKO0CFGR_HDEGOVEN HSP_BKO0CFGR_HDEGOVEN_Msk /*!< HDEGOVEN (HSP dedicated event generator overrun break enable for HDEGOVRF (1)) */ - -/******************** Bit definition for HSP_BKO1CFGR register ********************/ -/*!< ACCEREN configuration */ -#define HSP_BKO1CFGR_ACCEREN_Pos (0U) -#define HSP_BKO1CFGR_ACCEREN_Msk (0x1UL << HSP_BKO1CFGR_ACCEREN_Pos) /*!< 0x00000001 */ -#define HSP_BKO1CFGR_ACCEREN HSP_BKO1CFGR_ACCEREN_Msk /*!< ACCEREN (Access error break enable for ACCERRF (1)) */ -/*!< FPUEREN configuration */ -#define HSP_BKO1CFGR_FPUEREN_Pos (1U) -#define HSP_BKO1CFGR_FPUEREN_Msk (0x1UL << HSP_BKO1CFGR_FPUEREN_Pos) /*!< 0x00000002 */ -#define HSP_BKO1CFGR_FPUEREN HSP_BKO1CFGR_FPUEREN_Msk /*!< FPUEREN (FPU error break enable for FPUERRF (1)) */ -/*!< OPCEREN configuration */ -#define HSP_BKO1CFGR_OPCEREN_Pos (2U) -#define HSP_BKO1CFGR_OPCEREN_Msk (0x1UL << HSP_BKO1CFGR_OPCEREN_Pos) /*!< 0x00000004 */ -#define HSP_BKO1CFGR_OPCEREN HSP_BKO1CFGR_OPCEREN_Msk /*!< OPCEREN (Opcode error break enable for OPCOERRF ) */ -/*!< PFCT28EN configuration */ -#define HSP_BKO1CFGR_PFCT28EN_Pos (4U) -#define HSP_BKO1CFGR_PFCT28EN_Msk (0x1UL << HSP_BKO1CFGR_PFCT28EN_Pos) /*!< 0x00000010 */ -#define HSP_BKO1CFGR_PFCT28EN HSP_BKO1CFGR_PFCT28EN_Msk /*!< PFCT28EN (Processing function flag break enable for PFCTF[28] (1)) */ -/*!< PFCT29EN configuration */ -#define HSP_BKO1CFGR_PFCT29EN_Pos (5U) -#define HSP_BKO1CFGR_PFCT29EN_Msk (0x1UL << HSP_BKO1CFGR_PFCT29EN_Pos) /*!< 0x00000020 */ -#define HSP_BKO1CFGR_PFCT29EN HSP_BKO1CFGR_PFCT29EN_Msk /*!< PFCT29EN (Processing function flag break enable for PFCTF[29] (1)) */ -/*!< PFCT30EN configuration */ -#define HSP_BKO1CFGR_PFCT30EN_Pos (6U) -#define HSP_BKO1CFGR_PFCT30EN_Msk (0x1UL << HSP_BKO1CFGR_PFCT30EN_Pos) /*!< 0x00000040 */ -#define HSP_BKO1CFGR_PFCT30EN HSP_BKO1CFGR_PFCT30EN_Msk /*!< PFCT30EN (Processing function flag break enable for PFCTF[30] (1)) */ -/*!< PFCT31EN configuration */ -#define HSP_BKO1CFGR_PFCT31EN_Pos (7U) -#define HSP_BKO1CFGR_PFCT31EN_Msk (0x1UL << HSP_BKO1CFGR_PFCT31EN_Pos) /*!< 0x00000080 */ -#define HSP_BKO1CFGR_PFCT31EN HSP_BKO1CFGR_PFCT31EN_Msk /*!< PFCT31EN (Processing function flag break enable for PFCTF[31] (1)) */ -/*!< FWEREN configuration */ -#define HSP_BKO1CFGR_FWEREN_Pos (12U) -#define HSP_BKO1CFGR_FWEREN_Msk (0x1UL << HSP_BKO1CFGR_FWEREN_Pos) /*!< 0x00001000 */ -#define HSP_BKO1CFGR_FWEREN HSP_BKO1CFGR_FWEREN_Msk /*!< FWEREN (Firmware error break enable for FWERRF (1)) */ -/*!< HDEGOVEN configuration */ -#define HSP_BKO1CFGR_HDEGOVEN_Pos (13U) -#define HSP_BKO1CFGR_HDEGOVEN_Msk (0x1UL << HSP_BKO1CFGR_HDEGOVEN_Pos) /*!< 0x00002000 */ -#define HSP_BKO1CFGR_HDEGOVEN HSP_BKO1CFGR_HDEGOVEN_Msk /*!< HDEGOVEN (HSP dedicated event generator overrun break enable for HDEGOVRF (1)) */ - -/******************** Bit definition for HSP_BKO2CFGR register ********************/ -/*!< ACCEREN configuration */ -#define HSP_BKO2CFGR_ACCEREN_Pos (0U) -#define HSP_BKO2CFGR_ACCEREN_Msk (0x1UL << HSP_BKO2CFGR_ACCEREN_Pos) /*!< 0x00000001 */ -#define HSP_BKO2CFGR_ACCEREN HSP_BKO2CFGR_ACCEREN_Msk /*!< ACCEREN (Access error break enable for ACCERRF (1)) */ -/*!< FPUEREN configuration */ -#define HSP_BKO2CFGR_FPUEREN_Pos (1U) -#define HSP_BKO2CFGR_FPUEREN_Msk (0x1UL << HSP_BKO2CFGR_FPUEREN_Pos) /*!< 0x00000002 */ -#define HSP_BKO2CFGR_FPUEREN HSP_BKO2CFGR_FPUEREN_Msk /*!< FPUEREN (FPU error break enable for FPUERRF (1)) */ -/*!< OPCEREN configuration */ -#define HSP_BKO2CFGR_OPCEREN_Pos (2U) -#define HSP_BKO2CFGR_OPCEREN_Msk (0x1UL << HSP_BKO2CFGR_OPCEREN_Pos) /*!< 0x00000004 */ -#define HSP_BKO2CFGR_OPCEREN HSP_BKO2CFGR_OPCEREN_Msk /*!< OPCEREN (Opcode error break enable for OPCOERRF ) */ -/*!< PFCT28EN configuration */ -#define HSP_BKO2CFGR_PFCT28EN_Pos (4U) -#define HSP_BKO2CFGR_PFCT28EN_Msk (0x1UL << HSP_BKO2CFGR_PFCT28EN_Pos) /*!< 0x00000010 */ -#define HSP_BKO2CFGR_PFCT28EN HSP_BKO2CFGR_PFCT28EN_Msk /*!< PFCT28EN (Processing function flag break enable for PFCTF[28] (1)) */ -/*!< PFCT29EN configuration */ -#define HSP_BKO2CFGR_PFCT29EN_Pos (5U) -#define HSP_BKO2CFGR_PFCT29EN_Msk (0x1UL << HSP_BKO2CFGR_PFCT29EN_Pos) /*!< 0x00000020 */ -#define HSP_BKO2CFGR_PFCT29EN HSP_BKO2CFGR_PFCT29EN_Msk /*!< PFCT29EN (Processing function flag break enable for PFCTF[29] (1)) */ -/*!< PFCT30EN configuration */ -#define HSP_BKO2CFGR_PFCT30EN_Pos (6U) -#define HSP_BKO2CFGR_PFCT30EN_Msk (0x1UL << HSP_BKO2CFGR_PFCT30EN_Pos) /*!< 0x00000040 */ -#define HSP_BKO2CFGR_PFCT30EN HSP_BKO2CFGR_PFCT30EN_Msk /*!< PFCT30EN (Processing function flag break enable for PFCTF[30] (1)) */ -/*!< PFCT31EN configuration */ -#define HSP_BKO2CFGR_PFCT31EN_Pos (7U) -#define HSP_BKO2CFGR_PFCT31EN_Msk (0x1UL << HSP_BKO2CFGR_PFCT31EN_Pos) /*!< 0x00000080 */ -#define HSP_BKO2CFGR_PFCT31EN HSP_BKO2CFGR_PFCT31EN_Msk /*!< PFCT31EN (Processing function flag break enable for PFCTF[31] (1)) */ -/*!< FWEREN configuration */ -#define HSP_BKO2CFGR_FWEREN_Pos (12U) -#define HSP_BKO2CFGR_FWEREN_Msk (0x1UL << HSP_BKO2CFGR_FWEREN_Pos) /*!< 0x00001000 */ -#define HSP_BKO2CFGR_FWEREN HSP_BKO2CFGR_FWEREN_Msk /*!< FWEREN (Firmware error break enable for FWERRF (1)) */ -/*!< HDEGOVEN configuration */ -#define HSP_BKO2CFGR_HDEGOVEN_Pos (13U) -#define HSP_BKO2CFGR_HDEGOVEN_Msk (0x1UL << HSP_BKO2CFGR_HDEGOVEN_Pos) /*!< 0x00002000 */ -#define HSP_BKO2CFGR_HDEGOVEN HSP_BKO2CFGR_HDEGOVEN_Msk /*!< HDEGOVEN (HSP dedicated event generator overrun break enable for HDEGOVRF (1)) */ - -/******************** Bit definition for HSP_BKO3CFGR register ********************/ -/*!< ACCEREN configuration */ -#define HSP_BKO3CFGR_ACCEREN_Pos (0U) -#define HSP_BKO3CFGR_ACCEREN_Msk (0x1UL << HSP_BKO3CFGR_ACCEREN_Pos) /*!< 0x00000001 */ -#define HSP_BKO3CFGR_ACCEREN HSP_BKO3CFGR_ACCEREN_Msk /*!< ACCEREN (Access error break enable for ACCERRF (1)) */ -/*!< FPUEREN configuration */ -#define HSP_BKO3CFGR_FPUEREN_Pos (1U) -#define HSP_BKO3CFGR_FPUEREN_Msk (0x1UL << HSP_BKO3CFGR_FPUEREN_Pos) /*!< 0x00000002 */ -#define HSP_BKO3CFGR_FPUEREN HSP_BKO3CFGR_FPUEREN_Msk /*!< FPUEREN (FPU error break enable for FPUERRF (1)) */ -/*!< OPCEREN configuration */ -#define HSP_BKO3CFGR_OPCEREN_Pos (2U) -#define HSP_BKO3CFGR_OPCEREN_Msk (0x1UL << HSP_BKO3CFGR_OPCEREN_Pos) /*!< 0x00000004 */ -#define HSP_BKO3CFGR_OPCEREN HSP_BKO3CFGR_OPCEREN_Msk /*!< OPCEREN (Opcode error break enable for OPCOERRF ) */ -/*!< PFCT28EN configuration */ -#define HSP_BKO3CFGR_PFCT28EN_Pos (4U) -#define HSP_BKO3CFGR_PFCT28EN_Msk (0x1UL << HSP_BKO3CFGR_PFCT28EN_Pos) /*!< 0x00000010 */ -#define HSP_BKO3CFGR_PFCT28EN HSP_BKO3CFGR_PFCT28EN_Msk /*!< PFCT28EN (Processing function flag break enable for PFCTF[28] (1)) */ -/*!< PFCT29EN configuration */ -#define HSP_BKO3CFGR_PFCT29EN_Pos (5U) -#define HSP_BKO3CFGR_PFCT29EN_Msk (0x1UL << HSP_BKO3CFGR_PFCT29EN_Pos) /*!< 0x00000020 */ -#define HSP_BKO3CFGR_PFCT29EN HSP_BKO3CFGR_PFCT29EN_Msk /*!< PFCT29EN (Processing function flag break enable for PFCTF[29] (1)) */ -/*!< PFCT30EN configuration */ -#define HSP_BKO3CFGR_PFCT30EN_Pos (6U) -#define HSP_BKO3CFGR_PFCT30EN_Msk (0x1UL << HSP_BKO3CFGR_PFCT30EN_Pos) /*!< 0x00000040 */ -#define HSP_BKO3CFGR_PFCT30EN HSP_BKO3CFGR_PFCT30EN_Msk /*!< PFCT30EN (Processing function flag break enable for PFCTF[30] (1)) */ -/*!< PFCT31EN configuration */ -#define HSP_BKO3CFGR_PFCT31EN_Pos (7U) -#define HSP_BKO3CFGR_PFCT31EN_Msk (0x1UL << HSP_BKO3CFGR_PFCT31EN_Pos) /*!< 0x00000080 */ -#define HSP_BKO3CFGR_PFCT31EN HSP_BKO3CFGR_PFCT31EN_Msk /*!< PFCT31EN (Processing function flag break enable for PFCTF[31] (1)) */ -/*!< FWEREN configuration */ -#define HSP_BKO3CFGR_FWEREN_Pos (12U) -#define HSP_BKO3CFGR_FWEREN_Msk (0x1UL << HSP_BKO3CFGR_FWEREN_Pos) /*!< 0x00001000 */ -#define HSP_BKO3CFGR_FWEREN HSP_BKO3CFGR_FWEREN_Msk /*!< FWEREN (Firmware error break enable for FWERRF (1)) */ -/*!< HDEGOVEN configuration */ -#define HSP_BKO3CFGR_HDEGOVEN_Pos (13U) -#define HSP_BKO3CFGR_HDEGOVEN_Msk (0x1UL << HSP_BKO3CFGR_HDEGOVEN_Pos) /*!< 0x00002000 */ -#define HSP_BKO3CFGR_HDEGOVEN HSP_BKO3CFGR_HDEGOVEN_Msk /*!< HDEGOVEN (HSP dedicated event generator overrun break enable for HDEGOVRF (1)) */ +/******************** Bit definition for HSP_BKOxCFGR register ********************/ +#define HSP_BKOCFGR_ACCEREN_Pos (0U) +#define HSP_BKOCFGR_ACCEREN_Msk (0x1UL << HSP_BKOCFGR_ACCEREN_Pos) /*!< 0x00000001 */ +#define HSP_BKOCFGR_ACCEREN HSP_BKOCFGR_ACCEREN_Msk /*!< ACCEREN (Access error break enable for ACCERRF (1)) */ + +#define HSP_BKOCFGR_FPUEREN_Pos (1U) +#define HSP_BKOCFGR_FPUEREN_Msk (0x1UL << HSP_BKOCFGR_FPUEREN_Pos) /*!< 0x00000002 */ +#define HSP_BKOCFGR_FPUEREN HSP_BKOCFGR_FPUEREN_Msk /*!< FPUEREN (FPU error break enable for FPUERRF (1)) */ + +#define HSP_BKOCFGR_OPCEREN_Pos (2U) +#define HSP_BKOCFGR_OPCEREN_Msk (0x1UL << HSP_BKOCFGR_OPCEREN_Pos) /*!< 0x00000004 */ +#define HSP_BKOCFGR_OPCEREN HSP_BKOCFGR_OPCEREN_Msk /*!< OPCEREN (Opcode error break enable for OPCOERRF ) */ + +#define HSP_BKOCFGR_PFCT28EN_Pos (4U) +#define HSP_BKOCFGR_PFCT28EN_Msk (0x1UL << HSP_BKOCFGR_PFCT28EN_Pos) /*!< 0x00000010 */ +#define HSP_BKOCFGR_PFCT28EN HSP_BKOCFGR_PFCT28EN_Msk /*!< PFCT28EN (Processing function flag break enable for PFCTF[28] (1)) */ + +#define HSP_BKOCFGR_PFCT29EN_Pos (5U) +#define HSP_BKOCFGR_PFCT29EN_Msk (0x1UL << HSP_BKOCFGR_PFCT29EN_Pos) /*!< 0x00000020 */ +#define HSP_BKOCFGR_PFCT29EN HSP_BKOCFGR_PFCT29EN_Msk /*!< PFCT29EN (Processing function flag break enable for PFCTF[29] (1)) */ + +#define HSP_BKOCFGR_PFCT30EN_Pos (6U) +#define HSP_BKOCFGR_PFCT30EN_Msk (0x1UL << HSP_BKOCFGR_PFCT30EN_Pos) /*!< 0x00000040 */ +#define HSP_BKOCFGR_PFCT30EN HSP_BKOCFGR_PFCT30EN_Msk /*!< PFCT30EN (Processing function flag break enable for PFCTF[30] (1)) */ + +#define HSP_BKOCFGR_PFCT31EN_Pos (7U) +#define HSP_BKOCFGR_PFCT31EN_Msk (0x1UL << HSP_BKOCFGR_PFCT31EN_Pos) /*!< 0x00000080 */ +#define HSP_BKOCFGR_PFCT31EN HSP_BKOCFGR_PFCT31EN_Msk /*!< PFCT31EN (Processing function flag break enable for PFCTF[31] (1)) */ + +#define HSP_BKOCFGR_FWEREN_Pos (12U) +#define HSP_BKOCFGR_FWEREN_Msk (0x1UL << HSP_BKOCFGR_FWEREN_Pos) /*!< 0x00001000 */ +#define HSP_BKOCFGR_FWEREN HSP_BKOCFGR_FWEREN_Msk /*!< FWEREN (Firmware error break enable for FWERRF (1)) */ + +#define HSP_BKOCFGR_HDEGOVEN_Pos (13U) +#define HSP_BKOCFGR_HDEGOVEN_Msk (0x1UL << HSP_BKOCFGR_HDEGOVEN_Pos) /*!< 0x00002000 */ +#define HSP_BKOCFGR_HDEGOVEN HSP_BKOCFGR_HDEGOVEN_Msk /*!< HDEGOVEN (HSP dedicated event generator overrun break enable for HDEGOVRF (1)) */ /******************** Bit definition for HSP_BKICFGR register ********************/ -/*!< ACCEREN configuration */ -#define HSP_BKICFGR_ACCEREN_Pos (0U) +#define HSP_BKICFGR_ACCEREN_Pos (0UL) #define HSP_BKICFGR_ACCEREN_Msk (0x1UL << HSP_BKICFGR_ACCEREN_Pos) /*!< 0x00000001 */ #define HSP_BKICFGR_ACCEREN HSP_BKICFGR_ACCEREN_Msk /*!< ACCEREN (Access error break enable for ACCERRF (1)) */ -/*!< FPUEREN configuration */ -#define HSP_BKICFGR_FPUEREN_Pos (1U) + +#define HSP_BKICFGR_FPUEREN_Pos (1UL) #define HSP_BKICFGR_FPUEREN_Msk (0x1UL << HSP_BKICFGR_FPUEREN_Pos) /*!< 0x00000002 */ #define HSP_BKICFGR_FPUEREN HSP_BKICFGR_FPUEREN_Msk /*!< FPUEREN (FPU error break enable for FPUERRF (1)) */ -/*!< OPCEREN configuration */ -#define HSP_BKICFGR_OPCEREN_Pos (2U) + +#define HSP_BKICFGR_OPCEREN_Pos (2UL) #define HSP_BKICFGR_OPCEREN_Msk (0x1UL << HSP_BKICFGR_OPCEREN_Pos) /*!< 0x00000004 */ #define HSP_BKICFGR_OPCEREN HSP_BKICFGR_OPCEREN_Msk /*!< OPCEREN (Opcode error break enable for OPCOERRF ) */ -/*!< BKIEN configuration */ -#define HSP_BKICFGR_BKIEN_Pos (3U) -#define HSP_BKICFGR_BKIEN_Msk (0x1UL << HSP_BKICFGR_BKIEN_Pos) /*!< 0x00000008 */ -#define HSP_BKICFGR_BKIEN HSP_BKICFGR_BKIEN_Msk /*!< BKIEN (Break enable for hsp_break_in signal (1)) */ -/*!< PFCT28EN configuration */ -#define HSP_BKICFGR_PFCT28EN_Pos (4U) + +#define HSP_BKICFGR_PFCT28EN_Pos (4UL) #define HSP_BKICFGR_PFCT28EN_Msk (0x1UL << HSP_BKICFGR_PFCT28EN_Pos) /*!< 0x00000010 */ #define HSP_BKICFGR_PFCT28EN HSP_BKICFGR_PFCT28EN_Msk /*!< PFCT28EN (Processing function flag break enable for PFCTF[28] (1)) */ -/*!< PFCT29EN configuration */ -#define HSP_BKICFGR_PFCT29EN_Pos (5U) + +#define HSP_BKICFGR_PFCT29EN_Pos (5UL) #define HSP_BKICFGR_PFCT29EN_Msk (0x1UL << HSP_BKICFGR_PFCT29EN_Pos) /*!< 0x00000020 */ #define HSP_BKICFGR_PFCT29EN HSP_BKICFGR_PFCT29EN_Msk /*!< PFCT29EN (Processing function flag break enable for PFCTF[29] (1)) */ -/*!< PFCT30EN configuration */ -#define HSP_BKICFGR_PFCT30EN_Pos (6U) + +#define HSP_BKICFGR_PFCT30EN_Pos (6UL) #define HSP_BKICFGR_PFCT30EN_Msk (0x1UL << HSP_BKICFGR_PFCT30EN_Pos) /*!< 0x00000040 */ #define HSP_BKICFGR_PFCT30EN HSP_BKICFGR_PFCT30EN_Msk /*!< PFCT30EN (Processing function flag break enable for PFCTF[30] (1)) */ -/*!< PFCT31EN configuration */ -#define HSP_BKICFGR_PFCT31EN_Pos (7U) + +#define HSP_BKICFGR_PFCT31EN_Pos (7UL) #define HSP_BKICFGR_PFCT31EN_Msk (0x1UL << HSP_BKICFGR_PFCT31EN_Pos) /*!< 0x00000080 */ #define HSP_BKICFGR_PFCT31EN HSP_BKICFGR_PFCT31EN_Msk /*!< PFCT31EN (Processing function flag break enable for PFCTF[31] (1)) */ -/*!< FWEREN configuration */ -#define HSP_BKICFGR_FWEREN_Pos (12U) + +#define HSP_BKICFGR_FWEREN_Pos (12UL) #define HSP_BKICFGR_FWEREN_Msk (0x1UL << HSP_BKICFGR_FWEREN_Pos) /*!< 0x00001000 */ #define HSP_BKICFGR_FWEREN HSP_BKICFGR_FWEREN_Msk /*!< FWEREN (Firmware error break enable for FWERRF (1)) */ -/*!< HDEGOVEN configuration */ -#define HSP_BKICFGR_HDEGOVEN_Pos (13U) + +#define HSP_BKICFGR_HDEGOVEN_Pos (13UL) #define HSP_BKICFGR_HDEGOVEN_Msk (0x1UL << HSP_BKICFGR_HDEGOVEN_Pos) /*!< 0x00002000 */ #define HSP_BKICFGR_HDEGOVEN HSP_BKICFGR_HDEGOVEN_Msk /*!< HDEGOVEN (HSP dedicated event generator overrun break enable for HDEGOVRF (1)) */ -/*!< FSATEN configuration */ -#define HSP_BKICFGR_FSATEN_Pos (14U) + +#define HSP_BKICFGR_FSATEN_Pos (14UL) #define HSP_BKICFGR_FSATEN_Msk (0x1UL << HSP_BKICFGR_FSATEN_Pos) /*!< 0x00004000 */ #define HSP_BKICFGR_FSATEN HSP_BKICFGR_FSATEN_Msk /*!< FSATEN (FPU saturation break enable for FPUSATF (1)) */ -/*!< SSEN configuration */ -#define HSP_BKICFGR_SSEN_Pos (17U) + +#define HSP_BKICFGR_SSEN_Pos (17UL) #define HSP_BKICFGR_SSEN_Msk (0x1UL << HSP_BKICFGR_SSEN_Pos) /*!< 0x00020000 */ #define HSP_BKICFGR_SSEN HSP_BKICFGR_SSEN_Msk /*!< SSEN (Single step enable (1)) */ -/*!< BKIP configuration */ -#define HSP_BKICFGR_BKIP_Pos (18U) -#define HSP_BKICFGR_BKIP_Msk (0x1UL << HSP_BKICFGR_BKIP_Pos) /*!< 0x00040000 */ -#define HSP_BKICFGR_BKIP HSP_BKICFGR_BKIP_Msk /*!< BKIP (Break enable input polarity (1)) */ /******************** Bit definition for HSP_FWERR register ********************/ -/*!< FWERRN configuration */ -#define HSP_FWERR_FWERRN_Pos (0U) +#define HSP_FWERR_FWERRN_Pos (0UL) #define HSP_FWERR_FWERRN_Msk (0x3FFUL << HSP_FWERR_FWERRN_Pos) /*!< 0x000003FF */ #define HSP_FWERR_FWERRN HSP_FWERR_FWERRN_Msk /*!< FWERRN[9:0] bits (Firmware error number) */ -#define HSP_FWERR_FWERRN_0 (0x001UL << HSP_FWERR_FWERRN_Pos) /*!< 0x00000001 */ -#define HSP_FWERR_FWERRN_1 (0x002UL << HSP_FWERR_FWERRN_Pos) /*!< 0x00000002 */ -#define HSP_FWERR_FWERRN_2 (0x004UL << HSP_FWERR_FWERRN_Pos) /*!< 0x00000004 */ -#define HSP_FWERR_FWERRN_3 (0x008UL << HSP_FWERR_FWERRN_Pos) /*!< 0x00000008 */ -#define HSP_FWERR_FWERRN_4 (0x010UL << HSP_FWERR_FWERRN_Pos) /*!< 0x00000010 */ -#define HSP_FWERR_FWERRN_5 (0x020UL << HSP_FWERR_FWERRN_Pos) /*!< 0x00000020 */ -#define HSP_FWERR_FWERRN_6 (0x040UL << HSP_FWERR_FWERRN_Pos) /*!< 0x00000040 */ -#define HSP_FWERR_FWERRN_7 (0x080UL << HSP_FWERR_FWERRN_Pos) /*!< 0x00000080 */ -#define HSP_FWERR_FWERRN_8 (0x100UL << HSP_FWERR_FWERRN_Pos) /*!< 0x00000100 */ -#define HSP_FWERR_FWERRN_9 (0x200UL << HSP_FWERR_FWERRN_Pos) /*!< 0x00000200 */ /******************** Bit definition for HSP_PARAMR0 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR0_PARAM_Pos (0U) +#define HSP_PARAMR0_PARAM_Pos (0UL) #define HSP_PARAMR0_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR0_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR0_PARAM HSP_PARAMR0_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR0_PARAM_0 (0x00001UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR0_PARAM_1 (0x00002UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR0_PARAM_2 (0x00004UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR0_PARAM_3 (0x00008UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR0_PARAM_4 (0x00010UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR0_PARAM_5 (0x00020UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR0_PARAM_6 (0x00040UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR0_PARAM_7 (0x00080UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR0_PARAM_8 (0x00100UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR0_PARAM_9 (0x00200UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR0_PARAM_10 (0x00400UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR0_PARAM_11 (0x00800UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR0_PARAM_12 (0x01000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR0_PARAM_13 (0x02000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR0_PARAM_14 (0x04000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR0_PARAM_15 (0x08000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR0_PARAM_16 (0x10000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR0_PARAM_17 (0x20000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR0_PARAM_18 (0x40000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR0_PARAM_19 (0x80000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR0_PARAM_20 (0x100000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR0_PARAM_21 (0x200000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR0_PARAM_22 (0x400000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR0_PARAM_23 (0x800000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR0_PARAM_24 (0x1000000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR0_PARAM_25 (0x2000000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR0_PARAM_26 (0x4000000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR0_PARAM_27 (0x8000000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR0_PARAM_28 (0x10000000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR0_PARAM_29 (0x20000000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR0_PARAM_30 (0x40000000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR0_PARAM_31 (0x80000000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR1 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR1_PARAM_Pos (0U) +#define HSP_PARAMR1_PARAM_Pos (0UL) #define HSP_PARAMR1_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR1_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR1_PARAM HSP_PARAMR1_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR1_PARAM_0 (0x00001UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR1_PARAM_1 (0x00002UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR1_PARAM_2 (0x00004UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR1_PARAM_3 (0x00008UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR1_PARAM_4 (0x00010UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR1_PARAM_5 (0x00020UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR1_PARAM_6 (0x00040UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR1_PARAM_7 (0x00080UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR1_PARAM_8 (0x00100UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR1_PARAM_9 (0x00200UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR1_PARAM_10 (0x00400UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR1_PARAM_11 (0x00800UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR1_PARAM_12 (0x01000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR1_PARAM_13 (0x02000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR1_PARAM_14 (0x04000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR1_PARAM_15 (0x08000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR1_PARAM_16 (0x10000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR1_PARAM_17 (0x20000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR1_PARAM_18 (0x40000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR1_PARAM_19 (0x80000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR1_PARAM_20 (0x100000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR1_PARAM_21 (0x200000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR1_PARAM_22 (0x400000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR1_PARAM_23 (0x800000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR1_PARAM_24 (0x1000000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR1_PARAM_25 (0x2000000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR1_PARAM_26 (0x4000000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR1_PARAM_27 (0x8000000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR1_PARAM_28 (0x10000000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR1_PARAM_29 (0x20000000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR1_PARAM_30 (0x40000000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR1_PARAM_31 (0x80000000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR2 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR2_PARAM_Pos (0U) +#define HSP_PARAMR2_PARAM_Pos (0UL) #define HSP_PARAMR2_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR2_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR2_PARAM HSP_PARAMR2_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR2_PARAM_0 (0x00001UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR2_PARAM_1 (0x00002UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR2_PARAM_2 (0x00004UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR2_PARAM_3 (0x00008UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR2_PARAM_4 (0x00010UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR2_PARAM_5 (0x00020UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR2_PARAM_6 (0x00040UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR2_PARAM_7 (0x00080UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR2_PARAM_8 (0x00100UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR2_PARAM_9 (0x00200UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR2_PARAM_10 (0x00400UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR2_PARAM_11 (0x00800UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR2_PARAM_12 (0x01000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR2_PARAM_13 (0x02000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR2_PARAM_14 (0x04000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR2_PARAM_15 (0x08000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR2_PARAM_16 (0x10000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR2_PARAM_17 (0x20000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR2_PARAM_18 (0x40000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR2_PARAM_19 (0x80000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR2_PARAM_20 (0x100000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR2_PARAM_21 (0x200000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR2_PARAM_22 (0x400000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR2_PARAM_23 (0x800000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR2_PARAM_24 (0x1000000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR2_PARAM_25 (0x2000000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR2_PARAM_26 (0x4000000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR2_PARAM_27 (0x8000000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR2_PARAM_28 (0x10000000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR2_PARAM_29 (0x20000000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR2_PARAM_30 (0x40000000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR2_PARAM_31 (0x80000000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR3 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR3_PARAM_Pos (0U) +#define HSP_PARAMR3_PARAM_Pos (0UL) #define HSP_PARAMR3_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR3_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR3_PARAM HSP_PARAMR3_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR3_PARAM_0 (0x00001UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR3_PARAM_1 (0x00002UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR3_PARAM_2 (0x00004UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR3_PARAM_3 (0x00008UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR3_PARAM_4 (0x00010UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR3_PARAM_5 (0x00020UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR3_PARAM_6 (0x00040UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR3_PARAM_7 (0x00080UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR3_PARAM_8 (0x00100UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR3_PARAM_9 (0x00200UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR3_PARAM_10 (0x00400UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR3_PARAM_11 (0x00800UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR3_PARAM_12 (0x01000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR3_PARAM_13 (0x02000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR3_PARAM_14 (0x04000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR3_PARAM_15 (0x08000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR3_PARAM_16 (0x10000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR3_PARAM_17 (0x20000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR3_PARAM_18 (0x40000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR3_PARAM_19 (0x80000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR3_PARAM_20 (0x100000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR3_PARAM_21 (0x200000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR3_PARAM_22 (0x400000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR3_PARAM_23 (0x800000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR3_PARAM_24 (0x1000000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR3_PARAM_25 (0x2000000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR3_PARAM_26 (0x4000000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR3_PARAM_27 (0x8000000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR3_PARAM_28 (0x10000000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR3_PARAM_29 (0x20000000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR3_PARAM_30 (0x40000000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR3_PARAM_31 (0x80000000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR4 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR4_PARAM_Pos (0U) +#define HSP_PARAMR4_PARAM_Pos (0UL) #define HSP_PARAMR4_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR4_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR4_PARAM HSP_PARAMR4_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR4_PARAM_0 (0x00001UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR4_PARAM_1 (0x00002UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR4_PARAM_2 (0x00004UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR4_PARAM_3 (0x00008UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR4_PARAM_4 (0x00010UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR4_PARAM_5 (0x00020UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR4_PARAM_6 (0x00040UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR4_PARAM_7 (0x00080UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR4_PARAM_8 (0x00100UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR4_PARAM_9 (0x00200UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR4_PARAM_10 (0x00400UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR4_PARAM_11 (0x00800UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR4_PARAM_12 (0x01000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR4_PARAM_13 (0x02000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR4_PARAM_14 (0x04000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR4_PARAM_15 (0x08000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR4_PARAM_16 (0x10000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR4_PARAM_17 (0x20000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR4_PARAM_18 (0x40000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR4_PARAM_19 (0x80000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR4_PARAM_20 (0x100000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR4_PARAM_21 (0x200000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR4_PARAM_22 (0x400000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR4_PARAM_23 (0x800000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR4_PARAM_24 (0x1000000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR4_PARAM_25 (0x2000000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR4_PARAM_26 (0x4000000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR4_PARAM_27 (0x8000000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR4_PARAM_28 (0x10000000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR4_PARAM_29 (0x20000000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR4_PARAM_30 (0x40000000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR4_PARAM_31 (0x80000000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR5 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR5_PARAM_Pos (0U) +#define HSP_PARAMR5_PARAM_Pos (0UL) #define HSP_PARAMR5_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR5_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR5_PARAM HSP_PARAMR5_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR5_PARAM_0 (0x00001UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR5_PARAM_1 (0x00002UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR5_PARAM_2 (0x00004UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR5_PARAM_3 (0x00008UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR5_PARAM_4 (0x00010UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR5_PARAM_5 (0x00020UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR5_PARAM_6 (0x00040UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR5_PARAM_7 (0x00080UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR5_PARAM_8 (0x00100UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR5_PARAM_9 (0x00200UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR5_PARAM_10 (0x00400UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR5_PARAM_11 (0x00800UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR5_PARAM_12 (0x01000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR5_PARAM_13 (0x02000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR5_PARAM_14 (0x04000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR5_PARAM_15 (0x08000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR5_PARAM_16 (0x10000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR5_PARAM_17 (0x20000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR5_PARAM_18 (0x40000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR5_PARAM_19 (0x80000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR5_PARAM_20 (0x100000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR5_PARAM_21 (0x200000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR5_PARAM_22 (0x400000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR5_PARAM_23 (0x800000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR5_PARAM_24 (0x1000000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR5_PARAM_25 (0x2000000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR5_PARAM_26 (0x4000000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR5_PARAM_27 (0x8000000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR5_PARAM_28 (0x10000000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR5_PARAM_29 (0x20000000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR5_PARAM_30 (0x40000000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR5_PARAM_31 (0x80000000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR6 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR6_PARAM_Pos (0U) +#define HSP_PARAMR6_PARAM_Pos (0UL) #define HSP_PARAMR6_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR6_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR6_PARAM HSP_PARAMR6_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR6_PARAM_0 (0x00001UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR6_PARAM_1 (0x00002UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR6_PARAM_2 (0x00004UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR6_PARAM_3 (0x00008UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR6_PARAM_4 (0x00010UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR6_PARAM_5 (0x00020UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR6_PARAM_6 (0x00040UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR6_PARAM_7 (0x00080UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR6_PARAM_8 (0x00100UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR6_PARAM_9 (0x00200UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR6_PARAM_10 (0x00400UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR6_PARAM_11 (0x00800UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR6_PARAM_12 (0x01000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR6_PARAM_13 (0x02000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR6_PARAM_14 (0x04000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR6_PARAM_15 (0x08000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR6_PARAM_16 (0x10000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR6_PARAM_17 (0x20000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR6_PARAM_18 (0x40000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR6_PARAM_19 (0x80000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR6_PARAM_20 (0x100000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR6_PARAM_21 (0x200000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR6_PARAM_22 (0x400000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR6_PARAM_23 (0x800000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR6_PARAM_24 (0x1000000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR6_PARAM_25 (0x2000000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR6_PARAM_26 (0x4000000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR6_PARAM_27 (0x8000000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR6_PARAM_28 (0x10000000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR6_PARAM_29 (0x20000000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR6_PARAM_30 (0x40000000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR6_PARAM_31 (0x80000000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR7 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR7_PARAM_Pos (0U) +#define HSP_PARAMR7_PARAM_Pos (0UL) #define HSP_PARAMR7_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR7_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR7_PARAM HSP_PARAMR7_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR7_PARAM_0 (0x00001UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR7_PARAM_1 (0x00002UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR7_PARAM_2 (0x00004UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR7_PARAM_3 (0x00008UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR7_PARAM_4 (0x00010UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR7_PARAM_5 (0x00020UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR7_PARAM_6 (0x00040UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR7_PARAM_7 (0x00080UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR7_PARAM_8 (0x00100UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR7_PARAM_9 (0x00200UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR7_PARAM_10 (0x00400UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR7_PARAM_11 (0x00800UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR7_PARAM_12 (0x01000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR7_PARAM_13 (0x02000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR7_PARAM_14 (0x04000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR7_PARAM_15 (0x08000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR7_PARAM_16 (0x10000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR7_PARAM_17 (0x20000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR7_PARAM_18 (0x40000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR7_PARAM_19 (0x80000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR7_PARAM_20 (0x100000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR7_PARAM_21 (0x200000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR7_PARAM_22 (0x400000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR7_PARAM_23 (0x800000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR7_PARAM_24 (0x1000000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR7_PARAM_25 (0x2000000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR7_PARAM_26 (0x4000000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR7_PARAM_27 (0x8000000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR7_PARAM_28 (0x10000000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR7_PARAM_29 (0x20000000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR7_PARAM_30 (0x40000000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR7_PARAM_31 (0x80000000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR8 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR8_PARAM_Pos (0U) +#define HSP_PARAMR8_PARAM_Pos (0UL) #define HSP_PARAMR8_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR8_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR8_PARAM HSP_PARAMR8_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR8_PARAM_0 (0x00001UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR8_PARAM_1 (0x00002UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR8_PARAM_2 (0x00004UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR8_PARAM_3 (0x00008UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR8_PARAM_4 (0x00010UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR8_PARAM_5 (0x00020UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR8_PARAM_6 (0x00040UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR8_PARAM_7 (0x00080UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR8_PARAM_8 (0x00100UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR8_PARAM_9 (0x00200UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR8_PARAM_10 (0x00400UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR8_PARAM_11 (0x00800UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR8_PARAM_12 (0x01000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR8_PARAM_13 (0x02000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR8_PARAM_14 (0x04000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR8_PARAM_15 (0x08000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR8_PARAM_16 (0x10000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR8_PARAM_17 (0x20000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR8_PARAM_18 (0x40000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR8_PARAM_19 (0x80000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR8_PARAM_20 (0x100000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR8_PARAM_21 (0x200000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR8_PARAM_22 (0x400000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR8_PARAM_23 (0x800000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR8_PARAM_24 (0x1000000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR8_PARAM_25 (0x2000000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR8_PARAM_26 (0x4000000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR8_PARAM_27 (0x8000000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR8_PARAM_28 (0x10000000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR8_PARAM_29 (0x20000000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR8_PARAM_30 (0x40000000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR8_PARAM_31 (0x80000000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR9 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR9_PARAM_Pos (0U) +#define HSP_PARAMR9_PARAM_Pos (0UL) #define HSP_PARAMR9_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR9_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR9_PARAM HSP_PARAMR9_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR9_PARAM_0 (0x00001UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR9_PARAM_1 (0x00002UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR9_PARAM_2 (0x00004UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR9_PARAM_3 (0x00008UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR9_PARAM_4 (0x00010UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR9_PARAM_5 (0x00020UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR9_PARAM_6 (0x00040UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR9_PARAM_7 (0x00080UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR9_PARAM_8 (0x00100UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR9_PARAM_9 (0x00200UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR9_PARAM_10 (0x00400UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR9_PARAM_11 (0x00800UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR9_PARAM_12 (0x01000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR9_PARAM_13 (0x02000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR9_PARAM_14 (0x04000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR9_PARAM_15 (0x08000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR9_PARAM_16 (0x10000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR9_PARAM_17 (0x20000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR9_PARAM_18 (0x40000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR9_PARAM_19 (0x80000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR9_PARAM_20 (0x100000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR9_PARAM_21 (0x200000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR9_PARAM_22 (0x400000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR9_PARAM_23 (0x800000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR9_PARAM_24 (0x1000000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR9_PARAM_25 (0x2000000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR9_PARAM_26 (0x4000000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR9_PARAM_27 (0x8000000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR9_PARAM_28 (0x10000000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR9_PARAM_29 (0x20000000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR9_PARAM_30 (0x40000000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR9_PARAM_31 (0x80000000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR10 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR10_PARAM_Pos (0U) +#define HSP_PARAMR10_PARAM_Pos (0UL) #define HSP_PARAMR10_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR10_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR10_PARAM HSP_PARAMR10_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR10_PARAM_0 (0x00001UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR10_PARAM_1 (0x00002UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR10_PARAM_2 (0x00004UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR10_PARAM_3 (0x00008UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR10_PARAM_4 (0x00010UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR10_PARAM_5 (0x00020UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR10_PARAM_6 (0x00040UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR10_PARAM_7 (0x00080UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR10_PARAM_8 (0x00100UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR10_PARAM_9 (0x00200UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR10_PARAM_10 (0x00400UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR10_PARAM_11 (0x00800UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR10_PARAM_12 (0x01000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR10_PARAM_13 (0x02000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR10_PARAM_14 (0x04000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR10_PARAM_15 (0x08000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR10_PARAM_16 (0x10000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR10_PARAM_17 (0x20000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR10_PARAM_18 (0x40000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR10_PARAM_19 (0x80000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR10_PARAM_20 (0x100000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR10_PARAM_21 (0x200000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR10_PARAM_22 (0x400000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR10_PARAM_23 (0x800000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR10_PARAM_24 (0x1000000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR10_PARAM_25 (0x2000000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR10_PARAM_26 (0x4000000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR10_PARAM_27 (0x8000000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR10_PARAM_28 (0x10000000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR10_PARAM_29 (0x20000000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR10_PARAM_30 (0x40000000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR10_PARAM_31 (0x80000000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR11 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR11_PARAM_Pos (0U) +#define HSP_PARAMR11_PARAM_Pos (0UL) #define HSP_PARAMR11_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR11_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR11_PARAM HSP_PARAMR11_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR11_PARAM_0 (0x00001UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR11_PARAM_1 (0x00002UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR11_PARAM_2 (0x00004UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR11_PARAM_3 (0x00008UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR11_PARAM_4 (0x00010UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR11_PARAM_5 (0x00020UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR11_PARAM_6 (0x00040UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR11_PARAM_7 (0x00080UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR11_PARAM_8 (0x00100UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR11_PARAM_9 (0x00200UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR11_PARAM_10 (0x00400UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR11_PARAM_11 (0x00800UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR11_PARAM_12 (0x01000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR11_PARAM_13 (0x02000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR11_PARAM_14 (0x04000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR11_PARAM_15 (0x08000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR11_PARAM_16 (0x10000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR11_PARAM_17 (0x20000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR11_PARAM_18 (0x40000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR11_PARAM_19 (0x80000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR11_PARAM_20 (0x100000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR11_PARAM_21 (0x200000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR11_PARAM_22 (0x400000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR11_PARAM_23 (0x800000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR11_PARAM_24 (0x1000000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR11_PARAM_25 (0x2000000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR11_PARAM_26 (0x4000000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR11_PARAM_27 (0x8000000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR11_PARAM_28 (0x10000000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR11_PARAM_29 (0x20000000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR11_PARAM_30 (0x40000000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR11_PARAM_31 (0x80000000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR12 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR12_PARAM_Pos (0U) +#define HSP_PARAMR12_PARAM_Pos (0UL) #define HSP_PARAMR12_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR12_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR12_PARAM HSP_PARAMR12_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR12_PARAM_0 (0x00001UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR12_PARAM_1 (0x00002UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR12_PARAM_2 (0x00004UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR12_PARAM_3 (0x00008UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR12_PARAM_4 (0x00010UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR12_PARAM_5 (0x00020UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR12_PARAM_6 (0x00040UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR12_PARAM_7 (0x00080UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR12_PARAM_8 (0x00100UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR12_PARAM_9 (0x00200UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR12_PARAM_10 (0x00400UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR12_PARAM_11 (0x00800UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR12_PARAM_12 (0x01000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR12_PARAM_13 (0x02000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR12_PARAM_14 (0x04000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR12_PARAM_15 (0x08000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR12_PARAM_16 (0x10000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR12_PARAM_17 (0x20000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR12_PARAM_18 (0x40000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR12_PARAM_19 (0x80000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR12_PARAM_20 (0x100000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR12_PARAM_21 (0x200000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR12_PARAM_22 (0x400000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR12_PARAM_23 (0x800000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR12_PARAM_24 (0x1000000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR12_PARAM_25 (0x2000000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR12_PARAM_26 (0x4000000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR12_PARAM_27 (0x8000000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR12_PARAM_28 (0x10000000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR12_PARAM_29 (0x20000000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR12_PARAM_30 (0x40000000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR12_PARAM_31 (0x80000000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR13 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR13_PARAM_Pos (0U) +#define HSP_PARAMR13_PARAM_Pos (0UL) #define HSP_PARAMR13_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR13_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR13_PARAM HSP_PARAMR13_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR13_PARAM_0 (0x00001UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR13_PARAM_1 (0x00002UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR13_PARAM_2 (0x00004UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR13_PARAM_3 (0x00008UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR13_PARAM_4 (0x00010UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR13_PARAM_5 (0x00020UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR13_PARAM_6 (0x00040UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR13_PARAM_7 (0x00080UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR13_PARAM_8 (0x00100UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR13_PARAM_9 (0x00200UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR13_PARAM_10 (0x00400UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR13_PARAM_11 (0x00800UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR13_PARAM_12 (0x01000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR13_PARAM_13 (0x02000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR13_PARAM_14 (0x04000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR13_PARAM_15 (0x08000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR13_PARAM_16 (0x10000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR13_PARAM_17 (0x20000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR13_PARAM_18 (0x40000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR13_PARAM_19 (0x80000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR13_PARAM_20 (0x100000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR13_PARAM_21 (0x200000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR13_PARAM_22 (0x400000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR13_PARAM_23 (0x800000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR13_PARAM_24 (0x1000000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR13_PARAM_25 (0x2000000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR13_PARAM_26 (0x4000000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR13_PARAM_27 (0x8000000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR13_PARAM_28 (0x10000000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR13_PARAM_29 (0x20000000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR13_PARAM_30 (0x40000000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR13_PARAM_31 (0x80000000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR14 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR14_PARAM_Pos (0U) +#define HSP_PARAMR14_PARAM_Pos (0UL) #define HSP_PARAMR14_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR14_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR14_PARAM HSP_PARAMR14_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR14_PARAM_0 (0x00001UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR14_PARAM_1 (0x00002UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR14_PARAM_2 (0x00004UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR14_PARAM_3 (0x00008UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR14_PARAM_4 (0x00010UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR14_PARAM_5 (0x00020UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR14_PARAM_6 (0x00040UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR14_PARAM_7 (0x00080UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR14_PARAM_8 (0x00100UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR14_PARAM_9 (0x00200UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR14_PARAM_10 (0x00400UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR14_PARAM_11 (0x00800UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR14_PARAM_12 (0x01000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR14_PARAM_13 (0x02000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR14_PARAM_14 (0x04000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR14_PARAM_15 (0x08000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR14_PARAM_16 (0x10000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR14_PARAM_17 (0x20000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR14_PARAM_18 (0x40000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR14_PARAM_19 (0x80000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR14_PARAM_20 (0x100000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR14_PARAM_21 (0x200000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR14_PARAM_22 (0x400000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR14_PARAM_23 (0x800000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR14_PARAM_24 (0x1000000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR14_PARAM_25 (0x2000000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR14_PARAM_26 (0x4000000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR14_PARAM_27 (0x8000000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR14_PARAM_28 (0x10000000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR14_PARAM_29 (0x20000000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR14_PARAM_30 (0x40000000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR14_PARAM_31 (0x80000000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR15 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR15_PARAM_Pos (0U) +#define HSP_PARAMR15_PARAM_Pos (0UL) #define HSP_PARAMR15_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR15_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR15_PARAM HSP_PARAMR15_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR15_PARAM_0 (0x00001UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR15_PARAM_1 (0x00002UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR15_PARAM_2 (0x00004UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR15_PARAM_3 (0x00008UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR15_PARAM_4 (0x00010UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR15_PARAM_5 (0x00020UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR15_PARAM_6 (0x00040UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR15_PARAM_7 (0x00080UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR15_PARAM_8 (0x00100UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR15_PARAM_9 (0x00200UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR15_PARAM_10 (0x00400UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR15_PARAM_11 (0x00800UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR15_PARAM_12 (0x01000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR15_PARAM_13 (0x02000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR15_PARAM_14 (0x04000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR15_PARAM_15 (0x08000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR15_PARAM_16 (0x10000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR15_PARAM_17 (0x20000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR15_PARAM_18 (0x40000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR15_PARAM_19 (0x80000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR15_PARAM_20 (0x100000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR15_PARAM_21 (0x200000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR15_PARAM_22 (0x400000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR15_PARAM_23 (0x800000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR15_PARAM_24 (0x1000000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR15_PARAM_25 (0x2000000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR15_PARAM_26 (0x4000000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR15_PARAM_27 (0x8000000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR15_PARAM_28 (0x10000000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR15_PARAM_29 (0x20000000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR15_PARAM_30 (0x40000000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR15_PARAM_31 (0x80000000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_SPE_IER register ********************/ -/*!< C2HMRDYIE configuration */ -#define HSP_SPE_IER_C2HMRDYIE_Pos (0U) +#define HSP_SPE_IER_C2HMRDYIE_Pos (0UL) #define HSP_SPE_IER_C2HMRDYIE_Msk (0x1UL << HSP_SPE_IER_C2HMRDYIE_Pos) /*!< 0x00000001 */ #define HSP_SPE_IER_C2HMRDYIE HSP_SPE_IER_C2HMRDYIE_Msk /*!< C2HMRDYIE (CPU to SPE message ready interrupt enable) */ -/*!< H2CMFREEIE configuration */ -#define HSP_SPE_IER_H2CMFREEIE_Pos (1U) + +#define HSP_SPE_IER_H2CMFREEIE_Pos (1UL) #define HSP_SPE_IER_H2CMFREEIE_Msk (0x1UL << HSP_SPE_IER_H2CMFREEIE_Pos) /*!< 0x00000002 */ #define HSP_SPE_IER_H2CMFREEIE HSP_SPE_IER_H2CMFREEIE_Msk /*!< H2CMFREEIE (SPE to CPU message free interrupt enable) */ /******************** Bit definition for HSP_SPE_ISR register ********************/ -/*!< C2HMRDYF configuration */ -#define HSP_SPE_ISR_C2HMRDYF_Pos (0U) +#define HSP_SPE_ISR_C2HMRDYF_Pos (0UL) #define HSP_SPE_ISR_C2HMRDYF_Msk (0x1UL << HSP_SPE_ISR_C2HMRDYF_Pos) /*!< 0x00000001 */ #define HSP_SPE_ISR_C2HMRDYF HSP_SPE_ISR_C2HMRDYF_Msk /*!< C2HMRDYF (CPU to SPE message box status) */ -/*!< H2CMFREEF configuration */ -#define HSP_SPE_ISR_H2CMFREEF_Pos (1U) + +#define HSP_SPE_ISR_H2CMFREEF_Pos (1UL) #define HSP_SPE_ISR_H2CMFREEF_Msk (0x1UL << HSP_SPE_ISR_H2CMFREEF_Pos) /*!< 0x00000002 */ #define HSP_SPE_ISR_H2CMFREEF HSP_SPE_ISR_H2CMFREEF_Msk /*!< H2CMFREEF (SPE to CPU message box status) */ -/*!< RSTREQF configuration */ -#define HSP_SPE_ISR_RSTREQF_Pos (4U) + +#define HSP_SPE_ISR_RSTREQF_Pos (4UL) #define HSP_SPE_ISR_RSTREQF_Msk (0x1UL << HSP_SPE_ISR_RSTREQF_Pos) /*!< 0x00000010 */ #define HSP_SPE_ISR_RSTREQF HSP_SPE_ISR_RSTREQF_Msk /*!< RSTREQF (HSP reset request) */ -/*!< BUF0EVTF configuration */ -#define HSP_SPE_ISR_BUF0EVTF_Pos (12U) + +#define HSP_SPE_ISR_BUF0EVTF_Pos (12UL) #define HSP_SPE_ISR_BUF0EVTF_Msk (0x1UL << HSP_SPE_ISR_BUF0EVTF_Pos) /*!< 0x00001000 */ #define HSP_SPE_ISR_BUF0EVTF HSP_SPE_ISR_BUF0EVTF_Msk /*!< BUF0EVTF (BUF0 status) */ -/*!< BUF1EVTF configuration */ -#define HSP_SPE_ISR_BUF1EVTF_Pos (13U) + +#define HSP_SPE_ISR_BUF1EVTF_Pos (13UL) #define HSP_SPE_ISR_BUF1EVTF_Msk (0x1UL << HSP_SPE_ISR_BUF1EVTF_Pos) /*!< 0x00002000 */ #define HSP_SPE_ISR_BUF1EVTF HSP_SPE_ISR_BUF1EVTF_Msk /*!< BUF1EVTF (BUF1 status) */ -/*!< BUF2EVTF configuration */ -#define HSP_SPE_ISR_BUF2EVTF_Pos (14U) + +#define HSP_SPE_ISR_BUF2EVTF_Pos (14UL) #define HSP_SPE_ISR_BUF2EVTF_Msk (0x1UL << HSP_SPE_ISR_BUF2EVTF_Pos) /*!< 0x00004000 */ #define HSP_SPE_ISR_BUF2EVTF HSP_SPE_ISR_BUF2EVTF_Msk /*!< BUF2EVTF (BUF2 status) */ -/*!< BUF3EVTF configuration */ -#define HSP_SPE_ISR_BUF3EVTF_Pos (15U) + +#define HSP_SPE_ISR_BUF3EVTF_Pos (15UL) #define HSP_SPE_ISR_BUF3EVTF_Msk (0x1UL << HSP_SPE_ISR_BUF3EVTF_Pos) /*!< 0x00008000 */ #define HSP_SPE_ISR_BUF3EVTF HSP_SPE_ISR_BUF3EVTF_Msk /*!< BUF3EVTF (BUF3 status) */ /******************** Bit definition for HSP_TCUCFGR register ********************/ -/*!< TSKCMP0 configuration */ -#define HSP_TCUCFGR_TSKCMP0_Pos (0U) +#define HSP_TCUCFGR_TSKCMP0_Pos (0UL) #define HSP_TCUCFGR_TSKCMP0_Msk (0x3FUL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x0000003F */ #define HSP_TCUCFGR_TSKCMP0 HSP_TCUCFGR_TSKCMP0_Msk /*!< TSKCMP0[5:0] bits (Task compare 0 (1)) */ #define HSP_TCUCFGR_TSKCMP0_0 (0x01UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000001 */ @@ -12612,12 +13299,12 @@ typedef struct #define HSP_TCUCFGR_TSKCMP0_3 (0x08UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000008 */ #define HSP_TCUCFGR_TSKCMP0_4 (0x10UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000010 */ #define HSP_TCUCFGR_TSKCMP0_5 (0x20UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000020 */ -/*!< TC0EN configuration */ -#define HSP_TCUCFGR_TC0EN_Pos (7U) + +#define HSP_TCUCFGR_TC0EN_Pos (7UL) #define HSP_TCUCFGR_TC0EN_Msk (0x1UL << HSP_TCUCFGR_TC0EN_Pos) /*!< 0x00000080 */ #define HSP_TCUCFGR_TC0EN HSP_TCUCFGR_TC0EN_Msk /*!< TC0EN (Task comparator 0 enable (1)) */ -/*!< TSKCMP1 configuration */ -#define HSP_TCUCFGR_TSKCMP1_Pos (8U) + +#define HSP_TCUCFGR_TSKCMP1_Pos (8UL) #define HSP_TCUCFGR_TSKCMP1_Msk (0x3FUL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00003F00 */ #define HSP_TCUCFGR_TSKCMP1 HSP_TCUCFGR_TSKCMP1_Msk /*!< TSKCMP1[5:0] bits (Task compare 1 (1)) */ #define HSP_TCUCFGR_TSKCMP1_0 (0x01UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00000100 */ @@ -12626,12 +13313,12 @@ typedef struct #define HSP_TCUCFGR_TSKCMP1_3 (0x08UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00000800 */ #define HSP_TCUCFGR_TSKCMP1_4 (0x10UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00001000 */ #define HSP_TCUCFGR_TSKCMP1_5 (0x20UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00002000 */ -/*!< TC1EN configuration */ -#define HSP_TCUCFGR_TC1EN_Pos (15U) + +#define HSP_TCUCFGR_TC1EN_Pos (15UL) #define HSP_TCUCFGR_TC1EN_Msk (0x1UL << HSP_TCUCFGR_TC1EN_Pos) /*!< 0x00008000 */ #define HSP_TCUCFGR_TC1EN HSP_TCUCFGR_TC1EN_Msk /*!< TC1EN (Task comparator 1 enable (1)) */ -/*!< TSKCMP2 configuration */ -#define HSP_TCUCFGR_TSKCMP2_Pos (16U) + +#define HSP_TCUCFGR_TSKCMP2_Pos (16UL) #define HSP_TCUCFGR_TSKCMP2_Msk (0x3FUL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x003F0000 */ #define HSP_TCUCFGR_TSKCMP2 HSP_TCUCFGR_TSKCMP2_Msk /*!< TSKCMP2[5:0] bits (Task compare 2 (1)) */ #define HSP_TCUCFGR_TSKCMP2_0 (0x01UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00010000 */ @@ -12640,12 +13327,12 @@ typedef struct #define HSP_TCUCFGR_TSKCMP2_3 (0x08UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00080000 */ #define HSP_TCUCFGR_TSKCMP2_4 (0x10UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00100000 */ #define HSP_TCUCFGR_TSKCMP2_5 (0x20UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00200000 */ -/*!< TC2EN configuration */ -#define HSP_TCUCFGR_TC2EN_Pos (23U) + +#define HSP_TCUCFGR_TC2EN_Pos (23UL) #define HSP_TCUCFGR_TC2EN_Msk (0x1UL << HSP_TCUCFGR_TC2EN_Pos) /*!< 0x00800000 */ #define HSP_TCUCFGR_TC2EN HSP_TCUCFGR_TC2EN_Msk /*!< TC2EN (Task comparator 2 enable (1)) */ -/*!< TSKCMP3 configuration */ -#define HSP_TCUCFGR_TSKCMP3_Pos (24U) + +#define HSP_TCUCFGR_TSKCMP3_Pos (24UL) #define HSP_TCUCFGR_TSKCMP3_Msk (0x3FUL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x3F000000 */ #define HSP_TCUCFGR_TSKCMP3 HSP_TCUCFGR_TSKCMP3_Msk /*!< TSKCMP3[5:0] bits (Task compare 3 (1)) */ #define HSP_TCUCFGR_TSKCMP3_0 (0x01UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x01000000 */ @@ -12654,47 +13341,33 @@ typedef struct #define HSP_TCUCFGR_TSKCMP3_3 (0x08UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x08000000 */ #define HSP_TCUCFGR_TSKCMP3_4 (0x10UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x10000000 */ #define HSP_TCUCFGR_TSKCMP3_5 (0x20UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x20000000 */ -/*!< TC3EN configuration */ -#define HSP_TCUCFGR_TC3EN_Pos (31U) + +#define HSP_TCUCFGR_TC3EN_Pos (31UL) #define HSP_TCUCFGR_TC3EN_Msk (0x1UL << HSP_TCUCFGR_TC3EN_Pos) /*!< 0x80000000 */ #define HSP_TCUCFGR_TC3EN HSP_TCUCFGR_TC3EN_Msk /*!< TC3EN (Task comparator 3 enable ) */ /******************** Bit definition for HSP_TOVLPCR register ********************/ -/*!< TOVLPEN configuration */ -#define HSP_TOVLPCR_TOVLPEN_Pos (0U) +#define HSP_TOVLPCR_TOVLPEN_Pos (0UL) #define HSP_TOVLPCR_TOVLPEN_Msk (0x1UL << HSP_TOVLPCR_TOVLPEN_Pos) /*!< 0x00000001 */ #define HSP_TOVLPCR_TOVLPEN HSP_TOVLPCR_TOVLPEN_Msk /*!< TOVLPEN (Task overlap enable (1)) */ -/*!< LTNB configuration */ -#define HSP_TOVLPCR_LTNB_Pos (8U) + +#define HSP_TOVLPCR_LTNB_Pos (8UL) #define HSP_TOVLPCR_LTNB_Msk (0x3FUL << HSP_TOVLPCR_LTNB_Pos) /*!< 0x00003F00 */ #define HSP_TOVLPCR_LTNB HSP_TOVLPCR_LTNB_Msk /*!< LTNB[5:0] bits (Lower task number value (1)) */ -#define HSP_TOVLPCR_LTNB_0 (0x01UL << HSP_TOVLPCR_LTNB_Pos) /*!< 0x00000100 */ -#define HSP_TOVLPCR_LTNB_1 (0x02UL << HSP_TOVLPCR_LTNB_Pos) /*!< 0x00000200 */ -#define HSP_TOVLPCR_LTNB_2 (0x04UL << HSP_TOVLPCR_LTNB_Pos) /*!< 0x00000400 */ -#define HSP_TOVLPCR_LTNB_3 (0x08UL << HSP_TOVLPCR_LTNB_Pos) /*!< 0x00000800 */ -#define HSP_TOVLPCR_LTNB_4 (0x10UL << HSP_TOVLPCR_LTNB_Pos) /*!< 0x00001000 */ -#define HSP_TOVLPCR_LTNB_5 (0x20UL << HSP_TOVLPCR_LTNB_Pos) /*!< 0x00002000 */ -/*!< HTNB configuration */ -#define HSP_TOVLPCR_HTNB_Pos (16U) + +#define HSP_TOVLPCR_HTNB_Pos (16UL) #define HSP_TOVLPCR_HTNB_Msk (0x3FUL << HSP_TOVLPCR_HTNB_Pos) /*!< 0x003F0000 */ #define HSP_TOVLPCR_HTNB HSP_TOVLPCR_HTNB_Msk /*!< HTNB[5:0] bits (Higher task number value ) */ -#define HSP_TOVLPCR_HTNB_0 (0x01UL << HSP_TOVLPCR_HTNB_Pos) /*!< 0x00010000 */ -#define HSP_TOVLPCR_HTNB_1 (0x02UL << HSP_TOVLPCR_HTNB_Pos) /*!< 0x00020000 */ -#define HSP_TOVLPCR_HTNB_2 (0x04UL << HSP_TOVLPCR_HTNB_Pos) /*!< 0x00040000 */ -#define HSP_TOVLPCR_HTNB_3 (0x08UL << HSP_TOVLPCR_HTNB_Pos) /*!< 0x00080000 */ -#define HSP_TOVLPCR_HTNB_4 (0x10UL << HSP_TOVLPCR_HTNB_Pos) /*!< 0x00100000 */ -#define HSP_TOVLPCR_HTNB_5 (0x20UL << HSP_TOVLPCR_HTNB_Pos) /*!< 0x00200000 */ /******************** Bit definition for HSP_SNPR register ********************/ -/*!< SNPSELA configuration */ -#define HSP_SNPR_SNPSELA_Pos (0U) +#define HSP_SNPR_SNPSELA_Pos (0UL) #define HSP_SNPR_SNPSELA_Msk (0x7UL << HSP_SNPR_SNPSELA_Pos) /*!< 0x00000007 */ #define HSP_SNPR_SNPSELA HSP_SNPR_SNPSELA_Msk /*!< SNPSELA[2:0] bits (Snoop group A signal selection) */ #define HSP_SNPR_SNPSELA_0 (0x1UL << HSP_SNPR_SNPSELA_Pos) /*!< 0x00000001 */ #define HSP_SNPR_SNPSELA_1 (0x2UL << HSP_SNPR_SNPSELA_Pos) /*!< 0x00000002 */ #define HSP_SNPR_SNPSELA_2 (0x4UL << HSP_SNPR_SNPSELA_Pos) /*!< 0x00000004 */ -/*!< SNPSELB configuration */ -#define HSP_SNPR_SNPSELB_Pos (4U) + +#define HSP_SNPR_SNPSELB_Pos (4UL) #define HSP_SNPR_SNPSELB_Msk (0x7UL << HSP_SNPR_SNPSELB_Pos) /*!< 0x00000070 */ #define HSP_SNPR_SNPSELB HSP_SNPR_SNPSELB_Msk /*!< SNPSELB[2:0] bits (Snoop group B signal selection) */ #define HSP_SNPR_SNPSELB_0 (0x1UL << HSP_SNPR_SNPSELB_Pos) /*!< 0x00000010 */ @@ -12702,116 +13375,49 @@ typedef struct #define HSP_SNPR_SNPSELB_2 (0x4UL << HSP_SNPR_SNPSELB_Pos) /*!< 0x00000040 */ /******************** Bit definition for HSP_CCNTR register ********************/ -/*!< CCNTR configuration */ -#define HSP_CCNTR_CCNTR_Pos (0U) +#define HSP_CCNTR_CCNTR_Pos (0UL) #define HSP_CCNTR_CCNTR_Msk (0xFFFFFFFFUL << HSP_CCNTR_CCNTR_Pos) /*!< 0xFFFFFFFF */ #define HSP_CCNTR_CCNTR HSP_CCNTR_CCNTR_Msk /*!< CCNTR[31:0] bits (Conflict counter) */ -#define HSP_CCNTR_CCNTR_0 (0x00001UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00000001 */ -#define HSP_CCNTR_CCNTR_1 (0x00002UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00000002 */ -#define HSP_CCNTR_CCNTR_2 (0x00004UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00000004 */ -#define HSP_CCNTR_CCNTR_3 (0x00008UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00000008 */ -#define HSP_CCNTR_CCNTR_4 (0x00010UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00000010 */ -#define HSP_CCNTR_CCNTR_5 (0x00020UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00000020 */ -#define HSP_CCNTR_CCNTR_6 (0x00040UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00000040 */ -#define HSP_CCNTR_CCNTR_7 (0x00080UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00000080 */ -#define HSP_CCNTR_CCNTR_8 (0x00100UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00000100 */ -#define HSP_CCNTR_CCNTR_9 (0x00200UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00000200 */ -#define HSP_CCNTR_CCNTR_10 (0x00400UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00000400 */ -#define HSP_CCNTR_CCNTR_11 (0x00800UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00000800 */ -#define HSP_CCNTR_CCNTR_12 (0x01000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00001000 */ -#define HSP_CCNTR_CCNTR_13 (0x02000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00002000 */ -#define HSP_CCNTR_CCNTR_14 (0x04000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00004000 */ -#define HSP_CCNTR_CCNTR_15 (0x08000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00008000 */ -#define HSP_CCNTR_CCNTR_16 (0x10000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00010000 */ -#define HSP_CCNTR_CCNTR_17 (0x20000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00020000 */ -#define HSP_CCNTR_CCNTR_18 (0x40000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00040000 */ -#define HSP_CCNTR_CCNTR_19 (0x80000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00080000 */ -#define HSP_CCNTR_CCNTR_20 (0x100000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00100000 */ -#define HSP_CCNTR_CCNTR_21 (0x200000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00200000 */ -#define HSP_CCNTR_CCNTR_22 (0x400000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00400000 */ -#define HSP_CCNTR_CCNTR_23 (0x800000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00800000 */ -#define HSP_CCNTR_CCNTR_24 (0x1000000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x01000000 */ -#define HSP_CCNTR_CCNTR_25 (0x2000000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x02000000 */ -#define HSP_CCNTR_CCNTR_26 (0x4000000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x04000000 */ -#define HSP_CCNTR_CCNTR_27 (0x8000000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x08000000 */ -#define HSP_CCNTR_CCNTR_28 (0x10000000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x10000000 */ -#define HSP_CCNTR_CCNTR_29 (0x20000000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x20000000 */ -#define HSP_CCNTR_CCNTR_30 (0x40000000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x40000000 */ -#define HSP_CCNTR_CCNTR_31 (0x80000000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for HSP_CAPDR register ********************/ -/*!< TSTAMP configuration */ -#define HSP_CAPDR_TSTAMP_Pos (0U) -#define HSP_CAPDR_TSTAMP_Msk (0x3FFFUL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00003FFF */ -#define HSP_CAPDR_TSTAMP HSP_CAPDR_TSTAMP_Msk /*!< TSTAMP[13:0] bits (Time-stamp value) */ -#define HSP_CAPDR_TSTAMP_0 (0x001UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00000001 */ -#define HSP_CAPDR_TSTAMP_1 (0x002UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00000002 */ -#define HSP_CAPDR_TSTAMP_2 (0x004UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00000004 */ -#define HSP_CAPDR_TSTAMP_3 (0x008UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00000008 */ -#define HSP_CAPDR_TSTAMP_4 (0x010UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00000010 */ -#define HSP_CAPDR_TSTAMP_5 (0x020UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00000020 */ -#define HSP_CAPDR_TSTAMP_6 (0x040UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00000040 */ -#define HSP_CAPDR_TSTAMP_7 (0x080UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00000080 */ -#define HSP_CAPDR_TSTAMP_8 (0x100UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00000100 */ -#define HSP_CAPDR_TSTAMP_9 (0x200UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00000200 */ -#define HSP_CAPDR_TSTAMP_10 (0x400UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00000400 */ -#define HSP_CAPDR_TSTAMP_11 (0x800UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00000800 */ -#define HSP_CAPDR_TSTAMP_12 (0x1000UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00001000 */ -#define HSP_CAPDR_TSTAMP_13 (0x2000UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00002000 */ -/*!< IFHIST configuration */ -#define HSP_CAPDR_IFHIST_Pos (14U) -#define HSP_CAPDR_IFHIST_Msk (0xFFUL << HSP_CAPDR_IFHIST_Pos) /*!< 0x003FC000 */ -#define HSP_CAPDR_IFHIST HSP_CAPDR_IFHIST_Msk /*!< IFHIST[7:0] bits (IF condition history) */ -#define HSP_CAPDR_IFHIST_0 (0x001UL << HSP_CAPDR_IFHIST_Pos) /*!< 0x00004000 */ -#define HSP_CAPDR_IFHIST_1 (0x002UL << HSP_CAPDR_IFHIST_Pos) /*!< 0x00008000 */ -#define HSP_CAPDR_IFHIST_2 (0x004UL << HSP_CAPDR_IFHIST_Pos) /*!< 0x00010000 */ -#define HSP_CAPDR_IFHIST_3 (0x008UL << HSP_CAPDR_IFHIST_Pos) /*!< 0x00020000 */ -#define HSP_CAPDR_IFHIST_4 (0x010UL << HSP_CAPDR_IFHIST_Pos) /*!< 0x00040000 */ -#define HSP_CAPDR_IFHIST_5 (0x020UL << HSP_CAPDR_IFHIST_Pos) /*!< 0x00080000 */ -#define HSP_CAPDR_IFHIST_6 (0x040UL << HSP_CAPDR_IFHIST_Pos) /*!< 0x00100000 */ -#define HSP_CAPDR_IFHIST_7 (0x080UL << HSP_CAPDR_IFHIST_Pos) /*!< 0x00200000 */ -/*!< IFCNT configuration */ -#define HSP_CAPDR_IFCNT_Pos (22U) -#define HSP_CAPDR_IFCNT_Msk (0xFUL << HSP_CAPDR_IFCNT_Pos) /*!< 0x03C00000 */ -#define HSP_CAPDR_IFCNT HSP_CAPDR_IFCNT_Msk /*!< IFCNT[3:0] bits (IF instruction counter) */ -#define HSP_CAPDR_IFCNT_0 (0x01UL << HSP_CAPDR_IFCNT_Pos) /*!< 0x00400000 */ -#define HSP_CAPDR_IFCNT_1 (0x02UL << HSP_CAPDR_IFCNT_Pos) /*!< 0x00800000 */ -#define HSP_CAPDR_IFCNT_2 (0x04UL << HSP_CAPDR_IFCNT_Pos) /*!< 0x01000000 */ -#define HSP_CAPDR_IFCNT_3 (0x08UL << HSP_CAPDR_IFCNT_Pos) /*!< 0x02000000 */ -/*!< TSKNB configuration */ -#define HSP_CAPDR_TSKNB_Pos (26U) -#define HSP_CAPDR_TSKNB_Msk (0x3FUL << HSP_CAPDR_TSKNB_Pos) /*!< 0xFC000000 */ -#define HSP_CAPDR_TSKNB HSP_CAPDR_TSKNB_Msk /*!< TSKNB[5:0] bits (Last captured task number) */ -#define HSP_CAPDR_TSKNB_0 (0x01UL << HSP_CAPDR_TSKNB_Pos) /*!< 0x04000000 */ -#define HSP_CAPDR_TSKNB_1 (0x02UL << HSP_CAPDR_TSKNB_Pos) /*!< 0x08000000 */ -#define HSP_CAPDR_TSKNB_2 (0x04UL << HSP_CAPDR_TSKNB_Pos) /*!< 0x10000000 */ -#define HSP_CAPDR_TSKNB_3 (0x08UL << HSP_CAPDR_TSKNB_Pos) /*!< 0x20000000 */ -#define HSP_CAPDR_TSKNB_4 (0x10UL << HSP_CAPDR_TSKNB_Pos) /*!< 0x40000000 */ -#define HSP_CAPDR_TSKNB_5 (0x20UL << HSP_CAPDR_TSKNB_Pos) /*!< 0x80000000 */ -/*!< PFCTNB configuration */ -#define HSP_CAPDR_PFCTNB_Pos (16U) -#define HSP_CAPDR_PFCTNB_Msk (0x3FUL << HSP_CAPDR_PFCTNB_Pos) /*!< 0x003F0000 */ -#define HSP_CAPDR_PFCTNB HSP_CAPDR_PFCTNB_Msk /*!< PFCTNB[5:0] bits (Last captured processing function number) */ -#define HSP_CAPDR_PFCTNB_0 (0x01UL << HSP_CAPDR_PFCTNB_Pos) /*!< 0x00010000 */ -#define HSP_CAPDR_PFCTNB_1 (0x02UL << HSP_CAPDR_PFCTNB_Pos) /*!< 0x00020000 */ -#define HSP_CAPDR_PFCTNB_2 (0x04UL << HSP_CAPDR_PFCTNB_Pos) /*!< 0x00040000 */ -#define HSP_CAPDR_PFCTNB_3 (0x08UL << HSP_CAPDR_PFCTNB_Pos) /*!< 0x00080000 */ -#define HSP_CAPDR_PFCTNB_4 (0x10UL << HSP_CAPDR_PFCTNB_Pos) /*!< 0x00100000 */ -#define HSP_CAPDR_PFCTNB_5 (0x20UL << HSP_CAPDR_PFCTNB_Pos) /*!< 0x00200000 */ + +/****************** Bit definition for HSP_CAPDR register *******************/ +#define HSP_CAPDR_TSTAMP_Pos (0UL) +#define HSP_CAPDR_TSTAMP_Msk (0x3FFFUL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00003FFF */ +#define HSP_CAPDR_TSTAMP HSP_CAPDR_TSTAMP_Msk /*!< Time-stamp value */ +#define HSP_CAPDR_IFHIST_Pos (14UL) +#define HSP_CAPDR_IFHIST_Msk (0xFFUL << HSP_CAPDR_IFHIST_Pos) /*!< 0x003FC000 */ +#define HSP_CAPDR_IFHIST HSP_CAPDR_IFHIST_Msk /*!< IF condition history */ +#define HSP_CAPDR_IFCNT_Pos (22UL) +#define HSP_CAPDR_IFCNT_Msk (0xFUL << HSP_CAPDR_IFCNT_Pos) /*!< 0x03C00000 */ +#define HSP_CAPDR_IFCNT HSP_CAPDR_IFCNT_Msk /*!< IF instruction counter */ +#define HSP_CAPDR_TSKNB_Pos (26UL) +#define HSP_CAPDR_TSKNB_Msk (0x3FUL << HSP_CAPDR_TSKNB_Pos) /*!< 0xFC000000 */ +#define HSP_CAPDR_TSKNB HSP_CAPDR_TSKNB_Msk /*!< Last captured task number */ + +#define HSP_CAPDR_ALT_IFHIST_Pos (0UL) +#define HSP_CAPDR_ALT_IFHIST_Msk (0x7FFFUL << HSP_CAPDR_ALT_IFHIST_Pos) /*!< 0x00007FFF */ +#define HSP_CAPDR_ALT_IFHIST HSP_CAPDR_IFHIST_Msk /*!< IF condition history */ +#define HSP_CAPDR_ALT_PFCTNB_Pos (16UL) +#define HSP_CAPDR_ALT_PFCTNB_Msk (0x3FUL << HSP_CAPDR_ALT_PFCTNB_Pos) /*!< 0x0003F0000 */ +#define HSP_CAPDR_ALT_PFCTNB HSP_CAPDR_TSTAMP_Msk /*!< Processing Function Number */ +#define HSP_CAPDR_ALT_IFCNT_Pos (22UL) +#define HSP_CAPDR_ALT_IFCNT_Msk (0xFUL << HSP_CAPDR_ALT_IFCNT_Pos) /*!< 0x03C00000 */ +#define HSP_CAPDR_ALT_IFCNT HSP_CAPDR_IFCNT_Msk /*!< IF instruction counter */ +#define HSP_CAPDR_ALT_TSKNB_Pos (26UL) +#define HSP_CAPDR_ALT_TSKNB_Msk (0x3FUL << HSP_CAPDR_ALT_TSKNB_Pos) /*!< 0xFC000000 */ +#define HSP_CAPDR_ALT_TSKNB HSP_CAPDR_TSKNB_Msk /*!< Last captured task number */ /******************** Bit definition for HSP_CAPCR register ********************/ -/*!< CAPMOD configuration */ -#define HSP_CAPCR_CAPMOD_Pos (0U) +#define HSP_CAPCR_CAPMOD_Pos (0UL) #define HSP_CAPCR_CAPMOD_Msk (0x3UL << HSP_CAPCR_CAPMOD_Pos) /*!< 0x00000003 */ #define HSP_CAPCR_CAPMOD HSP_CAPCR_CAPMOD_Msk /*!< CAPMOD[1:0] bits (Capture mode ) */ #define HSP_CAPCR_CAPMOD_0 (0x1UL << HSP_CAPCR_CAPMOD_Pos) /*!< 0x00000001 */ #define HSP_CAPCR_CAPMOD_1 (0x2UL << HSP_CAPCR_CAPMOD_Pos) /*!< 0x00000002 */ -/*!< FRCNTEN configuration */ -#define HSP_CAPCR_FRCNTEN_Pos (2U) + +#define HSP_CAPCR_FRCNTEN_Pos (2UL) #define HSP_CAPCR_FRCNTEN_Msk (0x1UL << HSP_CAPCR_FRCNTEN_Pos) /*!< 0x00000004 */ #define HSP_CAPCR_FRCNTEN HSP_CAPCR_FRCNTEN_Msk /*!< FRCNTEN (Free-running counter enable ) */ -/*!< PRESC configuration */ -#define HSP_CAPCR_PRESC_Pos (4U) + +#define HSP_CAPCR_PRESC_Pos (4UL) #define HSP_CAPCR_PRESC_Msk (0x1FUL << HSP_CAPCR_PRESC_Pos) /*!< 0x000001F0 */ #define HSP_CAPCR_PRESC HSP_CAPCR_PRESC_Msk /*!< PRESC[4:0] bits (Time-stamp prescaler value ) */ #define HSP_CAPCR_PRESC_0 (0x01UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000010 */ @@ -12819,174 +13425,171 @@ typedef struct #define HSP_CAPCR_PRESC_2 (0x04UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000040 */ #define HSP_CAPCR_PRESC_3 (0x08UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000080 */ #define HSP_CAPCR_PRESC_4 (0x10UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000100 */ -/*!< TSKFLT configuration */ -#define HSP_CAPCR_TSKFLT_Pos (12U) + +#define HSP_CAPCR_TSKFLT_Pos (12UL) #define HSP_CAPCR_TSKFLT_Msk (0x1UL << HSP_CAPCR_TSKFLT_Pos) /*!< 0x00001000 */ #define HSP_CAPCR_TSKFLT HSP_CAPCR_TSKFLT_Msk /*!< TSKFLT (Task filter enable (1)) */ -/*!< CCNTREN configuration */ -#define HSP_CAPCR_CCNTREN_Pos (16U) + +#define HSP_CAPCR_CCNTREN_Pos (16UL) #define HSP_CAPCR_CCNTREN_Msk (0x1UL << HSP_CAPCR_CCNTREN_Pos) /*!< 0x00010000 */ #define HSP_CAPCR_CCNTREN HSP_CAPCR_CCNTREN_Msk /*!< CCNTREN (Conflict counter enable ) */ /******************** Bit definition for HSP_ERR_IER register ********************/ -/*!< TRGIOVRIE configuration */ -#define HSP_ERR_IER_TRGIOVRIE_Pos (8U) +#define HSP_ERR_IER_TRGIOVRIE_Pos (8UL) #define HSP_ERR_IER_TRGIOVRIE_Msk (0x1UL << HSP_ERR_IER_TRGIOVRIE_Pos) /*!< 0x00000100 */ #define HSP_ERR_IER_TRGIOVRIE HSP_ERR_IER_TRGIOVRIE_Msk /*!< TRGIOVRIE (TRGITF overrun interrupt enable) */ -/*!< B0ERRIE configuration */ -#define HSP_ERR_IER_B0ERRIE_Pos (12U) + +#define HSP_ERR_IER_B0ERRIE_Pos (12UL) #define HSP_ERR_IER_B0ERRIE_Msk (0x1UL << HSP_ERR_IER_B0ERRIE_Pos) /*!< 0x00001000 */ #define HSP_ERR_IER_B0ERRIE HSP_ERR_IER_B0ERRIE_Msk /*!< B0ERRIE (H2CBUFF0 underrun or C2HBUFF0 overrun interrupt enable) */ -/*!< B1ERRIE configuration */ -#define HSP_ERR_IER_B1ERRIE_Pos (13U) + +#define HSP_ERR_IER_B1ERRIE_Pos (13UL) #define HSP_ERR_IER_B1ERRIE_Msk (0x1UL << HSP_ERR_IER_B1ERRIE_Pos) /*!< 0x00002000 */ #define HSP_ERR_IER_B1ERRIE HSP_ERR_IER_B1ERRIE_Msk /*!< B1ERRIE (H2CBUFF1 underrun or C2HBUFF1 overrun interrupt enable) */ -/*!< B2ERRIE configuration */ -#define HSP_ERR_IER_B2ERRIE_Pos (14U) + +#define HSP_ERR_IER_B2ERRIE_Pos (14UL) #define HSP_ERR_IER_B2ERRIE_Msk (0x1UL << HSP_ERR_IER_B2ERRIE_Pos) /*!< 0x00004000 */ #define HSP_ERR_IER_B2ERRIE HSP_ERR_IER_B2ERRIE_Msk /*!< B2ERRIE (H2CBUFF2 underrun or C2HBUFF2 overrun interrupt enable) */ -/*!< B3ERRIE configuration */ -#define HSP_ERR_IER_B3ERRIE_Pos (15U) + +#define HSP_ERR_IER_B3ERRIE_Pos (15UL) #define HSP_ERR_IER_B3ERRIE_Msk (0x1UL << HSP_ERR_IER_B3ERRIE_Pos) /*!< 0x00008000 */ #define HSP_ERR_IER_B3ERRIE HSP_ERR_IER_B3ERRIE_Msk /*!< B3ERRIE (H2CBUFF3 underrun or C2HBUFF3 overrun interrupt enable) */ -/*!< CAPOVRIE configuration */ -#define HSP_ERR_IER_CAPOVRIE_Pos (16U) + +#define HSP_ERR_IER_CAPOVRIE_Pos (16UL) #define HSP_ERR_IER_CAPOVRIE_Msk (0x1UL << HSP_ERR_IER_CAPOVRIE_Pos) /*!< 0x00010000 */ #define HSP_ERR_IER_CAPOVRIE HSP_ERR_IER_CAPOVRIE_Msk /*!< CAPOVRIE (Capture register overrun interrupt enable) */ -/*!< FWERRIE configuration */ -#define HSP_ERR_IER_FWERRIE_Pos (17U) + +#define HSP_ERR_IER_FWERRIE_Pos (17UL) #define HSP_ERR_IER_FWERRIE_Msk (0x1UL << HSP_ERR_IER_FWERRIE_Pos) /*!< 0x00020000 */ #define HSP_ERR_IER_FWERRIE HSP_ERR_IER_FWERRIE_Msk /*!< FWERRIE (Firmware error interrupt enable) */ -/*!< SCHERRIE configuration */ -#define HSP_ERR_IER_SCHERRIE_Pos (18U) + +#define HSP_ERR_IER_SCHERRIE_Pos (18UL) #define HSP_ERR_IER_SCHERRIE_Msk (0x1UL << HSP_ERR_IER_SCHERRIE_Pos) /*!< 0x00040000 */ #define HSP_ERR_IER_SCHERRIE HSP_ERR_IER_SCHERRIE_Msk /*!< SCHERRIE (Scheduler error interrupt enable) */ -/*!< BKINIE configuration */ -#define HSP_ERR_IER_BKINIE_Pos (19U) + +#define HSP_ERR_IER_BKINIE_Pos (19UL) #define HSP_ERR_IER_BKINIE_Msk (0x1UL << HSP_ERR_IER_BKINIE_Pos) /*!< 0x00080000 */ #define HSP_ERR_IER_BKINIE HSP_ERR_IER_BKINIE_Msk /*!< BKINIE (Break input interrupt enable) */ -/*!< HDEGOVRIE configuration */ -#define HSP_ERR_IER_HDEGOVRIE_Pos (20U) + +#define HSP_ERR_IER_HDEGOVRIE_Pos (20UL) #define HSP_ERR_IER_HDEGOVRIE_Msk (0x1UL << HSP_ERR_IER_HDEGOVRIE_Pos) /*!< 0x00100000 */ #define HSP_ERR_IER_HDEGOVRIE HSP_ERR_IER_HDEGOVRIE_Msk /*!< HDEGOVRIE (SPE event overrun interrupt enable) */ -/*!< OPCOERRIE configuration */ -#define HSP_ERR_IER_OPCOERRIE_Pos (22U) + +#define HSP_ERR_IER_OPCOERRIE_Pos (22UL) #define HSP_ERR_IER_OPCOERRIE_Msk (0x1UL << HSP_ERR_IER_OPCOERRIE_Pos) /*!< 0x00400000 */ #define HSP_ERR_IER_OPCOERRIE HSP_ERR_IER_OPCOERRIE_Msk /*!< OPCOERRIE (Invalid Op. code error interrupt enable) */ -/*!< ACCERRIE configuration */ -#define HSP_ERR_IER_ACCERRIE_Pos (23U) + +#define HSP_ERR_IER_ACCERRIE_Pos (23UL) #define HSP_ERR_IER_ACCERRIE_Msk (0x1UL << HSP_ERR_IER_ACCERRIE_Pos) /*!< 0x00800000 */ #define HSP_ERR_IER_ACCERRIE HSP_ERR_IER_ACCERRIE_Msk /*!< ACCERRIE (SPE access error interrupt enable) */ -/*!< UDFIE configuration */ -#define HSP_ERR_IER_UDFIE_Pos (24U) + +#define HSP_ERR_IER_UDFIE_Pos (24UL) #define HSP_ERR_IER_UDFIE_Msk (0x1UL << HSP_ERR_IER_UDFIE_Pos) /*!< 0x01000000 */ #define HSP_ERR_IER_UDFIE HSP_ERR_IER_UDFIE_Msk /*!< UDFIE (FPU Underflow exception interrupt enable) */ -/*!< OVFIE configuration */ -#define HSP_ERR_IER_OVFIE_Pos (25U) + +#define HSP_ERR_IER_OVFIE_Pos (25UL) #define HSP_ERR_IER_OVFIE_Msk (0x1UL << HSP_ERR_IER_OVFIE_Pos) /*!< 0x02000000 */ #define HSP_ERR_IER_OVFIE HSP_ERR_IER_OVFIE_Msk /*!< OVFIE (FPU Overflow exception interrupt enable) */ -/*!< DBZIE configuration */ -#define HSP_ERR_IER_DBZIE_Pos (26U) + +#define HSP_ERR_IER_DBZIE_Pos (26UL) #define HSP_ERR_IER_DBZIE_Msk (0x1UL << HSP_ERR_IER_DBZIE_Pos) /*!< 0x04000000 */ #define HSP_ERR_IER_DBZIE HSP_ERR_IER_DBZIE_Msk /*!< DBZIE (FPU division-by-zero exception interrupt enable) */ -/*!< INVIE configuration */ -#define HSP_ERR_IER_INVIE_Pos (27U) + +#define HSP_ERR_IER_INVIE_Pos (27UL) #define HSP_ERR_IER_INVIE_Msk (0x1UL << HSP_ERR_IER_INVIE_Pos) /*!< 0x08000000 */ #define HSP_ERR_IER_INVIE HSP_ERR_IER_INVIE_Msk /*!< INVIE (FPU Invalid exception interrupt enable) */ -/*!< DENORMIE configuration */ -#define HSP_ERR_IER_DENORMIE_Pos (28U) + +#define HSP_ERR_IER_DENORMIE_Pos (28UL) #define HSP_ERR_IER_DENORMIE_Msk (0x1UL << HSP_ERR_IER_DENORMIE_Pos) /*!< 0x10000000 */ #define HSP_ERR_IER_DENORMIE HSP_ERR_IER_DENORMIE_Msk /*!< DENORMIE (FPU denormal interrupt enable) */ /******************** Bit definition for HSP_EVT_IER register ********************/ -/*!< H2CMRDYIE configuration */ -#define HSP_EVT_IER_H2CMRDYIE_Pos (0U) +#define HSP_EVT_IER_H2CMRDYIE_Pos (0UL) #define HSP_EVT_IER_H2CMRDYIE_Msk (0x1UL << HSP_EVT_IER_H2CMRDYIE_Pos) /*!< 0x00000001 */ #define HSP_EVT_IER_H2CMRDYIE HSP_EVT_IER_H2CMRDYIE_Msk /*!< H2CMRDYIE (HSP to CPU message ready interrupt enable) */ -/*!< C2HMFREEIE configuration */ -#define HSP_EVT_IER_C2HMFREEIE_Pos (1U) + +#define HSP_EVT_IER_C2HMFREEIE_Pos (1UL) #define HSP_EVT_IER_C2HMFREEIE_Msk (0x1UL << HSP_EVT_IER_C2HMFREEIE_Pos) /*!< 0x00000002 */ #define HSP_EVT_IER_C2HMFREEIE HSP_EVT_IER_C2HMFREEIE_Msk /*!< C2HMFREEIE (CPU to HSP message box free interrupt enable) */ -/*!< DCDONEIE configuration */ -#define HSP_EVT_IER_DCDONEIE_Pos (2U) + +#define HSP_EVT_IER_DCDONEIE_Pos (2UL) #define HSP_EVT_IER_DCDONEIE_Msk (0x1UL << HSP_EVT_IER_DCDONEIE_Pos) /*!< 0x00000004 */ #define HSP_EVT_IER_DCDONEIE HSP_EVT_IER_DCDONEIE_Msk /*!< DCDONEIE (Direct command done interrupt enable) */ -/*!< CAPRDYIE configuration */ -#define HSP_EVT_IER_CAPRDYIE_Pos (4U) + +#define HSP_EVT_IER_CAPRDYIE_Pos (4UL) #define HSP_EVT_IER_CAPRDYIE_Msk (0x1UL << HSP_EVT_IER_CAPRDYIE_Pos) /*!< 0x00000010 */ #define HSP_EVT_IER_CAPRDYIE HSP_EVT_IER_CAPRDYIE_Msk /*!< CAPRDYIE (Capture buffer data ready interrupt enable) */ -/*!< CDEGRDYIE configuration */ -#define HSP_EVT_IER_CDEGRDYIE_Pos (7U) + +#define HSP_EVT_IER_CDEGRDYIE_Pos (7UL) #define HSP_EVT_IER_CDEGRDYIE_Msk (0x1UL << HSP_EVT_IER_CDEGRDYIE_Pos) /*!< 0x00000080 */ #define HSP_EVT_IER_CDEGRDYIE HSP_EVT_IER_CDEGRDYIE_Msk /*!< CDEGRDYIE (CPU Dedicated event generator ready interrupt enable) */ -/*!< SOFWFEIE configuration */ -#define HSP_EVT_IER_SOFWFEIE_Pos (8U) + +#define HSP_EVT_IER_SOFWFEIE_Pos (8UL) #define HSP_EVT_IER_SOFWFEIE_Msk (0x1UL << HSP_EVT_IER_SOFWFEIE_Pos) /*!< 0x00000100 */ #define HSP_EVT_IER_SOFWFEIE HSP_EVT_IER_SOFWFEIE_Msk /*!< SOFWFEIE (Start of WFE interrupt enable) */ -/*!< EOFWFEIE configuration */ -#define HSP_EVT_IER_EOFWFEIE_Pos (9U) + +#define HSP_EVT_IER_EOFWFEIE_Pos (9UL) #define HSP_EVT_IER_EOFWFEIE_Msk (0x1UL << HSP_EVT_IER_EOFWFEIE_Pos) /*!< 0x00000200 */ #define HSP_EVT_IER_EOFWFEIE HSP_EVT_IER_EOFWFEIE_Msk /*!< EOFWFEIE (End of WFE interrupt enable) */ -/*!< B0EVTIE configuration */ -#define HSP_EVT_IER_B0EVTIE_Pos (12U) + +#define HSP_EVT_IER_B0EVTIE_Pos (12UL) #define HSP_EVT_IER_B0EVTIE_Msk (0x1UL << HSP_EVT_IER_B0EVTIE_Pos) /*!< 0x00001000 */ #define HSP_EVT_IER_B0EVTIE HSP_EVT_IER_B0EVTIE_Msk /*!< B0EVTIE (BUFF0 event interrupt enable) */ -/*!< B1EVTIE configuration */ -#define HSP_EVT_IER_B1EVTIE_Pos (13U) + +#define HSP_EVT_IER_B1EVTIE_Pos (13UL) #define HSP_EVT_IER_B1EVTIE_Msk (0x1UL << HSP_EVT_IER_B1EVTIE_Pos) /*!< 0x00002000 */ #define HSP_EVT_IER_B1EVTIE HSP_EVT_IER_B1EVTIE_Msk /*!< B1EVTIE (BUFF1 event interrupt enable) */ -/*!< B2EVTIE configuration */ -#define HSP_EVT_IER_B2EVTIE_Pos (14U) + +#define HSP_EVT_IER_B2EVTIE_Pos (14UL) #define HSP_EVT_IER_B2EVTIE_Msk (0x1UL << HSP_EVT_IER_B2EVTIE_Pos) /*!< 0x00004000 */ #define HSP_EVT_IER_B2EVTIE HSP_EVT_IER_B2EVTIE_Msk /*!< B2EVTIE (BUFF2 event interrupt enable) */ -/*!< B3EVTIE configuration */ -#define HSP_EVT_IER_B3EVTIE_Pos (15U) + +#define HSP_EVT_IER_B3EVTIE_Pos (15UL) #define HSP_EVT_IER_B3EVTIE_Msk (0x1UL << HSP_EVT_IER_B3EVTIE_Pos) /*!< 0x00008000 */ #define HSP_EVT_IER_B3EVTIE HSP_EVT_IER_B3EVTIE_Msk /*!< B3EVTIE (BUFF3 event interrupt enable) */ -/*!< SOTECP0IE configuration */ -#define HSP_EVT_IER_SOTECP0IE_Pos (16U) + +#define HSP_EVT_IER_SOTECP0IE_Pos (16UL) #define HSP_EVT_IER_SOTECP0IE_Msk (0x1UL << HSP_EVT_IER_SOTECP0IE_Pos) /*!< 0x00010000 */ #define HSP_EVT_IER_SOTECP0IE HSP_EVT_IER_SOTECP0IE_Msk /*!< SOTECP0IE (Start of task generated by event comparator 0 interrupt enable) */ -/*!< SOTECP1IE configuration */ -#define HSP_EVT_IER_SOTECP1IE_Pos (17U) + +#define HSP_EVT_IER_SOTECP1IE_Pos (17UL) #define HSP_EVT_IER_SOTECP1IE_Msk (0x1UL << HSP_EVT_IER_SOTECP1IE_Pos) /*!< 0x00020000 */ #define HSP_EVT_IER_SOTECP1IE HSP_EVT_IER_SOTECP1IE_Msk /*!< SOTECP1IE (Start of task generated by event comparator 1 interrupt enable) */ -/*!< SOTECP2IE configuration */ -#define HSP_EVT_IER_SOTECP2IE_Pos (18U) + +#define HSP_EVT_IER_SOTECP2IE_Pos (18UL) #define HSP_EVT_IER_SOTECP2IE_Msk (0x1UL << HSP_EVT_IER_SOTECP2IE_Pos) /*!< 0x00040000 */ #define HSP_EVT_IER_SOTECP2IE HSP_EVT_IER_SOTECP2IE_Msk /*!< SOTECP2IE (Start of task generated by event comparator 2 interrupt enable) */ -/*!< SOTECP3IE configuration */ -#define HSP_EVT_IER_SOTECP3IE_Pos (19U) + +#define HSP_EVT_IER_SOTECP3IE_Pos (19UL) #define HSP_EVT_IER_SOTECP3IE_Msk (0x1UL << HSP_EVT_IER_SOTECP3IE_Pos) /*!< 0x00080000 */ #define HSP_EVT_IER_SOTECP3IE HSP_EVT_IER_SOTECP3IE_Msk /*!< SOTECP3IE (Start of task generated by event comparator 3 interrupt enable) */ -/*!< EOTECP0IE configuration */ -#define HSP_EVT_IER_EOTECP0IE_Pos (20U) + +#define HSP_EVT_IER_EOTECP0IE_Pos (20UL) #define HSP_EVT_IER_EOTECP0IE_Msk (0x1UL << HSP_EVT_IER_EOTECP0IE_Pos) /*!< 0x00100000 */ #define HSP_EVT_IER_EOTECP0IE HSP_EVT_IER_EOTECP0IE_Msk /*!< EOTECP0IE (End of task generated by event comparator 0 interrupt enable) */ -/*!< EOTECP1IE configuration */ -#define HSP_EVT_IER_EOTECP1IE_Pos (21U) + +#define HSP_EVT_IER_EOTECP1IE_Pos (21UL) #define HSP_EVT_IER_EOTECP1IE_Msk (0x1UL << HSP_EVT_IER_EOTECP1IE_Pos) /*!< 0x00200000 */ #define HSP_EVT_IER_EOTECP1IE HSP_EVT_IER_EOTECP1IE_Msk /*!< EOTECP1IE (End of task generated by event comparator 1 interrupt enable) */ -/*!< EOTECP2IE configuration */ -#define HSP_EVT_IER_EOTECP2IE_Pos (22U) + +#define HSP_EVT_IER_EOTECP2IE_Pos (22UL) #define HSP_EVT_IER_EOTECP2IE_Msk (0x1UL << HSP_EVT_IER_EOTECP2IE_Pos) /*!< 0x00400000 */ #define HSP_EVT_IER_EOTECP2IE HSP_EVT_IER_EOTECP2IE_Msk /*!< EOTECP2IE (End of task generated by event comparator 2 interrupt enable) */ -/*!< EOTECP3IE configuration */ -#define HSP_EVT_IER_EOTECP3IE_Pos (23U) + +#define HSP_EVT_IER_EOTECP3IE_Pos (23UL) #define HSP_EVT_IER_EOTECP3IE_Msk (0x1UL << HSP_EVT_IER_EOTECP3IE_Pos) /*!< 0x00800000 */ #define HSP_EVT_IER_EOTECP3IE HSP_EVT_IER_EOTECP3IE_Msk /*!< EOTECP3IE (End of task generated by event comparator 3 interrupt enable) */ -/*!< TOVLPIE configuration */ -#define HSP_EVT_IER_TOVLPIE_Pos (28U) + +#define HSP_EVT_IER_TOVLPIE_Pos (28UL) #define HSP_EVT_IER_TOVLPIE_Msk (0x1UL << HSP_EVT_IER_TOVLPIE_Pos) /*!< 0x10000000 */ #define HSP_EVT_IER_TOVLPIE HSP_EVT_IER_TOVLPIE_Msk /*!< TOVLPIE (Task overlap flag interrupt enable) */ -/*!< FPUSATIE configuration */ -#define HSP_EVT_IER_FPUSATIE_Pos (31U) + +#define HSP_EVT_IER_FPUSATIE_Pos (31UL) #define HSP_EVT_IER_FPUSATIE_Msk (0x1UL << HSP_EVT_IER_FPUSATIE_Pos) /*!< 0x80000000 */ #define HSP_EVT_IER_FPUSATIE HSP_EVT_IER_FPUSATIE_Msk /*!< FPUSATIE (Saturation flag interrupt enable) */ /******************** Bit definition for HSP_PFCTEVT_IER register ********************/ -/*!< PFCTIE configuration */ -#define HSP_PFCTEVT_IER_PFCTIE_Pos (0U) +#define HSP_PFCTEVT_IER_PFCTIE_Pos (0UL) #define HSP_PFCTEVT_IER_PFCTIE_Msk (0xFFFFFFFFUL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0xFFFFFFFF */ #define HSP_PFCTEVT_IER_PFCTIE HSP_PFCTEVT_IER_PFCTIE_Msk /*!< PFCTIE[31:0] bits (Processing function flags interrupt enable) */ #define HSP_PFCTEVT_IER_PFCTIE_0 (0x00001UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000001 */ @@ -13023,148 +13626,145 @@ typedef struct #define HSP_PFCTEVT_IER_PFCTIE_31 (0x80000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_ERR_ISR register ********************/ -/*!< TRGIOVRF configuration */ -#define HSP_ERR_ISR_TRGIOVRF_Pos (8U) +#define HSP_ERR_ISR_TRGIOVRF_Pos (8UL) #define HSP_ERR_ISR_TRGIOVRF_Msk (0x1UL << HSP_ERR_ISR_TRGIOVRF_Pos) /*!< 0x00000100 */ #define HSP_ERR_ISR_TRGIOVRF HSP_ERR_ISR_TRGIOVRF_Msk /*!< TRGIOVRF (TRGITF overrun flag) */ -/*!< B0ERRF configuration */ -#define HSP_ERR_ISR_B0ERRF_Pos (12U) + +#define HSP_ERR_ISR_B0ERRF_Pos (12UL) #define HSP_ERR_ISR_B0ERRF_Msk (0x1UL << HSP_ERR_ISR_B0ERRF_Pos) /*!< 0x00001000 */ #define HSP_ERR_ISR_B0ERRF HSP_ERR_ISR_B0ERRF_Msk /*!< B0ERRF (H2CBUFF0 underrun or C2HBUFF0 overrun flag) */ -/*!< B1ERRF configuration */ -#define HSP_ERR_ISR_B1ERRF_Pos (13U) + +#define HSP_ERR_ISR_B1ERRF_Pos (13UL) #define HSP_ERR_ISR_B1ERRF_Msk (0x1UL << HSP_ERR_ISR_B1ERRF_Pos) /*!< 0x00002000 */ #define HSP_ERR_ISR_B1ERRF HSP_ERR_ISR_B1ERRF_Msk /*!< B1ERRF (H2CBUFF1 underrun or C2HBUFF1 overrun flag) */ -/*!< B2ERRF configuration */ -#define HSP_ERR_ISR_B2ERRF_Pos (14U) + +#define HSP_ERR_ISR_B2ERRF_Pos (14UL) #define HSP_ERR_ISR_B2ERRF_Msk (0x1UL << HSP_ERR_ISR_B2ERRF_Pos) /*!< 0x00004000 */ #define HSP_ERR_ISR_B2ERRF HSP_ERR_ISR_B2ERRF_Msk /*!< B2ERRF (H2CBUFF2 underrun or C2HBUFF2 overrun flag) */ -/*!< B3ERRF configuration */ -#define HSP_ERR_ISR_B3ERRF_Pos (15U) + +#define HSP_ERR_ISR_B3ERRF_Pos (15UL) #define HSP_ERR_ISR_B3ERRF_Msk (0x1UL << HSP_ERR_ISR_B3ERRF_Pos) /*!< 0x00008000 */ #define HSP_ERR_ISR_B3ERRF HSP_ERR_ISR_B3ERRF_Msk /*!< B3ERRF (H2CBUFF3 underrun or C2HBUFF3 overrun flag) */ -/*!< CAPOVRF configuration */ -#define HSP_ERR_ISR_CAPOVRF_Pos (16U) + +#define HSP_ERR_ISR_CAPOVRF_Pos (16UL) #define HSP_ERR_ISR_CAPOVRF_Msk (0x1UL << HSP_ERR_ISR_CAPOVRF_Pos) /*!< 0x00010000 */ #define HSP_ERR_ISR_CAPOVRF HSP_ERR_ISR_CAPOVRF_Msk /*!< CAPOVRF (Capture register overrun flag) */ -/*!< FWERRF configuration */ -#define HSP_ERR_ISR_FWERRF_Pos (17U) + +#define HSP_ERR_ISR_FWERRF_Pos (17UL) #define HSP_ERR_ISR_FWERRF_Msk (0x1UL << HSP_ERR_ISR_FWERRF_Pos) /*!< 0x00020000 */ #define HSP_ERR_ISR_FWERRF HSP_ERR_ISR_FWERRF_Msk /*!< FWERRF (Firmware error flag) */ -/*!< SCHERRF configuration */ -#define HSP_ERR_ISR_SCHERRF_Pos (18U) + +#define HSP_ERR_ISR_SCHERRF_Pos (18UL) #define HSP_ERR_ISR_SCHERRF_Msk (0x1UL << HSP_ERR_ISR_SCHERRF_Pos) /*!< 0x00040000 */ #define HSP_ERR_ISR_SCHERRF HSP_ERR_ISR_SCHERRF_Msk /*!< SCHERRF (Scheduler error flag) */ -/*!< BKINF configuration */ -#define HSP_ERR_ISR_BKINF_Pos (19U) + +#define HSP_ERR_ISR_BKINF_Pos (19UL) #define HSP_ERR_ISR_BKINF_Msk (0x1UL << HSP_ERR_ISR_BKINF_Pos) /*!< 0x00080000 */ #define HSP_ERR_ISR_BKINF HSP_ERR_ISR_BKINF_Msk /*!< BKINF (Break input flag) */ -/*!< HDEGOVRF configuration */ -#define HSP_ERR_ISR_HDEGOVRF_Pos (20U) + +#define HSP_ERR_ISR_HDEGOVRF_Pos (20UL) #define HSP_ERR_ISR_HDEGOVRF_Msk (0x1UL << HSP_ERR_ISR_HDEGOVRF_Pos) /*!< 0x00100000 */ #define HSP_ERR_ISR_HDEGOVRF HSP_ERR_ISR_HDEGOVRF_Msk /*!< HDEGOVRF (SPE event overrun flag) */ -/*!< OPCOERRF configuration */ -#define HSP_ERR_ISR_OPCOERRF_Pos (22U) + +#define HSP_ERR_ISR_OPCOERRF_Pos (22UL) #define HSP_ERR_ISR_OPCOERRF_Msk (0x1UL << HSP_ERR_ISR_OPCOERRF_Pos) /*!< 0x00400000 */ #define HSP_ERR_ISR_OPCOERRF HSP_ERR_ISR_OPCOERRF_Msk /*!< OPCOERRF (Invalid OpCode error flag) */ -/*!< ACCERRF configuration */ -#define HSP_ERR_ISR_ACCERRF_Pos (23U) + +#define HSP_ERR_ISR_ACCERRF_Pos (23UL) #define HSP_ERR_ISR_ACCERRF_Msk (0x1UL << HSP_ERR_ISR_ACCERRF_Pos) /*!< 0x00800000 */ #define HSP_ERR_ISR_ACCERRF HSP_ERR_ISR_ACCERRF_Msk /*!< ACCERRF (SPE Access error flag) */ -/*!< FPUERRF configuration */ -#define HSP_ERR_ISR_FPUERRF_Pos (24U) + +#define HSP_ERR_ISR_FPUERRF_Pos (24UL) #define HSP_ERR_ISR_FPUERRF_Msk (0x1UL << HSP_ERR_ISR_FPUERRF_Pos) /*!< 0x01000000 */ #define HSP_ERR_ISR_FPUERRF HSP_ERR_ISR_FPUERRF_Msk /*!< FPUERRF (Computation error flag) */ /******************** Bit definition for HSP_EVT_ISR register ********************/ -/*!< H2CMRDYF configuration */ -#define HSP_EVT_ISR_H2CMRDYF_Pos (0U) +#define HSP_EVT_ISR_H2CMRDYF_Pos (0UL) #define HSP_EVT_ISR_H2CMRDYF_Msk (0x1UL << HSP_EVT_ISR_H2CMRDYF_Pos) /*!< 0x00000001 */ #define HSP_EVT_ISR_H2CMRDYF HSP_EVT_ISR_H2CMRDYF_Msk /*!< H2CMRDYF (HSP to CPU message ready flag) */ -/*!< C2HMFREEF configuration */ -#define HSP_EVT_ISR_C2HMFREEF_Pos (1U) + +#define HSP_EVT_ISR_C2HMFREEF_Pos (1UL) #define HSP_EVT_ISR_C2HMFREEF_Msk (0x1UL << HSP_EVT_ISR_C2HMFREEF_Pos) /*!< 0x00000002 */ #define HSP_EVT_ISR_C2HMFREEF HSP_EVT_ISR_C2HMFREEF_Msk /*!< C2HMFREEF (CPU to HSP message box free flag) */ -/*!< DCDONEF configuration */ -#define HSP_EVT_ISR_DCDONEF_Pos (2U) + +#define HSP_EVT_ISR_DCDONEF_Pos (2UL) #define HSP_EVT_ISR_DCDONEF_Msk (0x1UL << HSP_EVT_ISR_DCDONEF_Pos) /*!< 0x00000004 */ #define HSP_EVT_ISR_DCDONEF HSP_EVT_ISR_DCDONEF_Msk /*!< DCDONEF (Direct command done flag) */ -/*!< CAPRDYF configuration */ -#define HSP_EVT_ISR_CAPRDYF_Pos (4U) + +#define HSP_EVT_ISR_CAPRDYF_Pos (4UL) #define HSP_EVT_ISR_CAPRDYF_Msk (0x1UL << HSP_EVT_ISR_CAPRDYF_Pos) /*!< 0x00000010 */ #define HSP_EVT_ISR_CAPRDYF HSP_EVT_ISR_CAPRDYF_Msk /*!< CAPRDYF (Capture buffer data ready flag) */ -/*!< CDEGRDYF configuration */ -#define HSP_EVT_ISR_CDEGRDYF_Pos (7U) + +#define HSP_EVT_ISR_CDEGRDYF_Pos (7UL) #define HSP_EVT_ISR_CDEGRDYF_Msk (0x1UL << HSP_EVT_ISR_CDEGRDYF_Pos) /*!< 0x00000080 */ #define HSP_EVT_ISR_CDEGRDYF HSP_EVT_ISR_CDEGRDYF_Msk /*!< CDEGRDYF (CPU Dedicated event generator ready flag) */ -/*!< SOFWFEF configuration */ -#define HSP_EVT_ISR_SOFWFEF_Pos (8U) + +#define HSP_EVT_ISR_SOFWFEF_Pos (8UL) #define HSP_EVT_ISR_SOFWFEF_Msk (0x1UL << HSP_EVT_ISR_SOFWFEF_Pos) /*!< 0x00000100 */ #define HSP_EVT_ISR_SOFWFEF HSP_EVT_ISR_SOFWFEF_Msk /*!< SOFWFEF (Start of WFE flag) */ -/*!< EOFWFEF configuration */ -#define HSP_EVT_ISR_EOFWFEF_Pos (9U) + +#define HSP_EVT_ISR_EOFWFEF_Pos (9UL) #define HSP_EVT_ISR_EOFWFEF_Msk (0x1UL << HSP_EVT_ISR_EOFWFEF_Pos) /*!< 0x00000200 */ #define HSP_EVT_ISR_EOFWFEF HSP_EVT_ISR_EOFWFEF_Msk /*!< EOFWFEF (End of WFE flag) */ -/*!< B0EVTF configuration */ -#define HSP_EVT_ISR_B0EVTF_Pos (12U) + +#define HSP_EVT_ISR_B0EVTF_Pos (12UL) #define HSP_EVT_ISR_B0EVTF_Msk (0x1UL << HSP_EVT_ISR_B0EVTF_Pos) /*!< 0x00001000 */ #define HSP_EVT_ISR_B0EVTF HSP_EVT_ISR_B0EVTF_Msk /*!< B0EVTF (BUFF0 event flag) */ -/*!< B1EVTF configuration */ -#define HSP_EVT_ISR_B1EVTF_Pos (13U) + +#define HSP_EVT_ISR_B1EVTF_Pos (13UL) #define HSP_EVT_ISR_B1EVTF_Msk (0x1UL << HSP_EVT_ISR_B1EVTF_Pos) /*!< 0x00002000 */ #define HSP_EVT_ISR_B1EVTF HSP_EVT_ISR_B1EVTF_Msk /*!< B1EVTF (BUFF1 event flag) */ -/*!< B2EVTF configuration */ -#define HSP_EVT_ISR_B2EVTF_Pos (14U) + +#define HSP_EVT_ISR_B2EVTF_Pos (14UL) #define HSP_EVT_ISR_B2EVTF_Msk (0x1UL << HSP_EVT_ISR_B2EVTF_Pos) /*!< 0x00004000 */ #define HSP_EVT_ISR_B2EVTF HSP_EVT_ISR_B2EVTF_Msk /*!< B2EVTF (BUFF2 event flag) */ -/*!< B3EVTF configuration */ -#define HSP_EVT_ISR_B3EVTF_Pos (15U) + +#define HSP_EVT_ISR_B3EVTF_Pos (15UL) #define HSP_EVT_ISR_B3EVTF_Msk (0x1UL << HSP_EVT_ISR_B3EVTF_Pos) /*!< 0x00008000 */ #define HSP_EVT_ISR_B3EVTF HSP_EVT_ISR_B3EVTF_Msk /*!< B3EVTF (BUFF3 event flag) */ -/*!< SOTECP0F configuration */ -#define HSP_EVT_ISR_SOTECP0F_Pos (16U) + +#define HSP_EVT_ISR_SOTECP0F_Pos (16UL) #define HSP_EVT_ISR_SOTECP0F_Msk (0x1UL << HSP_EVT_ISR_SOTECP0F_Pos) /*!< 0x00010000 */ #define HSP_EVT_ISR_SOTECP0F HSP_EVT_ISR_SOTECP0F_Msk /*!< SOTECP0F (Start of task flag, for event comparator 0) */ -/*!< SOTECP1F configuration */ -#define HSP_EVT_ISR_SOTECP1F_Pos (17U) + +#define HSP_EVT_ISR_SOTECP1F_Pos (17UL) #define HSP_EVT_ISR_SOTECP1F_Msk (0x1UL << HSP_EVT_ISR_SOTECP1F_Pos) /*!< 0x00020000 */ #define HSP_EVT_ISR_SOTECP1F HSP_EVT_ISR_SOTECP1F_Msk /*!< SOTECP1F (Start of task flag, for event comparator 1) */ -/*!< SOTECP2F configuration */ -#define HSP_EVT_ISR_SOTECP2F_Pos (18U) + +#define HSP_EVT_ISR_SOTECP2F_Pos (18UL) #define HSP_EVT_ISR_SOTECP2F_Msk (0x1UL << HSP_EVT_ISR_SOTECP2F_Pos) /*!< 0x00040000 */ #define HSP_EVT_ISR_SOTECP2F HSP_EVT_ISR_SOTECP2F_Msk /*!< SOTECP2F (Start of task flag, for event comparator 2) */ -/*!< SOTECP3F configuration */ -#define HSP_EVT_ISR_SOTECP3F_Pos (19U) + +#define HSP_EVT_ISR_SOTECP3F_Pos (19UL) #define HSP_EVT_ISR_SOTECP3F_Msk (0x1UL << HSP_EVT_ISR_SOTECP3F_Pos) /*!< 0x00080000 */ #define HSP_EVT_ISR_SOTECP3F HSP_EVT_ISR_SOTECP3F_Msk /*!< SOTECP3F (Start of task flag, for event comparator 3) */ -/*!< EOTECP0F configuration */ -#define HSP_EVT_ISR_EOTECP0F_Pos (20U) + +#define HSP_EVT_ISR_EOTECP0F_Pos (20UL) #define HSP_EVT_ISR_EOTECP0F_Msk (0x1UL << HSP_EVT_ISR_EOTECP0F_Pos) /*!< 0x00100000 */ #define HSP_EVT_ISR_EOTECP0F HSP_EVT_ISR_EOTECP0F_Msk /*!< EOTECP0F (End of task flag, for event comparator 0) */ -/*!< EOTECP1F configuration */ -#define HSP_EVT_ISR_EOTECP1F_Pos (21U) + +#define HSP_EVT_ISR_EOTECP1F_Pos (21UL) #define HSP_EVT_ISR_EOTECP1F_Msk (0x1UL << HSP_EVT_ISR_EOTECP1F_Pos) /*!< 0x00200000 */ #define HSP_EVT_ISR_EOTECP1F HSP_EVT_ISR_EOTECP1F_Msk /*!< EOTECP1F (End of task flag, for event comparator 1) */ -/*!< EOTECP2F configuration */ -#define HSP_EVT_ISR_EOTECP2F_Pos (22U) + +#define HSP_EVT_ISR_EOTECP2F_Pos (22UL) #define HSP_EVT_ISR_EOTECP2F_Msk (0x1UL << HSP_EVT_ISR_EOTECP2F_Pos) /*!< 0x00400000 */ #define HSP_EVT_ISR_EOTECP2F HSP_EVT_ISR_EOTECP2F_Msk /*!< EOTECP2F (End of task flag, for event comparator 2) */ -/*!< EOTECP3F configuration */ -#define HSP_EVT_ISR_EOTECP3F_Pos (23U) + +#define HSP_EVT_ISR_EOTECP3F_Pos (23UL) #define HSP_EVT_ISR_EOTECP3F_Msk (0x1UL << HSP_EVT_ISR_EOTECP3F_Pos) /*!< 0x00800000 */ #define HSP_EVT_ISR_EOTECP3F HSP_EVT_ISR_EOTECP3F_Msk /*!< EOTECP3F (End of task flag, for event comparator 3) */ -/*!< TOVLPF configuration */ -#define HSP_EVT_ISR_TOVLPF_Pos (28U) + +#define HSP_EVT_ISR_TOVLPF_Pos (28UL) #define HSP_EVT_ISR_TOVLPF_Msk (0x1UL << HSP_EVT_ISR_TOVLPF_Pos) /*!< 0x10000000 */ #define HSP_EVT_ISR_TOVLPF HSP_EVT_ISR_TOVLPF_Msk /*!< TOVLPF (Task overlap flag) */ -/*!< FPUSATF configuration */ -#define HSP_EVT_ISR_FPUSATF_Pos (31U) + +#define HSP_EVT_ISR_FPUSATF_Pos (31UL) #define HSP_EVT_ISR_FPUSATF_Msk (0x1UL << HSP_EVT_ISR_FPUSATF_Pos) /*!< 0x80000000 */ #define HSP_EVT_ISR_FPUSATF HSP_EVT_ISR_FPUSATF_Msk /*!< FPUSATF (FPU saturation flag) */ /******************** Bit definition for HSP_PFCTEVT_ISR register ********************/ -/*!< PFCTF configuration */ -#define HSP_PFCTEVT_ISR_PFCTF_Pos (0U) +#define HSP_PFCTEVT_ISR_PFCTF_Pos (0UL) #define HSP_PFCTEVT_ISR_PFCTF_Msk (0xFFFFFFFFUL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0xFFFFFFFF */ #define HSP_PFCTEVT_ISR_PFCTF HSP_PFCTEVT_ISR_PFCTF_Msk /*!< PFCTF[31:0] bits (Flags generated by SPE processing functions ) */ #define HSP_PFCTEVT_ISR_PFCTF_0 (0x00001UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000001 */ @@ -13201,48 +13801,47 @@ typedef struct #define HSP_PFCTEVT_ISR_PFCTF_31 (0x80000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_ERRINFR register ********************/ -/*!< INEXACT configuration */ -#define HSP_ERRINFR_INEXACT_Pos (0U) +#define HSP_ERRINFR_INEXACT_Pos (0UL) #define HSP_ERRINFR_INEXACT_Msk (0x1UL << HSP_ERRINFR_INEXACT_Pos) /*!< 0x00000001 */ #define HSP_ERRINFR_INEXACT HSP_ERRINFR_INEXACT_Msk /*!< INEXACT (INEXACT exception flag) */ -/*!< UDFLOW configuration */ -#define HSP_ERRINFR_UDFLOW_Pos (1U) + +#define HSP_ERRINFR_UDFLOW_Pos (1UL) #define HSP_ERRINFR_UDFLOW_Msk (0x1UL << HSP_ERRINFR_UDFLOW_Pos) /*!< 0x00000002 */ #define HSP_ERRINFR_UDFLOW HSP_ERRINFR_UDFLOW_Msk /*!< UDFLOW (UNDERFLOW exception flag) */ -/*!< OVFLOW configuration */ -#define HSP_ERRINFR_OVFLOW_Pos (2U) + +#define HSP_ERRINFR_OVFLOW_Pos (2UL) #define HSP_ERRINFR_OVFLOW_Msk (0x1UL << HSP_ERRINFR_OVFLOW_Pos) /*!< 0x00000004 */ #define HSP_ERRINFR_OVFLOW HSP_ERRINFR_OVFLOW_Msk /*!< OVFLOW (OVERFLOW exception flag) */ -/*!< DIVZERO configuration */ -#define HSP_ERRINFR_DIVZERO_Pos (3U) + +#define HSP_ERRINFR_DIVZERO_Pos (3UL) #define HSP_ERRINFR_DIVZERO_Msk (0x1UL << HSP_ERRINFR_DIVZERO_Pos) /*!< 0x00000008 */ #define HSP_ERRINFR_DIVZERO HSP_ERRINFR_DIVZERO_Msk /*!< DIVZERO (Division by zero exception flag) */ -/*!< INVALID configuration */ -#define HSP_ERRINFR_INVALID_Pos (4U) + +#define HSP_ERRINFR_INVALID_Pos (4UL) #define HSP_ERRINFR_INVALID_Msk (0x1UL << HSP_ERRINFR_INVALID_Pos) /*!< 0x00000010 */ #define HSP_ERRINFR_INVALID HSP_ERRINFR_INVALID_Msk /*!< INVALID (INVALID exception flag) */ -/*!< DENORM configuration */ -#define HSP_ERRINFR_DENORM_Pos (5U) + +#define HSP_ERRINFR_DENORM_Pos (5UL) #define HSP_ERRINFR_DENORM_Msk (0x1UL << HSP_ERRINFR_DENORM_Pos) /*!< 0x00000020 */ #define HSP_ERRINFR_DENORM HSP_ERRINFR_DENORM_Msk /*!< DENORM (DENORMAL exception flag) */ -/*!< CMERR configuration */ -#define HSP_ERRINFR_CMERR_Pos (8U) + +#define HSP_ERRINFR_CMERR_Pos (8UL) #define HSP_ERRINFR_CMERR_Msk (0x1UL << HSP_ERRINFR_CMERR_Pos) /*!< 0x00000100 */ #define HSP_ERRINFR_CMERR HSP_ERRINFR_CMERR_Msk /*!< CMERR (Code memory access error flag) */ -/*!< DMERR configuration */ -#define HSP_ERRINFR_DMERR_Pos (9U) + +#define HSP_ERRINFR_DMERR_Pos (9UL) #define HSP_ERRINFR_DMERR_Msk (0x1UL << HSP_ERRINFR_DMERR_Pos) /*!< 0x00000200 */ #define HSP_ERRINFR_DMERR HSP_ERRINFR_DMERR_Msk /*!< DMERR (Data memory access error flag) */ -/*!< MAHBERR configuration */ -#define HSP_ERRINFR_MAHBERR_Pos (11U) + +#define HSP_ERRINFR_MAHBERR_Pos (11UL) #define HSP_ERRINFR_MAHBERR_Msk (0x1UL << HSP_ERRINFR_MAHBERR_Pos) /*!< 0x00000800 */ #define HSP_ERRINFR_MAHBERR HSP_ERRINFR_MAHBERR_Msk /*!< MAHBERR (Internal AHB access error flag) */ -/*!< SAHBERR configuration */ -#define HSP_ERRINFR_SAHBERR_Pos (12U) + +#define HSP_ERRINFR_SAHBERR_Pos (12UL) #define HSP_ERRINFR_SAHBERR_Msk (0x1UL << HSP_ERRINFR_SAHBERR_Pos) /*!< 0x00001000 */ #define HSP_ERRINFR_SAHBERR HSP_ERRINFR_SAHBERR_Msk /*!< SAHBERR (Slave AHB access error flag) */ -/*!< TRGIERR configuration */ -#define HSP_ERRINFR_TRGIERR_Pos (16U) + +#define HSP_ERRINFR_TRGIERR_Pos (16UL) #define HSP_ERRINFR_TRGIERR_Msk (0x3FFUL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x03FF0000 */ #define HSP_ERRINFR_TRGIERR HSP_ERRINFR_TRGIERR_Msk /*!< TRGIERR[9:0] bits (TRGIN error information) */ #define HSP_ERRINFR_TRGIERR_0 (0x001UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00010000 */ @@ -13257,128 +13856,125 @@ typedef struct #define HSP_ERRINFR_TRGIERR_9 (0x200UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x02000000 */ /******************** Bit definition for HSP_ERR_ICR register ********************/ -/*!< TRGIOVRC configuration */ -#define HSP_ERR_ICR_TRGIOVRC_Pos (8U) +#define HSP_ERR_ICR_TRGIOVRC_Pos (8UL) #define HSP_ERR_ICR_TRGIOVRC_Msk (0x1UL << HSP_ERR_ICR_TRGIOVRC_Pos) /*!< 0x00000100 */ #define HSP_ERR_ICR_TRGIOVRC HSP_ERR_ICR_TRGIOVRC_Msk /*!< TRGIOVRC (Clear TRGIOVRF flag) */ -/*!< B0ERRC configuration */ -#define HSP_ERR_ICR_B0ERRC_Pos (12U) + +#define HSP_ERR_ICR_B0ERRC_Pos (12UL) #define HSP_ERR_ICR_B0ERRC_Msk (0x1UL << HSP_ERR_ICR_B0ERRC_Pos) /*!< 0x00001000 */ #define HSP_ERR_ICR_B0ERRC HSP_ERR_ICR_B0ERRC_Msk /*!< B0ERRC (Clear B0ERRF flag) */ -/*!< B1ERRC configuration */ -#define HSP_ERR_ICR_B1ERRC_Pos (13U) + +#define HSP_ERR_ICR_B1ERRC_Pos (13UL) #define HSP_ERR_ICR_B1ERRC_Msk (0x1UL << HSP_ERR_ICR_B1ERRC_Pos) /*!< 0x00002000 */ #define HSP_ERR_ICR_B1ERRC HSP_ERR_ICR_B1ERRC_Msk /*!< B1ERRC (Clear B1ERRF flag) */ -/*!< B2ERRC configuration */ -#define HSP_ERR_ICR_B2ERRC_Pos (14U) + +#define HSP_ERR_ICR_B2ERRC_Pos (14UL) #define HSP_ERR_ICR_B2ERRC_Msk (0x1UL << HSP_ERR_ICR_B2ERRC_Pos) /*!< 0x00004000 */ #define HSP_ERR_ICR_B2ERRC HSP_ERR_ICR_B2ERRC_Msk /*!< B2ERRC (Clear B2ERRF flag) */ -/*!< B3ERRC configuration */ -#define HSP_ERR_ICR_B3ERRC_Pos (15U) + +#define HSP_ERR_ICR_B3ERRC_Pos (15UL) #define HSP_ERR_ICR_B3ERRC_Msk (0x1UL << HSP_ERR_ICR_B3ERRC_Pos) /*!< 0x00008000 */ #define HSP_ERR_ICR_B3ERRC HSP_ERR_ICR_B3ERRC_Msk /*!< B3ERRC (Clear B3ERRF flag) */ -/*!< CAPOVRC configuration */ -#define HSP_ERR_ICR_CAPOVRC_Pos (16U) + +#define HSP_ERR_ICR_CAPOVRC_Pos (16UL) #define HSP_ERR_ICR_CAPOVRC_Msk (0x1UL << HSP_ERR_ICR_CAPOVRC_Pos) /*!< 0x00010000 */ #define HSP_ERR_ICR_CAPOVRC HSP_ERR_ICR_CAPOVRC_Msk /*!< CAPOVRC (Clear CAPOVRF flag) */ -/*!< FWERRC configuration */ -#define HSP_ERR_ICR_FWERRC_Pos (17U) + +#define HSP_ERR_ICR_FWERRC_Pos (17UL) #define HSP_ERR_ICR_FWERRC_Msk (0x1UL << HSP_ERR_ICR_FWERRC_Pos) /*!< 0x00020000 */ #define HSP_ERR_ICR_FWERRC HSP_ERR_ICR_FWERRC_Msk /*!< FWERRC (Clear FWERRF flag) */ -/*!< SCHERRC configuration */ -#define HSP_ERR_ICR_SCHERRC_Pos (18U) + +#define HSP_ERR_ICR_SCHERRC_Pos (18UL) #define HSP_ERR_ICR_SCHERRC_Msk (0x1UL << HSP_ERR_ICR_SCHERRC_Pos) /*!< 0x00040000 */ #define HSP_ERR_ICR_SCHERRC HSP_ERR_ICR_SCHERRC_Msk /*!< SCHERRC (Clear SCHERRF flag) */ -/*!< BKINC configuration */ -#define HSP_ERR_ICR_BKINC_Pos (19U) + +#define HSP_ERR_ICR_BKINC_Pos (19UL) #define HSP_ERR_ICR_BKINC_Msk (0x1UL << HSP_ERR_ICR_BKINC_Pos) /*!< 0x00080000 */ #define HSP_ERR_ICR_BKINC HSP_ERR_ICR_BKINC_Msk /*!< BKINC (Clear BKINF flag) */ -/*!< HDEGOVRC configuration */ -#define HSP_ERR_ICR_HDEGOVRC_Pos (20U) + +#define HSP_ERR_ICR_HDEGOVRC_Pos (20UL) #define HSP_ERR_ICR_HDEGOVRC_Msk (0x1UL << HSP_ERR_ICR_HDEGOVRC_Pos) /*!< 0x00100000 */ #define HSP_ERR_ICR_HDEGOVRC HSP_ERR_ICR_HDEGOVRC_Msk /*!< HDEGOVRC (Clear HDEGOVRF flag) */ -/*!< OPCOERRC configuration */ -#define HSP_ERR_ICR_OPCOERRC_Pos (22U) + +#define HSP_ERR_ICR_OPCOERRC_Pos (22UL) #define HSP_ERR_ICR_OPCOERRC_Msk (0x1UL << HSP_ERR_ICR_OPCOERRC_Pos) /*!< 0x00400000 */ #define HSP_ERR_ICR_OPCOERRC HSP_ERR_ICR_OPCOERRC_Msk /*!< OPCOERRC (Clear OPCOERRF flag) */ -/*!< ACCERRC configuration */ -#define HSP_ERR_ICR_ACCERRC_Pos (23U) + +#define HSP_ERR_ICR_ACCERRC_Pos (23UL) #define HSP_ERR_ICR_ACCERRC_Msk (0x1UL << HSP_ERR_ICR_ACCERRC_Pos) /*!< 0x00800000 */ #define HSP_ERR_ICR_ACCERRC HSP_ERR_ICR_ACCERRC_Msk /*!< ACCERRC (Clear ACCERRF flag) */ -/*!< FPUERRC configuration */ -#define HSP_ERR_ICR_FPUERRC_Pos (24U) + +#define HSP_ERR_ICR_FPUERRC_Pos (24UL) #define HSP_ERR_ICR_FPUERRC_Msk (0x1UL << HSP_ERR_ICR_FPUERRC_Pos) /*!< 0x01000000 */ #define HSP_ERR_ICR_FPUERRC HSP_ERR_ICR_FPUERRC_Msk /*!< FPUERRC (Clear FPUERRF flag) */ /******************** Bit definition for HSP_EVT_ICR register ********************/ -/*!< H2CMRDYC configuration */ -#define HSP_EVT_ICR_H2CMRDYC_Pos (0U) +#define HSP_EVT_ICR_H2CMRDYC_Pos (0UL) #define HSP_EVT_ICR_H2CMRDYC_Msk (0x1UL << HSP_EVT_ICR_H2CMRDYC_Pos) /*!< 0x00000001 */ #define HSP_EVT_ICR_H2CMRDYC HSP_EVT_ICR_H2CMRDYC_Msk /*!< H2CMRDYC (Clear H2CMRDYF flag) */ -/*!< C2HMFREEC configuration */ -#define HSP_EVT_ICR_C2HMFREEC_Pos (1U) + +#define HSP_EVT_ICR_C2HMFREEC_Pos (1UL) #define HSP_EVT_ICR_C2HMFREEC_Msk (0x1UL << HSP_EVT_ICR_C2HMFREEC_Pos) /*!< 0x00000002 */ #define HSP_EVT_ICR_C2HMFREEC HSP_EVT_ICR_C2HMFREEC_Msk /*!< C2HMFREEC (Clear C2HMFREEF flag) */ -/*!< DCDONEC configuration */ -#define HSP_EVT_ICR_DCDONEC_Pos (2U) + +#define HSP_EVT_ICR_DCDONEC_Pos (2UL) #define HSP_EVT_ICR_DCDONEC_Msk (0x1UL << HSP_EVT_ICR_DCDONEC_Pos) /*!< 0x00000004 */ #define HSP_EVT_ICR_DCDONEC HSP_EVT_ICR_DCDONEC_Msk /*!< DCDONEC (Clear DCDONEF flag) */ -/*!< CDEGRDYC configuration */ -#define HSP_EVT_ICR_CDEGRDYC_Pos (7U) + +#define HSP_EVT_ICR_CDEGRDYC_Pos (7UL) #define HSP_EVT_ICR_CDEGRDYC_Msk (0x1UL << HSP_EVT_ICR_CDEGRDYC_Pos) /*!< 0x00000080 */ #define HSP_EVT_ICR_CDEGRDYC HSP_EVT_ICR_CDEGRDYC_Msk /*!< CDEGRDYC (Clear of CDEGRDYF flag) */ -/*!< SOFWFEC configuration */ -#define HSP_EVT_ICR_SOFWFEC_Pos (8U) + +#define HSP_EVT_ICR_SOFWFEC_Pos (8UL) #define HSP_EVT_ICR_SOFWFEC_Msk (0x1UL << HSP_EVT_ICR_SOFWFEC_Pos) /*!< 0x00000100 */ #define HSP_EVT_ICR_SOFWFEC HSP_EVT_ICR_SOFWFEC_Msk /*!< SOFWFEC (Clear of SOFWFEF flag) */ -/*!< EOFWFEC configuration */ -#define HSP_EVT_ICR_EOFWFEC_Pos (9U) + +#define HSP_EVT_ICR_EOFWFEC_Pos (9UL) #define HSP_EVT_ICR_EOFWFEC_Msk (0x1UL << HSP_EVT_ICR_EOFWFEC_Pos) /*!< 0x00000200 */ #define HSP_EVT_ICR_EOFWFEC HSP_EVT_ICR_EOFWFEC_Msk /*!< EOFWFEC (Clear of EOFWFEF flag) */ -/*!< SOTECP0C configuration */ -#define HSP_EVT_ICR_SOTECP0C_Pos (16U) + +#define HSP_EVT_ICR_SOTECP0C_Pos (16UL) #define HSP_EVT_ICR_SOTECP0C_Msk (0x1UL << HSP_EVT_ICR_SOTECP0C_Pos) /*!< 0x00010000 */ #define HSP_EVT_ICR_SOTECP0C HSP_EVT_ICR_SOTECP0C_Msk /*!< SOTECP0C (Clear SOTECP0F flag) */ -/*!< SOTECP1C configuration */ -#define HSP_EVT_ICR_SOTECP1C_Pos (17U) + +#define HSP_EVT_ICR_SOTECP1C_Pos (17UL) #define HSP_EVT_ICR_SOTECP1C_Msk (0x1UL << HSP_EVT_ICR_SOTECP1C_Pos) /*!< 0x00020000 */ #define HSP_EVT_ICR_SOTECP1C HSP_EVT_ICR_SOTECP1C_Msk /*!< SOTECP1C (Clear SOTECP1F flag) */ -/*!< SOTECP2C configuration */ -#define HSP_EVT_ICR_SOTECP2C_Pos (18U) + +#define HSP_EVT_ICR_SOTECP2C_Pos (18UL) #define HSP_EVT_ICR_SOTECP2C_Msk (0x1UL << HSP_EVT_ICR_SOTECP2C_Pos) /*!< 0x00040000 */ #define HSP_EVT_ICR_SOTECP2C HSP_EVT_ICR_SOTECP2C_Msk /*!< SOTECP2C (Clear SOTECP2F flag) */ -/*!< SOTECP3C configuration */ -#define HSP_EVT_ICR_SOTECP3C_Pos (19U) + +#define HSP_EVT_ICR_SOTECP3C_Pos (19UL) #define HSP_EVT_ICR_SOTECP3C_Msk (0x1UL << HSP_EVT_ICR_SOTECP3C_Pos) /*!< 0x00080000 */ #define HSP_EVT_ICR_SOTECP3C HSP_EVT_ICR_SOTECP3C_Msk /*!< SOTECP3C (Clear SOTECP3F flag) */ -/*!< EOTECP0C configuration */ -#define HSP_EVT_ICR_EOTECP0C_Pos (20U) + +#define HSP_EVT_ICR_EOTECP0C_Pos (20UL) #define HSP_EVT_ICR_EOTECP0C_Msk (0x1UL << HSP_EVT_ICR_EOTECP0C_Pos) /*!< 0x00100000 */ #define HSP_EVT_ICR_EOTECP0C HSP_EVT_ICR_EOTECP0C_Msk /*!< EOTECP0C (Clear EOTECP0F flag) */ -/*!< EOTECP1C configuration */ -#define HSP_EVT_ICR_EOTECP1C_Pos (21U) + +#define HSP_EVT_ICR_EOTECP1C_Pos (21UL) #define HSP_EVT_ICR_EOTECP1C_Msk (0x1UL << HSP_EVT_ICR_EOTECP1C_Pos) /*!< 0x00200000 */ #define HSP_EVT_ICR_EOTECP1C HSP_EVT_ICR_EOTECP1C_Msk /*!< EOTECP1C (Clear EOTECP1F flag) */ -/*!< EOTECP2C configuration */ -#define HSP_EVT_ICR_EOTECP2C_Pos (22U) + +#define HSP_EVT_ICR_EOTECP2C_Pos (22UL) #define HSP_EVT_ICR_EOTECP2C_Msk (0x1UL << HSP_EVT_ICR_EOTECP2C_Pos) /*!< 0x00400000 */ #define HSP_EVT_ICR_EOTECP2C HSP_EVT_ICR_EOTECP2C_Msk /*!< EOTECP2C (Clear EOTECP2F flag) */ -/*!< EOTECP3C configuration */ -#define HSP_EVT_ICR_EOTECP3C_Pos (23U) + +#define HSP_EVT_ICR_EOTECP3C_Pos (23UL) #define HSP_EVT_ICR_EOTECP3C_Msk (0x1UL << HSP_EVT_ICR_EOTECP3C_Pos) /*!< 0x00800000 */ #define HSP_EVT_ICR_EOTECP3C HSP_EVT_ICR_EOTECP3C_Msk /*!< EOTECP3C (Clear EOTECP3F flag) */ -/*!< TOVLPC configuration */ -#define HSP_EVT_ICR_TOVLPC_Pos (28U) + +#define HSP_EVT_ICR_TOVLPC_Pos (28UL) #define HSP_EVT_ICR_TOVLPC_Msk (0x1UL << HSP_EVT_ICR_TOVLPC_Pos) /*!< 0x10000000 */ #define HSP_EVT_ICR_TOVLPC HSP_EVT_ICR_TOVLPC_Msk /*!< TOVLPC (Clear TOVLPF flag) */ -/*!< FPUSATC configuration */ -#define HSP_EVT_ICR_FPUSATC_Pos (31U) + +#define HSP_EVT_ICR_FPUSATC_Pos (31UL) #define HSP_EVT_ICR_FPUSATC_Msk (0x1UL << HSP_EVT_ICR_FPUSATC_Pos) /*!< 0x80000000 */ #define HSP_EVT_ICR_FPUSATC HSP_EVT_ICR_FPUSATC_Msk /*!< FPUSATC (Clear FPUSATF flag) */ /******************** Bit definition for HSP_PFCTEVT_ICR register ********************/ -/*!< PFCTC configuration */ -#define HSP_PFCTEVT_ICR_PFCTC_Pos (0U) +#define HSP_PFCTEVT_ICR_PFCTC_Pos (0UL) #define HSP_PFCTEVT_ICR_PFCTC_Msk (0xFFFFFFFFUL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0xFFFFFFFF */ #define HSP_PFCTEVT_ICR_PFCTC HSP_PFCTEVT_ICR_PFCTC_Msk /*!< PFCTC[31:0] bits (Clear PFCTF[31:0] flag) */ #define HSP_PFCTEVT_ICR_PFCTC_0 (0x00001UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000001 */ @@ -13415,358 +14011,29 @@ typedef struct #define HSP_PFCTEVT_ICR_PFCTC_31 (0x80000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_FWVERR register ********************/ -/*!< CROMINREV configuration */ -#define HSP_FWVERR_CROMINREV_Pos (0U) -#define HSP_FWVERR_CROMINREV_Msk (0xFUL << HSP_FWVERR_CROMINREV_Pos) /*!< 0x0000000F */ -#define HSP_FWVERR_CROMINREV HSP_FWVERR_CROMINREV_Msk /*!< CROMINREV[3:0] bits (Code ROM Minor revision) */ -#define HSP_FWVERR_CROMINREV_0 (0x01UL << HSP_FWVERR_CROMINREV_Pos) /*!< 0x00000001 */ -#define HSP_FWVERR_CROMINREV_1 (0x02UL << HSP_FWVERR_CROMINREV_Pos) /*!< 0x00000002 */ -#define HSP_FWVERR_CROMINREV_2 (0x04UL << HSP_FWVERR_CROMINREV_Pos) /*!< 0x00000004 */ -#define HSP_FWVERR_CROMINREV_3 (0x08UL << HSP_FWVERR_CROMINREV_Pos) /*!< 0x00000008 */ -/*!< CROMAJREV configuration */ -#define HSP_FWVERR_CROMAJREV_Pos (4U) -#define HSP_FWVERR_CROMAJREV_Msk (0xFUL << HSP_FWVERR_CROMAJREV_Pos) /*!< 0x000000F0 */ -#define HSP_FWVERR_CROMAJREV HSP_FWVERR_CROMAJREV_Msk /*!< CROMAJREV[3:0] bits (Code ROM Major revision) */ -#define HSP_FWVERR_CROMAJREV_0 (0x01UL << HSP_FWVERR_CROMAJREV_Pos) /*!< 0x00000010 */ -#define HSP_FWVERR_CROMAJREV_1 (0x02UL << HSP_FWVERR_CROMAJREV_Pos) /*!< 0x00000020 */ -#define HSP_FWVERR_CROMAJREV_2 (0x04UL << HSP_FWVERR_CROMAJREV_Pos) /*!< 0x00000040 */ -#define HSP_FWVERR_CROMAJREV_3 (0x08UL << HSP_FWVERR_CROMAJREV_Pos) /*!< 0x00000080 */ -/*!< CRAMINREV configuration */ -#define HSP_FWVERR_CRAMINREV_Pos (8U) -#define HSP_FWVERR_CRAMINREV_Msk (0xFUL << HSP_FWVERR_CRAMINREV_Pos) /*!< 0x00000F00 */ -#define HSP_FWVERR_CRAMINREV HSP_FWVERR_CRAMINREV_Msk /*!< CRAMINREV[3:0] bits (Code RAM Minor revision) */ -#define HSP_FWVERR_CRAMINREV_0 (0x01UL << HSP_FWVERR_CRAMINREV_Pos) /*!< 0x00000100 */ -#define HSP_FWVERR_CRAMINREV_1 (0x02UL << HSP_FWVERR_CRAMINREV_Pos) /*!< 0x00000200 */ -#define HSP_FWVERR_CRAMINREV_2 (0x04UL << HSP_FWVERR_CRAMINREV_Pos) /*!< 0x00000400 */ -#define HSP_FWVERR_CRAMINREV_3 (0x08UL << HSP_FWVERR_CRAMINREV_Pos) /*!< 0x00000800 */ -/*!< CRAMAJREV configuration */ -#define HSP_FWVERR_CRAMAJREV_Pos (12U) -#define HSP_FWVERR_CRAMAJREV_Msk (0xFUL << HSP_FWVERR_CRAMAJREV_Pos) /*!< 0x0000F000 */ +#define HSP_FWVERR_CRAMINREV_Pos (0UL) +#define HSP_FWVERR_CRAMINREV_Msk (0xFFUL << HSP_FWVERR_CRAMINREV_Pos) /*!< 0x000000FF */ +#define HSP_FWVERR_CRAMINREV HSP_FWVERR_CRAMINREV_Msk /*!< CRAMINREV[7:0] bits (Code RAM Minor revision) */ + +#define HSP_FWVERR_CRAMAJREV_Pos (8UL) +#define HSP_FWVERR_CRAMAJREV_Msk (0xFUL << HSP_FWVERR_CRAMAJREV_Pos) /*!< 0x00000F00 */ #define HSP_FWVERR_CRAMAJREV HSP_FWVERR_CRAMAJREV_Msk /*!< CRAMAJREV[3:0] bits (Code RAM Major revision) */ -#define HSP_FWVERR_CRAMAJREV_0 (0x01UL << HSP_FWVERR_CRAMAJREV_Pos) /*!< 0x00001000 */ -#define HSP_FWVERR_CRAMAJREV_1 (0x02UL << HSP_FWVERR_CRAMAJREV_Pos) /*!< 0x00002000 */ -#define HSP_FWVERR_CRAMAJREV_2 (0x04UL << HSP_FWVERR_CRAMAJREV_Pos) /*!< 0x00004000 */ -#define HSP_FWVERR_CRAMAJREV_3 (0x08UL << HSP_FWVERR_CRAMAJREV_Pos) /*!< 0x00008000 */ -/*!< DROMINREV configuration */ -#define HSP_FWVERR_DROMINREV_Pos (16U) -#define HSP_FWVERR_DROMINREV_Msk (0xFUL << HSP_FWVERR_DROMINREV_Pos) /*!< 0x000F0000 */ + +#define HSP_FWVERR_CROMINREV_Pos (12UL) +#define HSP_FWVERR_CROMINREV_Msk (0xFFUL << HSP_FWVERR_CROMINREV_Pos) /*!< 0x000FF000 */ +#define HSP_FWVERR_CROMINREV HSP_FWVERR_CROMINREV_Msk /*!< CROMINREV[7:0] bits (Code ROM Minor revision) */ + +#define HSP_FWVERR_CROMAJREV_Pos (20UL) +#define HSP_FWVERR_CROMAJREV_Msk (0xFUL << HSP_FWVERR_CROMAJREV_Pos) /*!< 0x000F0000 */ +#define HSP_FWVERR_CROMAJREV HSP_FWVERR_CROMAJREV_Msk /*!< CROMAJREV[3:0] bits (Code ROM Major revision) */ + +#define HSP_FWVERR_DROMINREV_Pos (24UL) +#define HSP_FWVERR_DROMINREV_Msk (0xFUL << HSP_FWVERR_DROMINREV_Pos) /*!< 0x00F00000 */ #define HSP_FWVERR_DROMINREV HSP_FWVERR_DROMINREV_Msk /*!< DROMINREV[3:0] bits (Data ROM Minor revision) */ -#define HSP_FWVERR_DROMINREV_0 (0x01UL << HSP_FWVERR_DROMINREV_Pos) /*!< 0x00010000 */ -#define HSP_FWVERR_DROMINREV_1 (0x02UL << HSP_FWVERR_DROMINREV_Pos) /*!< 0x00020000 */ -#define HSP_FWVERR_DROMINREV_2 (0x04UL << HSP_FWVERR_DROMINREV_Pos) /*!< 0x00040000 */ -#define HSP_FWVERR_DROMINREV_3 (0x08UL << HSP_FWVERR_DROMINREV_Pos) /*!< 0x00080000 */ -/*!< DROMAJREV configuration */ -#define HSP_FWVERR_DROMAJREV_Pos (20U) -#define HSP_FWVERR_DROMAJREV_Msk (0xFUL << HSP_FWVERR_DROMAJREV_Pos) /*!< 0x00F00000 */ + +#define HSP_FWVERR_DROMAJREV_Pos (28UL) +#define HSP_FWVERR_DROMAJREV_Msk (0xFUL << HSP_FWVERR_DROMAJREV_Pos) /*!< 0x0F000000 */ #define HSP_FWVERR_DROMAJREV HSP_FWVERR_DROMAJREV_Msk /*!< DROMAJREV[3:0] bits (Data ROM Major revision) */ -#define HSP_FWVERR_DROMAJREV_0 (0x01UL << HSP_FWVERR_DROMAJREV_Pos) /*!< 0x00100000 */ -#define HSP_FWVERR_DROMAJREV_1 (0x02UL << HSP_FWVERR_DROMAJREV_Pos) /*!< 0x00200000 */ -#define HSP_FWVERR_DROMAJREV_2 (0x04UL << HSP_FWVERR_DROMAJREV_Pos) /*!< 0x00400000 */ -#define HSP_FWVERR_DROMAJREV_3 (0x08UL << HSP_FWVERR_DROMAJREV_Pos) /*!< 0x00800000 */ - -/******************** Bit definition for HSP_SPEVERR register ********************/ -/*!< SPEVER configuration */ -#define HSP_SPEVERR_SPEVER_Pos (0U) -#define HSP_SPEVERR_SPEVER_Msk (0xFFFFFFFFUL << HSP_SPEVERR_SPEVER_Pos) /*!< 0xFFFFFFFF */ -#define HSP_SPEVERR_SPEVER HSP_SPEVERR_SPEVER_Msk /*!< SPEVER[31:0] bits (SPE version ) */ -#define HSP_SPEVERR_SPEVER_0 (0x00001UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00000001 */ -#define HSP_SPEVERR_SPEVER_1 (0x00002UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00000002 */ -#define HSP_SPEVERR_SPEVER_2 (0x00004UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00000004 */ -#define HSP_SPEVERR_SPEVER_3 (0x00008UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00000008 */ -#define HSP_SPEVERR_SPEVER_4 (0x00010UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00000010 */ -#define HSP_SPEVERR_SPEVER_5 (0x00020UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00000020 */ -#define HSP_SPEVERR_SPEVER_6 (0x00040UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00000040 */ -#define HSP_SPEVERR_SPEVER_7 (0x00080UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00000080 */ -#define HSP_SPEVERR_SPEVER_8 (0x00100UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00000100 */ -#define HSP_SPEVERR_SPEVER_9 (0x00200UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00000200 */ -#define HSP_SPEVERR_SPEVER_10 (0x00400UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00000400 */ -#define HSP_SPEVERR_SPEVER_11 (0x00800UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00000800 */ -#define HSP_SPEVERR_SPEVER_12 (0x01000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00001000 */ -#define HSP_SPEVERR_SPEVER_13 (0x02000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00002000 */ -#define HSP_SPEVERR_SPEVER_14 (0x04000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00004000 */ -#define HSP_SPEVERR_SPEVER_15 (0x08000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00008000 */ -#define HSP_SPEVERR_SPEVER_16 (0x10000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00010000 */ -#define HSP_SPEVERR_SPEVER_17 (0x20000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00020000 */ -#define HSP_SPEVERR_SPEVER_18 (0x40000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00040000 */ -#define HSP_SPEVERR_SPEVER_19 (0x80000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00080000 */ -#define HSP_SPEVERR_SPEVER_20 (0x100000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00100000 */ -#define HSP_SPEVERR_SPEVER_21 (0x200000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00200000 */ -#define HSP_SPEVERR_SPEVER_22 (0x400000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00400000 */ -#define HSP_SPEVERR_SPEVER_23 (0x800000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00800000 */ -#define HSP_SPEVERR_SPEVER_24 (0x1000000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x01000000 */ -#define HSP_SPEVERR_SPEVER_25 (0x2000000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x02000000 */ -#define HSP_SPEVERR_SPEVER_26 (0x4000000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x04000000 */ -#define HSP_SPEVERR_SPEVER_27 (0x8000000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x08000000 */ -#define HSP_SPEVERR_SPEVER_28 (0x10000000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x10000000 */ -#define HSP_SPEVERR_SPEVER_29 (0x20000000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x20000000 */ -#define HSP_SPEVERR_SPEVER_30 (0x40000000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x40000000 */ -#define HSP_SPEVERR_SPEVER_31 (0x80000000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for HSP_HWCFGR4 register ********************/ -/*!< NUM_DMA_REQ configuration */ -#define HSP_HWCFGR4_NUM_DMA_REQ_Pos (0U) -#define HSP_HWCFGR4_NUM_DMA_REQ_Msk (0xFFUL << HSP_HWCFGR4_NUM_DMA_REQ_Pos) /*!< 0x000000FF */ -#define HSP_HWCFGR4_NUM_DMA_REQ HSP_HWCFGR4_NUM_DMA_REQ_Msk /*!< NUM_DMA_REQ[7:0] bits (Number of DMA request supported) */ -#define HSP_HWCFGR4_NUM_DMA_REQ_0 (0x001UL << HSP_HWCFGR4_NUM_DMA_REQ_Pos) /*!< 0x00000001 */ -#define HSP_HWCFGR4_NUM_DMA_REQ_1 (0x002UL << HSP_HWCFGR4_NUM_DMA_REQ_Pos) /*!< 0x00000002 */ -#define HSP_HWCFGR4_NUM_DMA_REQ_2 (0x004UL << HSP_HWCFGR4_NUM_DMA_REQ_Pos) /*!< 0x00000004 */ -#define HSP_HWCFGR4_NUM_DMA_REQ_3 (0x008UL << HSP_HWCFGR4_NUM_DMA_REQ_Pos) /*!< 0x00000008 */ -#define HSP_HWCFGR4_NUM_DMA_REQ_4 (0x010UL << HSP_HWCFGR4_NUM_DMA_REQ_Pos) /*!< 0x00000010 */ -#define HSP_HWCFGR4_NUM_DMA_REQ_5 (0x020UL << HSP_HWCFGR4_NUM_DMA_REQ_Pos) /*!< 0x00000020 */ -#define HSP_HWCFGR4_NUM_DMA_REQ_6 (0x040UL << HSP_HWCFGR4_NUM_DMA_REQ_Pos) /*!< 0x00000040 */ -#define HSP_HWCFGR4_NUM_DMA_REQ_7 (0x080UL << HSP_HWCFGR4_NUM_DMA_REQ_Pos) /*!< 0x00000080 */ -/*!< NO_DMA_STI configuration */ -#define HSP_HWCFGR4_NO_DMA_STI_Pos (8U) -#define HSP_HWCFGR4_NO_DMA_STI_Msk (0xFUL << HSP_HWCFGR4_NO_DMA_STI_Pos) /*!< 0x00000F00 */ -#define HSP_HWCFGR4_NO_DMA_STI HSP_HWCFGR4_NO_DMA_STI_Msk /*!< NO_DMA_STI[3:0] bits (HSPDMA and STI implementation) */ -#define HSP_HWCFGR4_NO_DMA_STI_0 (0x01UL << HSP_HWCFGR4_NO_DMA_STI_Pos) /*!< 0x00000100 */ -#define HSP_HWCFGR4_NO_DMA_STI_1 (0x02UL << HSP_HWCFGR4_NO_DMA_STI_Pos) /*!< 0x00000200 */ -#define HSP_HWCFGR4_NO_DMA_STI_2 (0x04UL << HSP_HWCFGR4_NO_DMA_STI_Pos) /*!< 0x00000400 */ -#define HSP_HWCFGR4_NO_DMA_STI_3 (0x08UL << HSP_HWCFGR4_NO_DMA_STI_Pos) /*!< 0x00000800 */ - -/******************** Bit definition for HSP_HWCFGR3 register ********************/ -/*!< NUM_STIAP configuration */ -#define HSP_HWCFGR3_NUM_STIAP_Pos (0U) -#define HSP_HWCFGR3_NUM_STIAP_Msk (0xFUL << HSP_HWCFGR3_NUM_STIAP_Pos) /*!< 0x0000000F */ -#define HSP_HWCFGR3_NUM_STIAP HSP_HWCFGR3_NUM_STIAP_Msk /*!< NUM_STIAP[3:0] bits (Number of STI_AP ports) */ -#define HSP_HWCFGR3_NUM_STIAP_0 (0x01UL << HSP_HWCFGR3_NUM_STIAP_Pos) /*!< 0x00000001 */ -#define HSP_HWCFGR3_NUM_STIAP_1 (0x02UL << HSP_HWCFGR3_NUM_STIAP_Pos) /*!< 0x00000002 */ -#define HSP_HWCFGR3_NUM_STIAP_2 (0x04UL << HSP_HWCFGR3_NUM_STIAP_Pos) /*!< 0x00000004 */ -#define HSP_HWCFGR3_NUM_STIAP_3 (0x08UL << HSP_HWCFGR3_NUM_STIAP_Pos) /*!< 0x00000008 */ -/*!< NUM_STIHP configuration */ -#define HSP_HWCFGR3_NUM_STIHP_Pos (4U) -#define HSP_HWCFGR3_NUM_STIHP_Msk (0xFUL << HSP_HWCFGR3_NUM_STIHP_Pos) /*!< 0x000000F0 */ -#define HSP_HWCFGR3_NUM_STIHP HSP_HWCFGR3_NUM_STIHP_Msk /*!< NUM_STIHP[3:0] bits (Number of STI_HP ports) */ -#define HSP_HWCFGR3_NUM_STIHP_0 (0x01UL << HSP_HWCFGR3_NUM_STIHP_Pos) /*!< 0x00000010 */ -#define HSP_HWCFGR3_NUM_STIHP_1 (0x02UL << HSP_HWCFGR3_NUM_STIHP_Pos) /*!< 0x00000020 */ -#define HSP_HWCFGR3_NUM_STIHP_2 (0x04UL << HSP_HWCFGR3_NUM_STIHP_Pos) /*!< 0x00000040 */ -#define HSP_HWCFGR3_NUM_STIHP_3 (0x08UL << HSP_HWCFGR3_NUM_STIHP_Pos) /*!< 0x00000080 */ -/*!< NUM_TRIG configuration */ -#define HSP_HWCFGR3_NUM_TRIG_Pos (8U) -#define HSP_HWCFGR3_NUM_TRIG_Msk (0xFFUL << HSP_HWCFGR3_NUM_TRIG_Pos) /*!< 0x0000FF00 */ -#define HSP_HWCFGR3_NUM_TRIG HSP_HWCFGR3_NUM_TRIG_Msk /*!< NUM_TRIG[7:0] bits (Number of trigger inputs) */ -#define HSP_HWCFGR3_NUM_TRIG_0 (0x001UL << HSP_HWCFGR3_NUM_TRIG_Pos) /*!< 0x00000100 */ -#define HSP_HWCFGR3_NUM_TRIG_1 (0x002UL << HSP_HWCFGR3_NUM_TRIG_Pos) /*!< 0x00000200 */ -#define HSP_HWCFGR3_NUM_TRIG_2 (0x004UL << HSP_HWCFGR3_NUM_TRIG_Pos) /*!< 0x00000400 */ -#define HSP_HWCFGR3_NUM_TRIG_3 (0x008UL << HSP_HWCFGR3_NUM_TRIG_Pos) /*!< 0x00000800 */ -#define HSP_HWCFGR3_NUM_TRIG_4 (0x010UL << HSP_HWCFGR3_NUM_TRIG_Pos) /*!< 0x00001000 */ -#define HSP_HWCFGR3_NUM_TRIG_5 (0x020UL << HSP_HWCFGR3_NUM_TRIG_Pos) /*!< 0x00002000 */ -#define HSP_HWCFGR3_NUM_TRIG_6 (0x040UL << HSP_HWCFGR3_NUM_TRIG_Pos) /*!< 0x00004000 */ -#define HSP_HWCFGR3_NUM_TRIG_7 (0x080UL << HSP_HWCFGR3_NUM_TRIG_Pos) /*!< 0x00008000 */ -/*!< NUM_TSK_MAX configuration */ -#define HSP_HWCFGR3_NUM_TSK_MAX_Pos (16U) -#define HSP_HWCFGR3_NUM_TSK_MAX_Msk (0xFFUL << HSP_HWCFGR3_NUM_TSK_MAX_Pos) /*!< 0x00FF0000 */ -#define HSP_HWCFGR3_NUM_TSK_MAX HSP_HWCFGR3_NUM_TSK_MAX_Msk /*!< NUM_TSK_MAX[7:0] bits (Maximum number of tasks supported) */ -#define HSP_HWCFGR3_NUM_TSK_MAX_0 (0x001UL << HSP_HWCFGR3_NUM_TSK_MAX_Pos) /*!< 0x00010000 */ -#define HSP_HWCFGR3_NUM_TSK_MAX_1 (0x002UL << HSP_HWCFGR3_NUM_TSK_MAX_Pos) /*!< 0x00020000 */ -#define HSP_HWCFGR3_NUM_TSK_MAX_2 (0x004UL << HSP_HWCFGR3_NUM_TSK_MAX_Pos) /*!< 0x00040000 */ -#define HSP_HWCFGR3_NUM_TSK_MAX_3 (0x008UL << HSP_HWCFGR3_NUM_TSK_MAX_Pos) /*!< 0x00080000 */ -#define HSP_HWCFGR3_NUM_TSK_MAX_4 (0x010UL << HSP_HWCFGR3_NUM_TSK_MAX_Pos) /*!< 0x00100000 */ -#define HSP_HWCFGR3_NUM_TSK_MAX_5 (0x020UL << HSP_HWCFGR3_NUM_TSK_MAX_Pos) /*!< 0x00200000 */ -#define HSP_HWCFGR3_NUM_TSK_MAX_6 (0x040UL << HSP_HWCFGR3_NUM_TSK_MAX_Pos) /*!< 0x00400000 */ -#define HSP_HWCFGR3_NUM_TSK_MAX_7 (0x080UL << HSP_HWCFGR3_NUM_TSK_MAX_Pos) /*!< 0x00800000 */ -/*!< TSK_OFF_SIZE configuration */ -#define HSP_HWCFGR3_TSK_OFF_SIZE_Pos (24U) -#define HSP_HWCFGR3_TSK_OFF_SIZE_Msk (0xFUL << HSP_HWCFGR3_TSK_OFF_SIZE_Pos) /*!< 0x0F000000 */ -#define HSP_HWCFGR3_TSK_OFF_SIZE HSP_HWCFGR3_TSK_OFF_SIZE_Msk /*!< TSK_OFF_SIZE[3:0] bits (Size of task offset values) */ -#define HSP_HWCFGR3_TSK_OFF_SIZE_0 (0x01UL << HSP_HWCFGR3_TSK_OFF_SIZE_Pos) /*!< 0x01000000 */ -#define HSP_HWCFGR3_TSK_OFF_SIZE_1 (0x02UL << HSP_HWCFGR3_TSK_OFF_SIZE_Pos) /*!< 0x02000000 */ -#define HSP_HWCFGR3_TSK_OFF_SIZE_2 (0x04UL << HSP_HWCFGR3_TSK_OFF_SIZE_Pos) /*!< 0x04000000 */ -#define HSP_HWCFGR3_TSK_OFF_SIZE_3 (0x08UL << HSP_HWCFGR3_TSK_OFF_SIZE_Pos) /*!< 0x08000000 */ -/*!< NUM_ADC configuration */ -#define HSP_HWCFGR3_NUM_ADC_Pos (28U) -#define HSP_HWCFGR3_NUM_ADC_Msk (0xFUL << HSP_HWCFGR3_NUM_ADC_Pos) /*!< 0xF0000000 */ -#define HSP_HWCFGR3_NUM_ADC HSP_HWCFGR3_NUM_ADC_Msk /*!< NUM_ADC[3:0] bits (Number of ADC parallel interfaces) */ -#define HSP_HWCFGR3_NUM_ADC_0 (0x01UL << HSP_HWCFGR3_NUM_ADC_Pos) /*!< 0x10000000 */ -#define HSP_HWCFGR3_NUM_ADC_1 (0x02UL << HSP_HWCFGR3_NUM_ADC_Pos) /*!< 0x20000000 */ -#define HSP_HWCFGR3_NUM_ADC_2 (0x04UL << HSP_HWCFGR3_NUM_ADC_Pos) /*!< 0x40000000 */ -#define HSP_HWCFGR3_NUM_ADC_3 (0x08UL << HSP_HWCFGR3_NUM_ADC_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for HSP_HWCFGR2 register ********************/ -/*!< OPTION_REGOUT configuration */ -#define HSP_HWCFGR2_OPTION_REGOUT_Pos (0U) -#define HSP_HWCFGR2_OPTION_REGOUT_Msk (0xFFUL << HSP_HWCFGR2_OPTION_REGOUT_Pos) /*!< 0x000000FF */ -#define HSP_HWCFGR2_OPTION_REGOUT HSP_HWCFGR2_OPTION_REGOUT_Msk /*!< OPTION_REGOUT[7:0] bits (Support of HSP_OR register) */ -#define HSP_HWCFGR2_OPTION_REGOUT_0 (0x001UL << HSP_HWCFGR2_OPTION_REGOUT_Pos) /*!< 0x00000001 */ -#define HSP_HWCFGR2_OPTION_REGOUT_1 (0x002UL << HSP_HWCFGR2_OPTION_REGOUT_Pos) /*!< 0x00000002 */ -#define HSP_HWCFGR2_OPTION_REGOUT_2 (0x004UL << HSP_HWCFGR2_OPTION_REGOUT_Pos) /*!< 0x00000004 */ -#define HSP_HWCFGR2_OPTION_REGOUT_3 (0x008UL << HSP_HWCFGR2_OPTION_REGOUT_Pos) /*!< 0x00000008 */ -#define HSP_HWCFGR2_OPTION_REGOUT_4 (0x010UL << HSP_HWCFGR2_OPTION_REGOUT_Pos) /*!< 0x00000010 */ -#define HSP_HWCFGR2_OPTION_REGOUT_5 (0x020UL << HSP_HWCFGR2_OPTION_REGOUT_Pos) /*!< 0x00000020 */ -#define HSP_HWCFGR2_OPTION_REGOUT_6 (0x040UL << HSP_HWCFGR2_OPTION_REGOUT_Pos) /*!< 0x00000040 */ -#define HSP_HWCFGR2_OPTION_REGOUT_7 (0x080UL << HSP_HWCFGR2_OPTION_REGOUT_Pos) /*!< 0x00000080 */ -/*!< NUM_RESYNC_FFS configuration */ -#define HSP_HWCFGR2_NUM_RESYNC_FFS_Pos (8U) -#define HSP_HWCFGR2_NUM_RESYNC_FFS_Msk (0xFUL << HSP_HWCFGR2_NUM_RESYNC_FFS_Pos) /*!< 0x00000F00 */ -#define HSP_HWCFGR2_NUM_RESYNC_FFS HSP_HWCFGR2_NUM_RESYNC_FFS_Msk /*!< NUM_RESYNC_FFS[3:0] bits (Number of resynchronization flops for Clock Domain Crossing synchronizers.) */ -#define HSP_HWCFGR2_NUM_RESYNC_FFS_0 (0x01UL << HSP_HWCFGR2_NUM_RESYNC_FFS_Pos) /*!< 0x00000100 */ -#define HSP_HWCFGR2_NUM_RESYNC_FFS_1 (0x02UL << HSP_HWCFGR2_NUM_RESYNC_FFS_Pos) /*!< 0x00000200 */ -#define HSP_HWCFGR2_NUM_RESYNC_FFS_2 (0x04UL << HSP_HWCFGR2_NUM_RESYNC_FFS_Pos) /*!< 0x00000400 */ -#define HSP_HWCFGR2_NUM_RESYNC_FFS_3 (0x08UL << HSP_HWCFGR2_NUM_RESYNC_FFS_Pos) /*!< 0x00000800 */ -/*!< DROM_SIZE configuration */ -#define HSP_HWCFGR2_DROM_SIZE_Pos (16U) -#define HSP_HWCFGR2_DROM_SIZE_Msk (0xFFUL << HSP_HWCFGR2_DROM_SIZE_Pos) /*!< 0x00FF0000 */ -#define HSP_HWCFGR2_DROM_SIZE HSP_HWCFGR2_DROM_SIZE_Msk /*!< DROM_SIZE[7:0] bits (DROM Size) */ -#define HSP_HWCFGR2_DROM_SIZE_0 (0x001UL << HSP_HWCFGR2_DROM_SIZE_Pos) /*!< 0x00010000 */ -#define HSP_HWCFGR2_DROM_SIZE_1 (0x002UL << HSP_HWCFGR2_DROM_SIZE_Pos) /*!< 0x00020000 */ -#define HSP_HWCFGR2_DROM_SIZE_2 (0x004UL << HSP_HWCFGR2_DROM_SIZE_Pos) /*!< 0x00040000 */ -#define HSP_HWCFGR2_DROM_SIZE_3 (0x008UL << HSP_HWCFGR2_DROM_SIZE_Pos) /*!< 0x00080000 */ -#define HSP_HWCFGR2_DROM_SIZE_4 (0x010UL << HSP_HWCFGR2_DROM_SIZE_Pos) /*!< 0x00100000 */ -#define HSP_HWCFGR2_DROM_SIZE_5 (0x020UL << HSP_HWCFGR2_DROM_SIZE_Pos) /*!< 0x00200000 */ -#define HSP_HWCFGR2_DROM_SIZE_6 (0x040UL << HSP_HWCFGR2_DROM_SIZE_Pos) /*!< 0x00400000 */ -#define HSP_HWCFGR2_DROM_SIZE_7 (0x080UL << HSP_HWCFGR2_DROM_SIZE_Pos) /*!< 0x00800000 */ -/*!< CROM_SIZE configuration */ -#define HSP_HWCFGR2_CROM_SIZE_Pos (24U) -#define HSP_HWCFGR2_CROM_SIZE_Msk (0xFFUL << HSP_HWCFGR2_CROM_SIZE_Pos) /*!< 0xFF000000 */ -#define HSP_HWCFGR2_CROM_SIZE HSP_HWCFGR2_CROM_SIZE_Msk /*!< CROM_SIZE[7:0] bits (CROM Size) */ -#define HSP_HWCFGR2_CROM_SIZE_0 (0x001UL << HSP_HWCFGR2_CROM_SIZE_Pos) /*!< 0x01000000 */ -#define HSP_HWCFGR2_CROM_SIZE_1 (0x002UL << HSP_HWCFGR2_CROM_SIZE_Pos) /*!< 0x02000000 */ -#define HSP_HWCFGR2_CROM_SIZE_2 (0x004UL << HSP_HWCFGR2_CROM_SIZE_Pos) /*!< 0x04000000 */ -#define HSP_HWCFGR2_CROM_SIZE_3 (0x008UL << HSP_HWCFGR2_CROM_SIZE_Pos) /*!< 0x08000000 */ -#define HSP_HWCFGR2_CROM_SIZE_4 (0x010UL << HSP_HWCFGR2_CROM_SIZE_Pos) /*!< 0x10000000 */ -#define HSP_HWCFGR2_CROM_SIZE_5 (0x020UL << HSP_HWCFGR2_CROM_SIZE_Pos) /*!< 0x20000000 */ -#define HSP_HWCFGR2_CROM_SIZE_6 (0x040UL << HSP_HWCFGR2_CROM_SIZE_Pos) /*!< 0x40000000 */ -#define HSP_HWCFGR2_CROM_SIZE_7 (0x080UL << HSP_HWCFGR2_CROM_SIZE_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for HSP_HWCFGR1 register ********************/ -/*!< BRAM_SIZE configuration */ -#define HSP_HWCFGR1_BRAM_SIZE_Pos (0U) -#define HSP_HWCFGR1_BRAM_SIZE_Msk (0xFFFFUL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x0000FFFF */ -#define HSP_HWCFGR1_BRAM_SIZE HSP_HWCFGR1_BRAM_SIZE_Msk /*!< BRAM_SIZE[15:0] bits (BRAM size) */ -#define HSP_HWCFGR1_BRAM_SIZE_0 (0x0001UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00000001 */ -#define HSP_HWCFGR1_BRAM_SIZE_1 (0x0002UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00000002 */ -#define HSP_HWCFGR1_BRAM_SIZE_2 (0x0004UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00000004 */ -#define HSP_HWCFGR1_BRAM_SIZE_3 (0x0008UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00000008 */ -#define HSP_HWCFGR1_BRAM_SIZE_4 (0x0010UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00000010 */ -#define HSP_HWCFGR1_BRAM_SIZE_5 (0x0020UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00000020 */ -#define HSP_HWCFGR1_BRAM_SIZE_6 (0x0040UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00000040 */ -#define HSP_HWCFGR1_BRAM_SIZE_7 (0x0080UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00000080 */ -#define HSP_HWCFGR1_BRAM_SIZE_8 (0x0100UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00000100 */ -#define HSP_HWCFGR1_BRAM_SIZE_9 (0x0200UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00000200 */ -#define HSP_HWCFGR1_BRAM_SIZE_10 (0x0400UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00000400 */ -#define HSP_HWCFGR1_BRAM_SIZE_11 (0x0800UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00000800 */ -#define HSP_HWCFGR1_BRAM_SIZE_12 (0x1000UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00001000 */ -#define HSP_HWCFGR1_BRAM_SIZE_13 (0x2000UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00002000 */ -#define HSP_HWCFGR1_BRAM_SIZE_14 (0x4000UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00004000 */ -#define HSP_HWCFGR1_BRAM_SIZE_15 (0x8000UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00008000 */ -/*!< DRAM_SIZE configuration */ -#define HSP_HWCFGR1_DRAM_SIZE_Pos (16U) -#define HSP_HWCFGR1_DRAM_SIZE_Msk (0xFFUL << HSP_HWCFGR1_DRAM_SIZE_Pos) /*!< 0x00FF0000 */ -#define HSP_HWCFGR1_DRAM_SIZE HSP_HWCFGR1_DRAM_SIZE_Msk /*!< DRAM_SIZE[7:0] bits (DRAM Size) */ -#define HSP_HWCFGR1_DRAM_SIZE_0 (0x001UL << HSP_HWCFGR1_DRAM_SIZE_Pos) /*!< 0x00010000 */ -#define HSP_HWCFGR1_DRAM_SIZE_1 (0x002UL << HSP_HWCFGR1_DRAM_SIZE_Pos) /*!< 0x00020000 */ -#define HSP_HWCFGR1_DRAM_SIZE_2 (0x004UL << HSP_HWCFGR1_DRAM_SIZE_Pos) /*!< 0x00040000 */ -#define HSP_HWCFGR1_DRAM_SIZE_3 (0x008UL << HSP_HWCFGR1_DRAM_SIZE_Pos) /*!< 0x00080000 */ -#define HSP_HWCFGR1_DRAM_SIZE_4 (0x010UL << HSP_HWCFGR1_DRAM_SIZE_Pos) /*!< 0x00100000 */ -#define HSP_HWCFGR1_DRAM_SIZE_5 (0x020UL << HSP_HWCFGR1_DRAM_SIZE_Pos) /*!< 0x00200000 */ -#define HSP_HWCFGR1_DRAM_SIZE_6 (0x040UL << HSP_HWCFGR1_DRAM_SIZE_Pos) /*!< 0x00400000 */ -#define HSP_HWCFGR1_DRAM_SIZE_7 (0x080UL << HSP_HWCFGR1_DRAM_SIZE_Pos) /*!< 0x00800000 */ -/*!< CRAM_SIZE configuration */ -#define HSP_HWCFGR1_CRAM_SIZE_Pos (24U) -#define HSP_HWCFGR1_CRAM_SIZE_Msk (0xFFUL << HSP_HWCFGR1_CRAM_SIZE_Pos) /*!< 0xFF000000 */ -#define HSP_HWCFGR1_CRAM_SIZE HSP_HWCFGR1_CRAM_SIZE_Msk /*!< CRAM_SIZE[7:0] bits (CRAM Size) */ -#define HSP_HWCFGR1_CRAM_SIZE_0 (0x001UL << HSP_HWCFGR1_CRAM_SIZE_Pos) /*!< 0x01000000 */ -#define HSP_HWCFGR1_CRAM_SIZE_1 (0x002UL << HSP_HWCFGR1_CRAM_SIZE_Pos) /*!< 0x02000000 */ -#define HSP_HWCFGR1_CRAM_SIZE_2 (0x004UL << HSP_HWCFGR1_CRAM_SIZE_Pos) /*!< 0x04000000 */ -#define HSP_HWCFGR1_CRAM_SIZE_3 (0x008UL << HSP_HWCFGR1_CRAM_SIZE_Pos) /*!< 0x08000000 */ -#define HSP_HWCFGR1_CRAM_SIZE_4 (0x010UL << HSP_HWCFGR1_CRAM_SIZE_Pos) /*!< 0x10000000 */ -#define HSP_HWCFGR1_CRAM_SIZE_5 (0x020UL << HSP_HWCFGR1_CRAM_SIZE_Pos) /*!< 0x20000000 */ -#define HSP_HWCFGR1_CRAM_SIZE_6 (0x040UL << HSP_HWCFGR1_CRAM_SIZE_Pos) /*!< 0x40000000 */ -#define HSP_HWCFGR1_CRAM_SIZE_7 (0x080UL << HSP_HWCFGR1_CRAM_SIZE_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for HSP_VERR register ********************/ -/*!< MINREV configuration */ -#define HSP_VERR_MINREV_Pos (0U) -#define HSP_VERR_MINREV_Msk (0xFUL << HSP_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define HSP_VERR_MINREV HSP_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */ -#define HSP_VERR_MINREV_0 (0x01UL << HSP_VERR_MINREV_Pos) /*!< 0x00000001 */ -#define HSP_VERR_MINREV_1 (0x02UL << HSP_VERR_MINREV_Pos) /*!< 0x00000002 */ -#define HSP_VERR_MINREV_2 (0x04UL << HSP_VERR_MINREV_Pos) /*!< 0x00000004 */ -#define HSP_VERR_MINREV_3 (0x08UL << HSP_VERR_MINREV_Pos) /*!< 0x00000008 */ -/*!< MAJREV configuration */ -#define HSP_VERR_MAJREV_Pos (4U) -#define HSP_VERR_MAJREV_Msk (0xFUL << HSP_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define HSP_VERR_MAJREV HSP_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */ -#define HSP_VERR_MAJREV_0 (0x01UL << HSP_VERR_MAJREV_Pos) /*!< 0x00000010 */ -#define HSP_VERR_MAJREV_1 (0x02UL << HSP_VERR_MAJREV_Pos) /*!< 0x00000020 */ -#define HSP_VERR_MAJREV_2 (0x04UL << HSP_VERR_MAJREV_Pos) /*!< 0x00000040 */ -#define HSP_VERR_MAJREV_3 (0x08UL << HSP_VERR_MAJREV_Pos) /*!< 0x00000080 */ - -/******************** Bit definition for HSP_IPIDR register ********************/ -/*!< ID configuration */ -#define HSP_IPIDR_ID_Pos (0U) -#define HSP_IPIDR_ID_Msk (0xFFFFFFFFUL << HSP_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */ -#define HSP_IPIDR_ID HSP_IPIDR_ID_Msk /*!< ID[31:0] bits (HSP identifier) */ -#define HSP_IPIDR_ID_0 (0x00001UL << HSP_IPIDR_ID_Pos) /*!< 0x00000001 */ -#define HSP_IPIDR_ID_1 (0x00002UL << HSP_IPIDR_ID_Pos) /*!< 0x00000002 */ -#define HSP_IPIDR_ID_2 (0x00004UL << HSP_IPIDR_ID_Pos) /*!< 0x00000004 */ -#define HSP_IPIDR_ID_3 (0x00008UL << HSP_IPIDR_ID_Pos) /*!< 0x00000008 */ -#define HSP_IPIDR_ID_4 (0x00010UL << HSP_IPIDR_ID_Pos) /*!< 0x00000010 */ -#define HSP_IPIDR_ID_5 (0x00020UL << HSP_IPIDR_ID_Pos) /*!< 0x00000020 */ -#define HSP_IPIDR_ID_6 (0x00040UL << HSP_IPIDR_ID_Pos) /*!< 0x00000040 */ -#define HSP_IPIDR_ID_7 (0x00080UL << HSP_IPIDR_ID_Pos) /*!< 0x00000080 */ -#define HSP_IPIDR_ID_8 (0x00100UL << HSP_IPIDR_ID_Pos) /*!< 0x00000100 */ -#define HSP_IPIDR_ID_9 (0x00200UL << HSP_IPIDR_ID_Pos) /*!< 0x00000200 */ -#define HSP_IPIDR_ID_10 (0x00400UL << HSP_IPIDR_ID_Pos) /*!< 0x00000400 */ -#define HSP_IPIDR_ID_11 (0x00800UL << HSP_IPIDR_ID_Pos) /*!< 0x00000800 */ -#define HSP_IPIDR_ID_12 (0x01000UL << HSP_IPIDR_ID_Pos) /*!< 0x00001000 */ -#define HSP_IPIDR_ID_13 (0x02000UL << HSP_IPIDR_ID_Pos) /*!< 0x00002000 */ -#define HSP_IPIDR_ID_14 (0x04000UL << HSP_IPIDR_ID_Pos) /*!< 0x00004000 */ -#define HSP_IPIDR_ID_15 (0x08000UL << HSP_IPIDR_ID_Pos) /*!< 0x00008000 */ -#define HSP_IPIDR_ID_16 (0x10000UL << HSP_IPIDR_ID_Pos) /*!< 0x00010000 */ -#define HSP_IPIDR_ID_17 (0x20000UL << HSP_IPIDR_ID_Pos) /*!< 0x00020000 */ -#define HSP_IPIDR_ID_18 (0x40000UL << HSP_IPIDR_ID_Pos) /*!< 0x00040000 */ -#define HSP_IPIDR_ID_19 (0x80000UL << HSP_IPIDR_ID_Pos) /*!< 0x00080000 */ -#define HSP_IPIDR_ID_20 (0x100000UL << HSP_IPIDR_ID_Pos) /*!< 0x00100000 */ -#define HSP_IPIDR_ID_21 (0x200000UL << HSP_IPIDR_ID_Pos) /*!< 0x00200000 */ -#define HSP_IPIDR_ID_22 (0x400000UL << HSP_IPIDR_ID_Pos) /*!< 0x00400000 */ -#define HSP_IPIDR_ID_23 (0x800000UL << HSP_IPIDR_ID_Pos) /*!< 0x00800000 */ -#define HSP_IPIDR_ID_24 (0x1000000UL << HSP_IPIDR_ID_Pos) /*!< 0x01000000 */ -#define HSP_IPIDR_ID_25 (0x2000000UL << HSP_IPIDR_ID_Pos) /*!< 0x02000000 */ -#define HSP_IPIDR_ID_26 (0x4000000UL << HSP_IPIDR_ID_Pos) /*!< 0x04000000 */ -#define HSP_IPIDR_ID_27 (0x8000000UL << HSP_IPIDR_ID_Pos) /*!< 0x08000000 */ -#define HSP_IPIDR_ID_28 (0x10000000UL << HSP_IPIDR_ID_Pos) /*!< 0x10000000 */ -#define HSP_IPIDR_ID_29 (0x20000000UL << HSP_IPIDR_ID_Pos) /*!< 0x20000000 */ -#define HSP_IPIDR_ID_30 (0x40000000UL << HSP_IPIDR_ID_Pos) /*!< 0x40000000 */ -#define HSP_IPIDR_ID_31 (0x80000000UL << HSP_IPIDR_ID_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for HSP_SIDR register ********************/ -/*!< SID configuration */ -#define HSP_SIDR_SID_Pos (0U) -#define HSP_SIDR_SID_Msk (0xFFFFFFFFUL << HSP_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ -#define HSP_SIDR_SID HSP_SIDR_SID_Msk /*!< SID[31:0] bits (Size identification) */ -#define HSP_SIDR_SID_0 (0x00001UL << HSP_SIDR_SID_Pos) /*!< 0x00000001 */ -#define HSP_SIDR_SID_1 (0x00002UL << HSP_SIDR_SID_Pos) /*!< 0x00000002 */ -#define HSP_SIDR_SID_2 (0x00004UL << HSP_SIDR_SID_Pos) /*!< 0x00000004 */ -#define HSP_SIDR_SID_3 (0x00008UL << HSP_SIDR_SID_Pos) /*!< 0x00000008 */ -#define HSP_SIDR_SID_4 (0x00010UL << HSP_SIDR_SID_Pos) /*!< 0x00000010 */ -#define HSP_SIDR_SID_5 (0x00020UL << HSP_SIDR_SID_Pos) /*!< 0x00000020 */ -#define HSP_SIDR_SID_6 (0x00040UL << HSP_SIDR_SID_Pos) /*!< 0x00000040 */ -#define HSP_SIDR_SID_7 (0x00080UL << HSP_SIDR_SID_Pos) /*!< 0x00000080 */ -#define HSP_SIDR_SID_8 (0x00100UL << HSP_SIDR_SID_Pos) /*!< 0x00000100 */ -#define HSP_SIDR_SID_9 (0x00200UL << HSP_SIDR_SID_Pos) /*!< 0x00000200 */ -#define HSP_SIDR_SID_10 (0x00400UL << HSP_SIDR_SID_Pos) /*!< 0x00000400 */ -#define HSP_SIDR_SID_11 (0x00800UL << HSP_SIDR_SID_Pos) /*!< 0x00000800 */ -#define HSP_SIDR_SID_12 (0x01000UL << HSP_SIDR_SID_Pos) /*!< 0x00001000 */ -#define HSP_SIDR_SID_13 (0x02000UL << HSP_SIDR_SID_Pos) /*!< 0x00002000 */ -#define HSP_SIDR_SID_14 (0x04000UL << HSP_SIDR_SID_Pos) /*!< 0x00004000 */ -#define HSP_SIDR_SID_15 (0x08000UL << HSP_SIDR_SID_Pos) /*!< 0x00008000 */ -#define HSP_SIDR_SID_16 (0x10000UL << HSP_SIDR_SID_Pos) /*!< 0x00010000 */ -#define HSP_SIDR_SID_17 (0x20000UL << HSP_SIDR_SID_Pos) /*!< 0x00020000 */ -#define HSP_SIDR_SID_18 (0x40000UL << HSP_SIDR_SID_Pos) /*!< 0x00040000 */ -#define HSP_SIDR_SID_19 (0x80000UL << HSP_SIDR_SID_Pos) /*!< 0x00080000 */ -#define HSP_SIDR_SID_20 (0x100000UL << HSP_SIDR_SID_Pos) /*!< 0x00100000 */ -#define HSP_SIDR_SID_21 (0x200000UL << HSP_SIDR_SID_Pos) /*!< 0x00200000 */ -#define HSP_SIDR_SID_22 (0x400000UL << HSP_SIDR_SID_Pos) /*!< 0x00400000 */ -#define HSP_SIDR_SID_23 (0x800000UL << HSP_SIDR_SID_Pos) /*!< 0x00800000 */ -#define HSP_SIDR_SID_24 (0x1000000UL << HSP_SIDR_SID_Pos) /*!< 0x01000000 */ -#define HSP_SIDR_SID_25 (0x2000000UL << HSP_SIDR_SID_Pos) /*!< 0x02000000 */ -#define HSP_SIDR_SID_26 (0x4000000UL << HSP_SIDR_SID_Pos) /*!< 0x04000000 */ -#define HSP_SIDR_SID_27 (0x8000000UL << HSP_SIDR_SID_Pos) /*!< 0x08000000 */ -#define HSP_SIDR_SID_28 (0x10000000UL << HSP_SIDR_SID_Pos) /*!< 0x10000000 */ -#define HSP_SIDR_SID_29 (0x20000000UL << HSP_SIDR_SID_Pos) /*!< 0x20000000 */ -#define HSP_SIDR_SID_30 (0x40000000UL << HSP_SIDR_SID_Pos) /*!< 0x40000000 */ -#define HSP_SIDR_SID_31 (0x80000000UL << HSP_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -13774,303 +14041,303 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for I2C_CR1 register *******************/ -#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Pos (0UL) #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ -#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Pos (1UL) #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ -#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Pos (2UL) #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ -#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Pos (3UL) #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ -#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Pos (4UL) #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ -#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Pos (5UL) #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ -#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Pos (6UL) #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ -#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Pos (7UL) #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ -#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Pos (8UL) #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ -#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Pos (12UL) #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ -#define I2C_CR1_SWRST_Pos (13U) +#define I2C_CR1_SWRST_Pos (13UL) #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ -#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Pos (14UL) #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ -#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Pos (15UL) #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ -#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Pos (16UL) #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ -#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Pos (17UL) #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ -#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Pos (18UL) #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ -#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Pos (19UL) #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ -#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Pos (20UL) #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ -#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Pos (21UL) #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ -#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Pos (22UL) #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ -#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Pos (23UL) #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ -#define I2C_CR1_FMP_Pos (24U) +#define I2C_CR1_FMP_Pos (24UL) #define I2C_CR1_FMP_Msk (0x1UL << I2C_CR1_FMP_Pos) /*!< 0x01000000 */ #define I2C_CR1_FMP I2C_CR1_FMP_Msk /*!< FMP enable */ -#define I2C_CR1_ADDRACLR_Pos (30U) +#define I2C_CR1_ADDRACLR_Pos (30UL) #define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ #define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ -#define I2C_CR1_STOPFACLR_Pos (31U) +#define I2C_CR1_STOPFACLR_Pos (31UL) #define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ #define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ /****************** Bit definition for I2C_CR2 register ********************/ -#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Pos (0UL) #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ -#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Pos (10UL) #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ -#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Pos (11UL) #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ -#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Pos (12UL) #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ -#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Pos (13UL) #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ -#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Pos (14UL) #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ -#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Pos (15UL) #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ -#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Pos (16UL) #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ -#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Pos (24UL) #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ -#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Pos (25UL) #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ -#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Pos (26UL) #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ /******************* Bit definition for I2C_OAR1 register ******************/ -#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Pos (0UL) #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ -#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Pos (10UL) #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ -#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Pos (15UL) #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ /******************* Bit definition for I2C_OAR2 register ******************/ -#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Pos (1UL) #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ -#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Pos (8UL) #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ #define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */ -#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Pos (8UL) #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ -#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Pos (9UL) #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ -#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Pos (8UL) #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ -#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Pos (10UL) #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ -#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Pos (8UL) #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ -#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Pos (9UL) #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ -#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Pos (8UL) #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ -#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Pos (15UL) #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ /******************* Bit definition for I2C_TIMINGR register *******************/ -#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Pos (0UL) #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ -#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Pos (8UL) #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ -#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Pos (16UL) #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ -#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Pos (20UL) #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ -#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Pos (28UL) #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ /******************* Bit definition for I2C_TIMEOUTR register *******************/ -#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0UL) #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ -#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Pos (12UL) #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ -#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15UL) #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ -#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16UL) #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ -#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Pos (31UL) #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ /****************** Bit definition for I2C_ISR register *********************/ -#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Pos (0UL) #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ -#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Pos (1UL) #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ -#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Pos (2UL) #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ -#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Pos (3UL) #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ -#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Pos (4UL) #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ -#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Pos (5UL) #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ -#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Pos (6UL) #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ -#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Pos (7UL) #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ -#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Pos (8UL) #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ -#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Pos (9UL) #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ -#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Pos (10UL) #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ -#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Pos (11UL) #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ -#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Pos (12UL) #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ -#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Pos (13UL) #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ -#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Pos (15UL) #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ -#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Pos (16UL) #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ -#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Pos (17UL) #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ /****************** Bit definition for I2C_ICR register *********************/ -#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Pos (3UL) #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ -#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Pos (4UL) #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ -#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Pos (5UL) #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ -#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Pos (8UL) #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ -#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Pos (9UL) #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ -#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Pos (10UL) #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ -#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Pos (11UL) #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ -#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Pos (12UL) #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ -#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Pos (13UL) #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ /****************** Bit definition for I2C_PECR register *********************/ -#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Pos (0UL) #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ /****************** Bit definition for I2C_RXDR register *********************/ -#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Pos (0UL) #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ /****************** Bit definition for I2C_TXDR register *********************/ -#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Pos (0UL) #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ /****************** Bit definition for I2C_AUTOCR register ********************/ -#define I2C_AUTOCR_TCDMAEN_Pos (6U) +#define I2C_AUTOCR_TCDMAEN_Pos (6UL) #define I2C_AUTOCR_TCDMAEN_Msk (0x1UL << I2C_AUTOCR_TCDMAEN_Pos) /*!< 0x00000040 */ #define I2C_AUTOCR_TCDMAEN I2C_AUTOCR_TCDMAEN_Msk /*!< DMA request enable on Transfer Complete event */ -#define I2C_AUTOCR_TCRDMAEN_Pos (7U) +#define I2C_AUTOCR_TCRDMAEN_Pos (7UL) #define I2C_AUTOCR_TCRDMAEN_Msk (0x1UL << I2C_AUTOCR_TCRDMAEN_Pos) /*!< 0x00000080 */ #define I2C_AUTOCR_TCRDMAEN I2C_AUTOCR_TCRDMAEN_Msk /*!< DMA request enable on Transfer Complete Reload event */ -#define I2C_AUTOCR_TRIGSEL_Pos (16U) +#define I2C_AUTOCR_TRIGSEL_Pos (16UL) #define I2C_AUTOCR_TRIGSEL_Msk (0xFUL << I2C_AUTOCR_TRIGSEL_Pos) /*!< 0x000F0000 */ #define I2C_AUTOCR_TRIGSEL I2C_AUTOCR_TRIGSEL_Msk /*!< Trigger selection */ -#define I2C_AUTOCR_TRIGPOL_Pos (20U) +#define I2C_AUTOCR_TRIGPOL_Pos (20UL) #define I2C_AUTOCR_TRIGPOL_Msk (0x1UL << I2C_AUTOCR_TRIGPOL_Pos) /*!< 0x000100000 */ #define I2C_AUTOCR_TRIGPOL I2C_AUTOCR_TRIGPOL_Msk /*!< Trigger polarity */ -#define I2C_AUTOCR_TRIGEN_Pos (21U) +#define I2C_AUTOCR_TRIGEN_Pos (21UL) #define I2C_AUTOCR_TRIGEN_Msk (0x1UL << I2C_AUTOCR_TRIGEN_Pos) /*!< 0x000200000 */ #define I2C_AUTOCR_TRIGEN I2C_AUTOCR_TRIGEN_Msk /*!< Trigger enable */ @@ -14080,566 +14347,566 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for I3C_CR register *********************/ -#define I3C_CR_DCNT_Pos (0U) +#define I3C_CR_DCNT_Pos (0UL) #define I3C_CR_DCNT_Msk (0xFFFFUL << I3C_CR_DCNT_Pos) /*!< 0x0000FFFF */ #define I3C_CR_DCNT I3C_CR_DCNT_Msk /*!< Data Byte Count */ -#define I3C_CR_RNW_Pos (16U) +#define I3C_CR_RNW_Pos (16UL) #define I3C_CR_RNW_Msk (0x1UL << I3C_CR_RNW_Pos) /*!< 0x00010000 */ #define I3C_CR_RNW I3C_CR_RNW_Msk /*!< Read Not Write */ -#define I3C_CR_CCC_Pos (16U) +#define I3C_CR_CCC_Pos (16UL) #define I3C_CR_CCC_Msk (0xFFUL << I3C_CR_CCC_Pos) /*!< 0x00FF0000 */ #define I3C_CR_CCC I3C_CR_CCC_Msk /*!< 8-Bit CCC code */ -#define I3C_CR_ADD_Pos (17U) +#define I3C_CR_ADD_Pos (17UL) #define I3C_CR_ADD_Msk (0x7FUL << I3C_CR_ADD_Pos) /*!< 0x00FE0000 */ #define I3C_CR_ADD I3C_CR_ADD_Msk /*!< Target Address */ -#define I3C_CR_MTYPE_Pos (27U) +#define I3C_CR_MTYPE_Pos (27UL) #define I3C_CR_MTYPE_Msk (0xFUL << I3C_CR_MTYPE_Pos) /*!< 0xF8000000 */ #define I3C_CR_MTYPE I3C_CR_MTYPE_Msk /*!< Message Type */ #define I3C_CR_MTYPE_0 (0x1UL << I3C_CR_MTYPE_Pos) /*!< 0x08000000 */ #define I3C_CR_MTYPE_1 (0x2UL << I3C_CR_MTYPE_Pos) /*!< 0x10000000 */ #define I3C_CR_MTYPE_2 (0x4UL << I3C_CR_MTYPE_Pos) /*!< 0x20000000 */ #define I3C_CR_MTYPE_3 (0x8UL << I3C_CR_MTYPE_Pos) /*!< 0x40000000 */ -#define I3C_CR_MEND_Pos (31U) +#define I3C_CR_MEND_Pos (31UL) #define I3C_CR_MEND_Msk (0x1UL << I3C_CR_MEND_Pos) /*!< 0x80000000 */ #define I3C_CR_MEND I3C_CR_MEND_Msk /*!< Message End */ /******************* Bit definition for I3C_CFGR register *******************/ -#define I3C_CFGR_EN_Pos (0U) +#define I3C_CFGR_EN_Pos (0UL) #define I3C_CFGR_EN_Msk (0x1UL << I3C_CFGR_EN_Pos) /*!< 0x00000001 */ #define I3C_CFGR_EN I3C_CFGR_EN_Msk /*!< Peripheral Enable */ -#define I3C_CFGR_CRINIT_Pos (1U) +#define I3C_CFGR_CRINIT_Pos (1UL) #define I3C_CFGR_CRINIT_Msk (0x1UL << I3C_CFGR_CRINIT_Pos) /*!< 0x00000002 */ #define I3C_CFGR_CRINIT I3C_CFGR_CRINIT_Msk /*!< Peripheral Init mode (Target/Controller) */ -#define I3C_CFGR_NOARBH_Pos (2U) +#define I3C_CFGR_NOARBH_Pos (2UL) #define I3C_CFGR_NOARBH_Msk (0x1UL << I3C_CFGR_NOARBH_Pos) /*!< 0x00000004 */ #define I3C_CFGR_NOARBH I3C_CFGR_NOARBH_Msk /*!< No Arbitration Header (7'h7E)*/ -#define I3C_CFGR_RSTPTRN_Pos (3U) +#define I3C_CFGR_RSTPTRN_Pos (3UL) #define I3C_CFGR_RSTPTRN_Msk (0x1UL << I3C_CFGR_RSTPTRN_Pos) /*!< 0x00000008 */ #define I3C_CFGR_RSTPTRN I3C_CFGR_RSTPTRN_Msk /*!< Reset Pattern enable */ -#define I3C_CFGR_EXITPTRN_Pos (4U) +#define I3C_CFGR_EXITPTRN_Pos (4UL) #define I3C_CFGR_EXITPTRN_Msk (0x1UL << I3C_CFGR_EXITPTRN_Pos) /*!< 0x00000010 */ #define I3C_CFGR_EXITPTRN I3C_CFGR_EXITPTRN_Msk /*!< Exit Pattern enable */ -#define I3C_CFGR_HKSDAEN_Pos (5U) +#define I3C_CFGR_HKSDAEN_Pos (5UL) #define I3C_CFGR_HKSDAEN_Msk (0x1UL << I3C_CFGR_HKSDAEN_Pos) /*!< 0x00000020 */ #define I3C_CFGR_HKSDAEN I3C_CFGR_HKSDAEN_Msk /*!< High-Keeper on SDA Enable */ -#define I3C_CFGR_HJACK_Pos (7U) +#define I3C_CFGR_HJACK_Pos (7UL) #define I3C_CFGR_HJACK_Msk (0x1UL << I3C_CFGR_HJACK_Pos) /*!< 0x00000080 */ #define I3C_CFGR_HJACK I3C_CFGR_HJACK_Msk /*!< Hot Join Acknowledgment */ -#define I3C_CFGR_RXDMAEN_Pos (8U) +#define I3C_CFGR_RXDMAEN_Pos (8UL) #define I3C_CFGR_RXDMAEN_Msk (0x1UL << I3C_CFGR_RXDMAEN_Pos) /*!< 0x00000100 */ #define I3C_CFGR_RXDMAEN I3C_CFGR_RXDMAEN_Msk /*!< RX FIFO DMA mode Enable */ -#define I3C_CFGR_RXFLUSH_Pos (9U) +#define I3C_CFGR_RXFLUSH_Pos (9UL) #define I3C_CFGR_RXFLUSH_Msk (0x1UL << I3C_CFGR_RXFLUSH_Pos) /*!< 0x00000200 */ #define I3C_CFGR_RXFLUSH I3C_CFGR_RXFLUSH_Msk /*!< RX FIFO Flush */ -#define I3C_CFGR_RXTHRES_Pos (10U) +#define I3C_CFGR_RXTHRES_Pos (10UL) #define I3C_CFGR_RXTHRES_Msk (0x1UL << I3C_CFGR_RXTHRES_Pos) /*!< 0x00000400 */ #define I3C_CFGR_RXTHRES I3C_CFGR_RXTHRES_Msk /*!< RX FIFO Threshold */ -#define I3C_CFGR_TXDMAEN_Pos (12U) +#define I3C_CFGR_TXDMAEN_Pos (12UL) #define I3C_CFGR_TXDMAEN_Msk (0x1UL << I3C_CFGR_TXDMAEN_Pos) /*!< 0x00001000 */ #define I3C_CFGR_TXDMAEN I3C_CFGR_TXDMAEN_Msk /*!< TX FIFO DMA mode Enable */ -#define I3C_CFGR_TXFLUSH_Pos (13U) +#define I3C_CFGR_TXFLUSH_Pos (13UL) #define I3C_CFGR_TXFLUSH_Msk (0x1UL << I3C_CFGR_TXFLUSH_Pos) /*!< 0x00002000 */ #define I3C_CFGR_TXFLUSH I3C_CFGR_TXFLUSH_Msk /*!< TX FIFO Flush */ -#define I3C_CFGR_TXTHRES_Pos (14U) +#define I3C_CFGR_TXTHRES_Pos (14UL) #define I3C_CFGR_TXTHRES_Msk (0x1UL << I3C_CFGR_TXTHRES_Pos) /*!< 0x00004000 */ #define I3C_CFGR_TXTHRES I3C_CFGR_TXTHRES_Msk /*!< TX FIFO Threshold */ -#define I3C_CFGR_SDMAEN_Pos (16U) +#define I3C_CFGR_SDMAEN_Pos (16UL) #define I3C_CFGR_SDMAEN_Msk (0x1UL << I3C_CFGR_SDMAEN_Pos) /*!< 0x00010000 */ #define I3C_CFGR_SDMAEN I3C_CFGR_SDMAEN_Msk /*!< Status FIFO DMA mode Enable */ -#define I3C_CFGR_SFLUSH_Pos (17U) +#define I3C_CFGR_SFLUSH_Pos (17UL) #define I3C_CFGR_SFLUSH_Msk (0x1UL << I3C_CFGR_SFLUSH_Pos) /*!< 0x00020000 */ #define I3C_CFGR_SFLUSH I3C_CFGR_SFLUSH_Msk /*!< Status FIFO Flush */ -#define I3C_CFGR_SMODE_Pos (18U) +#define I3C_CFGR_SMODE_Pos (18UL) #define I3C_CFGR_SMODE_Msk (0x1UL << I3C_CFGR_SMODE_Pos) /*!< 0x00040000 */ #define I3C_CFGR_SMODE I3C_CFGR_SMODE_Msk /*!< Status FIFO mode Enable */ -#define I3C_CFGR_TMODE_Pos (19U) +#define I3C_CFGR_TMODE_Pos (19UL) #define I3C_CFGR_TMODE_Msk (0x1UL << I3C_CFGR_TMODE_Pos) /*!< 0x00080000 */ #define I3C_CFGR_TMODE I3C_CFGR_TMODE_Msk /*!< Control FIFO mode Enable */ -#define I3C_CFGR_CDMAEN_Pos (20U) +#define I3C_CFGR_CDMAEN_Pos (20UL) #define I3C_CFGR_CDMAEN_Msk (0x1UL << I3C_CFGR_CDMAEN_Pos) /*!< 0x00100000 */ #define I3C_CFGR_CDMAEN I3C_CFGR_CDMAEN_Msk /*!< Control FIFO DMA mode Enable */ -#define I3C_CFGR_CFLUSH_Pos (21U) +#define I3C_CFGR_CFLUSH_Pos (21UL) #define I3C_CFGR_CFLUSH_Msk (0x1UL << I3C_CFGR_CFLUSH_Pos) /*!< 0x00200000 */ #define I3C_CFGR_CFLUSH I3C_CFGR_CFLUSH_Msk /*!< Control FIFO Flush */ -#define I3C_CFGR_FCFDIS_Pos (23U) +#define I3C_CFGR_FCFDIS_Pos (23UL) #define I3C_CFGR_FCFDIS_Msk (0x1UL << I3C_CFGR_FCFDIS_Pos) /*!< 0x00800000 */ #define I3C_CFGR_FCFDIS I3C_CFGR_FCFDIS_Msk /*!< FCF generation disable */ -#define I3C_CFGR_TRIGSEL_Pos (24U) +#define I3C_CFGR_TRIGSEL_Pos (24UL) #define I3C_CFGR_TRIGSEL_Msk (0xFUL << I3C_CFGR_TRIGSEL_Pos) /*!< 0x0F000000 */ #define I3C_CFGR_TRIGSEL I3C_CFGR_TRIGSEL_Msk /*!< Trigger selection */ -#define I3C_CFGR_TRIGPOL_Pos (28U) +#define I3C_CFGR_TRIGPOL_Pos (28UL) #define I3C_CFGR_TRIGPOL_Msk (0x1UL << I3C_CFGR_TRIGPOL_Pos) /*!< 0x10000000 */ #define I3C_CFGR_TRIGPOL I3C_CFGR_TRIGPOL_Msk /*!< Trigger polarity */ -#define I3C_CFGR_TRIGHWEN_Pos (29U) +#define I3C_CFGR_TRIGHWEN_Pos (29UL) #define I3C_CFGR_TRIGHWEN_Msk (0x1UL << I3C_CFGR_TRIGHWEN_Pos) /*!< 0x20000000 */ #define I3C_CFGR_TRIGHWEN I3C_CFGR_TRIGHWEN_Msk /*!< Trigger enable */ -#define I3C_CFGR_TSFSET_Pos (30U) +#define I3C_CFGR_TSFSET_Pos (30UL) #define I3C_CFGR_TSFSET_Msk (0x1UL << I3C_CFGR_TSFSET_Pos) /*!< 0x40000000 */ #define I3C_CFGR_TSFSET I3C_CFGR_TSFSET_Msk /*!< Transfer Set */ /******************* Bit definition for I3C_RDR register ********************/ -#define I3C_RDR_RDB0_Pos (0U) +#define I3C_RDR_RDB0_Pos (0UL) #define I3C_RDR_RDB0_Msk (0xFFUL << I3C_RDR_RDB0_Pos) /*!< 0x000000FF */ #define I3C_RDR_RDB0 I3C_RDR_RDB0_Msk /*!< Receive Data Byte */ /****************** Bit definition for I3C_RDWR register ********************/ -#define I3C_RDWR_RDBx_Pos (0U) +#define I3C_RDWR_RDBx_Pos (0UL) #define I3C_RDWR_RDBx_Msk (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos) /*!< 0xFFFFFFFF */ #define I3C_RDWR_RDBx I3C_RDWR_RDBx_Msk /*!< Receive Data Byte, full double word */ -#define I3C_RDWR_RDB0_Pos (0U) +#define I3C_RDWR_RDB0_Pos (0UL) #define I3C_RDWR_RDB0_Msk (0xFFUL << I3C_RDWR_RDB0_Pos) /*!< 0x000000FF */ #define I3C_RDWR_RDB0 I3C_RDWR_RDB0_Msk /*!< Receive Data Byte 0 */ -#define I3C_RDWR_RDB1_Pos (8U) +#define I3C_RDWR_RDB1_Pos (8UL) #define I3C_RDWR_RDB1_Msk (0xFFUL << I3C_RDWR_RDB1_Pos) /*!< 0x0000FF00 */ #define I3C_RDWR_RDB1 I3C_RDWR_RDB1_Msk /*!< Receive Data Byte 1 */ -#define I3C_RDWR_RDB2_Pos (16U) +#define I3C_RDWR_RDB2_Pos (16UL) #define I3C_RDWR_RDB2_Msk (0xFFUL << I3C_RDWR_RDB2_Pos) /*!< 0x00FF0000 */ #define I3C_RDWR_RDB2 I3C_RDWR_RDB2_Msk /*!< Receive Data Byte 2 */ -#define I3C_RDWR_RDB3_Pos (24U) +#define I3C_RDWR_RDB3_Pos (24UL) #define I3C_RDWR_RDB3_Msk (0xFFUL << I3C_RDWR_RDB3_Pos) /*!< 0xFF000000 */ #define I3C_RDWR_RDB3 I3C_RDWR_RDB3_Msk /*!< Receive Data Byte 3 */ /******************* Bit definition for I3C_TDR register ********************/ -#define I3C_TDR_TDB0_Pos (0U) +#define I3C_TDR_TDB0_Pos (0UL) #define I3C_TDR_TDB0_Msk (0xFFUL << I3C_TDR_TDB0_Pos) /*!< 0x000000FF */ #define I3C_TDR_TDB0 I3C_TDR_TDB0_Msk /*!< Transmit Data Byte */ /****************** Bit definition for I3C_TDWR register ********************/ -#define I3C_TDWR_TDBx_Pos (0U) +#define I3C_TDWR_TDBx_Pos (0UL) #define I3C_TDWR_TDBx_Msk (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos) /*!< 0xFFFFFFFF */ #define I3C_TDWR_TDBx I3C_TDWR_TDBx_Msk /*!< Transmit Data Byte, full double word */ -#define I3C_TDWR_TDB0_Pos (0U) +#define I3C_TDWR_TDB0_Pos (0UL) #define I3C_TDWR_TDB0_Msk (0xFFUL << I3C_TDWR_TDB0_Pos) /*!< 0x000000FF */ #define I3C_TDWR_TDB0 I3C_TDWR_TDB0_Msk /*!< Transmit Data Byte 0 */ -#define I3C_TDWR_TDB1_Pos (8U) +#define I3C_TDWR_TDB1_Pos (8UL) #define I3C_TDWR_TDB1_Msk (0xFFUL << I3C_TDWR_TDB1_Pos) /*!< 0x0000FF00 */ #define I3C_TDWR_TDB1 I3C_TDWR_TDB1_Msk /*!< Transmit Data Byte 1 */ -#define I3C_TDWR_TDB2_Pos (16U) +#define I3C_TDWR_TDB2_Pos (16UL) #define I3C_TDWR_TDB2_Msk (0xFFUL << I3C_TDWR_TDB2_Pos) /*!< 0x00FF0000 */ #define I3C_TDWR_TDB2 I3C_TDWR_TDB2_Msk /*!< Transmit Data Byte 2 */ -#define I3C_TDWR_TDB3_Pos (24U) +#define I3C_TDWR_TDB3_Pos (24UL) #define I3C_TDWR_TDB3_Msk (0xFFUL << I3C_TDWR_TDB3_Pos) /*!< 0xFF000000 */ #define I3C_TDWR_TDB3 I3C_TDWR_TDB3_Msk /*!< Transmit Data Byte 3 */ /******************* Bit definition for I3C_IBIDR register ******************/ -#define I3C_IBIDR_IBIDBx_Pos (0U) +#define I3C_IBIDR_IBIDBx_Pos (0UL) #define I3C_IBIDR_IBIDBx_Msk (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos) /*!< 0xFFFFFFFF */ #define I3C_IBIDR_IBIDBx I3C_IBIDR_IBIDBx_Msk /*!< IBI Data Byte, full double word */ -#define I3C_IBIDR_IBIDB0_Pos (0U) +#define I3C_IBIDR_IBIDB0_Pos (0UL) #define I3C_IBIDR_IBIDB0_Msk (0xFFUL << I3C_IBIDR_IBIDB0_Pos) /*!< 0x000000FF */ #define I3C_IBIDR_IBIDB0 I3C_IBIDR_IBIDB0_Msk /*!< IBI Data Byte 0 */ -#define I3C_IBIDR_IBIDB1_Pos (8U) +#define I3C_IBIDR_IBIDB1_Pos (8UL) #define I3C_IBIDR_IBIDB1_Msk (0xFFUL << I3C_IBIDR_IBIDB1_Pos) /*!< 0x0000FF00 */ #define I3C_IBIDR_IBIDB1 I3C_IBIDR_IBIDB1_Msk /*!< IBI Data Byte 1 */ -#define I3C_IBIDR_IBIDB2_Pos (16U) +#define I3C_IBIDR_IBIDB2_Pos (16UL) #define I3C_IBIDR_IBIDB2_Msk (0xFFUL << I3C_IBIDR_IBIDB2_Pos) /*!< 0x00FF0000 */ #define I3C_IBIDR_IBIDB2 I3C_IBIDR_IBIDB2_Msk /*!< IBI Data Byte 2 */ -#define I3C_IBIDR_IBIDB3_Pos (24U) +#define I3C_IBIDR_IBIDB3_Pos (24UL) #define I3C_IBIDR_IBIDB3_Msk (0xFFUL << I3C_IBIDR_IBIDB3_Pos) /*!< 0xFF000000 */ #define I3C_IBIDR_IBIDB3 I3C_IBIDR_IBIDB3_Msk /*!< IBI Data Byte 3 */ /****************** Bit definition for I3C_TGTTDR register ******************/ -#define I3C_TGTTDR_TGTTDCNT_Pos (0U) +#define I3C_TGTTDR_TGTTDCNT_Pos (0UL) #define I3C_TGTTDR_TGTTDCNT_Msk (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos) /*!< 0x0000FFFF */ #define I3C_TGTTDR_TGTTDCNT I3C_TGTTDR_TGTTDCNT_Msk /*!< Target Transmit Data Counter */ -#define I3C_TGTTDR_PRELOAD_Pos (16U) +#define I3C_TGTTDR_PRELOAD_Pos (16UL) #define I3C_TGTTDR_PRELOAD_Msk (0x1UL << I3C_TGTTDR_PRELOAD_Pos) /*!< 0x00010000 */ #define I3C_TGTTDR_PRELOAD I3C_TGTTDR_PRELOAD_Msk /*!< Transmit FIFO Preload Enable/Status */ /******************* Bit definition for I3C_SR register *********************/ -#define I3C_SR_XDCNT_Pos (0U) +#define I3C_SR_XDCNT_Pos (0UL) #define I3C_SR_XDCNT_Msk (0xFFFFUL << I3C_SR_XDCNT_Pos) /*!< 0x0000FFFF */ #define I3C_SR_XDCNT I3C_SR_XDCNT_Msk /*!< Transfer Data Byte Count status */ -#define I3C_SR_ABT_Pos (17U) +#define I3C_SR_ABT_Pos (17UL) #define I3C_SR_ABT_Msk (0x1UL << I3C_SR_ABT_Pos) /*!< 0x00020000 */ #define I3C_SR_ABT I3C_SR_ABT_Msk /*!< Target Abort Indication */ -#define I3C_SR_DIR_Pos (18U) +#define I3C_SR_DIR_Pos (18UL) #define I3C_SR_DIR_Msk (0x1UL << I3C_SR_DIR_Pos) /*!< 0x00040000 */ #define I3C_SR_DIR I3C_SR_DIR_Msk /*!< Message Direction */ -#define I3C_SR_MID_Pos (24U) +#define I3C_SR_MID_Pos (24UL) #define I3C_SR_MID_Msk (0xFFUL << I3C_SR_MID_Pos) /*!< 0xFF000000 */ #define I3C_SR_MID I3C_SR_MID_Msk /*!< Message Identifier */ /******************* Bit definition for I3C_SER register ********************/ -#define I3C_SER_CODERR_Pos (0U) +#define I3C_SER_CODERR_Pos (0UL) #define I3C_SER_CODERR_Msk (0xFUL << I3C_SER_CODERR_Pos) /*!< 0x0000000F */ #define I3C_SER_CODERR I3C_SER_CODERR_Msk /*!< Protocol Error Code */ #define I3C_SER_CODERR_0 (0x1UL << I3C_SER_CODERR_Pos) /*!< 0x00000001 */ #define I3C_SER_CODERR_1 (0x2UL << I3C_SER_CODERR_Pos) /*!< 0x00000002 */ #define I3C_SER_CODERR_2 (0x4UL << I3C_SER_CODERR_Pos) /*!< 0x00000004 */ #define I3C_SER_CODERR_3 (0x8UL << I3C_SER_CODERR_Pos) /*!< 0x00000008 */ -#define I3C_SER_PERR_Pos (4U) +#define I3C_SER_PERR_Pos (4UL) #define I3C_SER_PERR_Msk (0x1UL << I3C_SER_PERR_Pos) /*!< 0x00000010 */ #define I3C_SER_PERR I3C_SER_PERR_Msk /*!< Protocol Error */ -#define I3C_SER_STALL_Pos (5U) +#define I3C_SER_STALL_Pos (5UL) #define I3C_SER_STALL_Msk (0x1UL << I3C_SER_STALL_Pos) /*!< 0x00000020 */ #define I3C_SER_STALL I3C_SER_STALL_Msk /*!< SCL Stall Error */ -#define I3C_SER_DOVR_Pos (6U) +#define I3C_SER_DOVR_Pos (6UL) #define I3C_SER_DOVR_Msk (0x1UL << I3C_SER_DOVR_Pos) /*!< 0x00000040 */ #define I3C_SER_DOVR I3C_SER_DOVR_Msk /*!< RX/TX FIFO Overrun */ -#define I3C_SER_COVR_Pos (7U) +#define I3C_SER_COVR_Pos (7UL) #define I3C_SER_COVR_Msk (0x1UL << I3C_SER_COVR_Pos) /*!< 0x00000080 */ #define I3C_SER_COVR I3C_SER_COVR_Msk /*!< Status/Control FIFO Overrun */ -#define I3C_SER_ANACK_Pos (8U) +#define I3C_SER_ANACK_Pos (8UL) #define I3C_SER_ANACK_Msk (0x1UL << I3C_SER_ANACK_Pos) /*!< 0x00000100 */ #define I3C_SER_ANACK I3C_SER_ANACK_Msk /*!< Address Not Acknowledged */ -#define I3C_SER_DNACK_Pos (9U) +#define I3C_SER_DNACK_Pos (9UL) #define I3C_SER_DNACK_Msk (0x1UL << I3C_SER_DNACK_Pos) /*!< 0x00000200 */ #define I3C_SER_DNACK I3C_SER_DNACK_Msk /*!< Data Not Acknowledged */ -#define I3C_SER_DERR_Pos (10U) +#define I3C_SER_DERR_Pos (10UL) #define I3C_SER_DERR_Msk (0x1UL << I3C_SER_DERR_Pos) /*!< 0x00000400 */ #define I3C_SER_DERR I3C_SER_DERR_Msk /*!< Data Error during the controller-role hand-off procedure */ /******************* Bit definition for I3C_RMR register ********************/ -#define I3C_RMR_IBIRDCNT_Pos (0U) +#define I3C_RMR_IBIRDCNT_Pos (0UL) #define I3C_RMR_IBIRDCNT_Msk (0x7UL << I3C_RMR_IBIRDCNT_Pos) /*!< 0x00000007 */ #define I3C_RMR_IBIRDCNT I3C_RMR_IBIRDCNT_Msk /*!< Data Count when reading IBI data */ -#define I3C_RMR_RCODE_Pos (8U) +#define I3C_RMR_RCODE_Pos (8UL) #define I3C_RMR_RCODE_Msk (0xFFUL << I3C_RMR_RCODE_Pos) /*!< 0x0000FF00 */ #define I3C_RMR_RCODE I3C_RMR_RCODE_Msk /*!< CCC code of received command */ -#define I3C_RMR_RADD_Pos (17U) +#define I3C_RMR_RADD_Pos (17UL) #define I3C_RMR_RADD_Msk (0x7FUL << I3C_RMR_RADD_Pos) /*!< 0x00FE0000 */ #define I3C_RMR_RADD I3C_RMR_RADD_Msk /*!< Target Address Received during accepted IBI or Controller-role request */ /******************* Bit definition for I3C_EVR register ********************/ -#define I3C_EVR_CFEF_Pos (0U) +#define I3C_EVR_CFEF_Pos (0UL) #define I3C_EVR_CFEF_Msk (0x1UL << I3C_EVR_CFEF_Pos) /*!< 0x00000001 */ #define I3C_EVR_CFEF I3C_EVR_CFEF_Msk /*!< Control FIFO Empty Flag */ -#define I3C_EVR_TXFEF_Pos (1U) +#define I3C_EVR_TXFEF_Pos (1UL) #define I3C_EVR_TXFEF_Msk (0x1UL << I3C_EVR_TXFEF_Pos) /*!< 0x00000002 */ #define I3C_EVR_TXFEF I3C_EVR_TXFEF_Msk /*!< TX FIFO Empty Flag */ -#define I3C_EVR_CFNFF_Pos (2U) +#define I3C_EVR_CFNFF_Pos (2UL) #define I3C_EVR_CFNFF_Msk (0x1UL << I3C_EVR_CFNFF_Pos) /*!< 0x00000004 */ #define I3C_EVR_CFNFF I3C_EVR_CFNFF_Msk /*!< Control FIFO Not Full Flag */ -#define I3C_EVR_SFNEF_Pos (3U) +#define I3C_EVR_SFNEF_Pos (3UL) #define I3C_EVR_SFNEF_Msk (0x1UL << I3C_EVR_SFNEF_Pos) /*!< 0x00000008 */ #define I3C_EVR_SFNEF I3C_EVR_SFNEF_Msk /*!< Status FIFO Not Empty Flag */ -#define I3C_EVR_TXFNFF_Pos (4U) +#define I3C_EVR_TXFNFF_Pos (4UL) #define I3C_EVR_TXFNFF_Msk (0x1UL << I3C_EVR_TXFNFF_Pos) /*!< 0x00000010 */ #define I3C_EVR_TXFNFF I3C_EVR_TXFNFF_Msk /*!< TX FIFO Not Full Flag */ -#define I3C_EVR_RXFNEF_Pos (5U) +#define I3C_EVR_RXFNEF_Pos (5UL) #define I3C_EVR_RXFNEF_Msk (0x1UL << I3C_EVR_RXFNEF_Pos) /*!< 0x00000020 */ #define I3C_EVR_RXFNEF I3C_EVR_RXFNEF_Msk /*!< RX FIFO Not Empty Flag */ -#define I3C_EVR_TXLASTF_Pos (6U) +#define I3C_EVR_TXLASTF_Pos (6UL) #define I3C_EVR_TXLASTF_Msk (0x1UL << I3C_EVR_TXLASTF_Pos) /*!< 0x00000040 */ #define I3C_EVR_TXLASTF I3C_EVR_TXLASTF_Msk /*!< Last TX byte available in FIFO */ -#define I3C_EVR_RXLASTF_Pos (7U) +#define I3C_EVR_RXLASTF_Pos (7UL) #define I3C_EVR_RXLASTF_Msk (0x1UL << I3C_EVR_RXLASTF_Pos) /*!< 0x00000080 */ #define I3C_EVR_RXLASTF I3C_EVR_RXLASTF_Msk /*!< Last RX byte read from FIFO */ -#define I3C_EVR_FCF_Pos (9U) +#define I3C_EVR_FCF_Pos (9UL) #define I3C_EVR_FCF_Msk (0x1UL << I3C_EVR_FCF_Pos) /*!< 0x00000200 */ #define I3C_EVR_FCF I3C_EVR_FCF_Msk /*!< Frame Complete Flag */ -#define I3C_EVR_RXTGTENDF_Pos (10U) +#define I3C_EVR_RXTGTENDF_Pos (10UL) #define I3C_EVR_RXTGTENDF_Msk (0x1UL << I3C_EVR_RXTGTENDF_Pos) /*!< 0x00000400 */ #define I3C_EVR_RXTGTENDF I3C_EVR_RXTGTENDF_Msk /*!< Reception Target End Flag */ -#define I3C_EVR_ERRF_Pos (11U) +#define I3C_EVR_ERRF_Pos (11UL) #define I3C_EVR_ERRF_Msk (0x1UL << I3C_EVR_ERRF_Pos) /*!< 0x00000800 */ #define I3C_EVR_ERRF I3C_EVR_ERRF_Msk /*!< Error Flag */ -#define I3C_EVR_IBIF_Pos (15U) +#define I3C_EVR_IBIF_Pos (15UL) #define I3C_EVR_IBIF_Msk (0x1UL << I3C_EVR_IBIF_Pos) /*!< 0x00008000 */ #define I3C_EVR_IBIF I3C_EVR_IBIF_Msk /*!< IBI Flag */ -#define I3C_EVR_IBIENDF_Pos (16U) +#define I3C_EVR_IBIENDF_Pos (16UL) #define I3C_EVR_IBIENDF_Msk (0x1UL << I3C_EVR_IBIENDF_Pos) /*!< 0x00010000 */ #define I3C_EVR_IBIENDF I3C_EVR_IBIENDF_Msk /*!< IBI End Flag */ -#define I3C_EVR_CRF_Pos (17U) +#define I3C_EVR_CRF_Pos (17UL) #define I3C_EVR_CRF_Msk (0x1UL << I3C_EVR_CRF_Pos) /*!< 0x00020000 */ #define I3C_EVR_CRF I3C_EVR_CRF_Msk /*!< Controller-role Request Flag */ -#define I3C_EVR_CRUPDF_Pos (18U) +#define I3C_EVR_CRUPDF_Pos (18UL) #define I3C_EVR_CRUPDF_Msk (0x1UL << I3C_EVR_CRUPDF_Pos) /*!< 0x00040000 */ #define I3C_EVR_CRUPDF I3C_EVR_CRUPDF_Msk /*!< Controller-role Update Flag */ -#define I3C_EVR_HJF_Pos (19U) +#define I3C_EVR_HJF_Pos (19UL) #define I3C_EVR_HJF_Msk (0x1UL << I3C_EVR_HJF_Pos) /*!< 0x00080000 */ #define I3C_EVR_HJF I3C_EVR_HJF_Msk /*!< Hot Join Flag */ -#define I3C_EVR_WKPF_Pos (21U) +#define I3C_EVR_WKPF_Pos (21UL) #define I3C_EVR_WKPF_Msk (0x1UL << I3C_EVR_WKPF_Pos) /*!< 0x00200000 */ #define I3C_EVR_WKPF I3C_EVR_WKPF_Msk /*!< Wake Up Flag */ -#define I3C_EVR_GETF_Pos (22U) +#define I3C_EVR_GETF_Pos (22UL) #define I3C_EVR_GETF_Msk (0x1UL << I3C_EVR_GETF_Pos) /*!< 0x00400000 */ #define I3C_EVR_GETF I3C_EVR_GETF_Msk /*!< Get type CCC received Flag */ -#define I3C_EVR_STAF_Pos (23U) +#define I3C_EVR_STAF_Pos (23UL) #define I3C_EVR_STAF_Msk (0x1UL << I3C_EVR_STAF_Pos) /*!< 0x00800000 */ #define I3C_EVR_STAF I3C_EVR_STAF_Msk /*!< Get Status Flag */ -#define I3C_EVR_DAUPDF_Pos (24U) +#define I3C_EVR_DAUPDF_Pos (24UL) #define I3C_EVR_DAUPDF_Msk (0x1UL << I3C_EVR_DAUPDF_Pos) /*!< 0x01000000 */ #define I3C_EVR_DAUPDF I3C_EVR_DAUPDF_Msk /*!< Dynamic Address Update Flag */ -#define I3C_EVR_MWLUPDF_Pos (25U) +#define I3C_EVR_MWLUPDF_Pos (25UL) #define I3C_EVR_MWLUPDF_Msk (0x1UL << I3C_EVR_MWLUPDF_Pos) /*!< 0x02000000 */ #define I3C_EVR_MWLUPDF I3C_EVR_MWLUPDF_Msk /*!< Max Write Length Update Flag */ -#define I3C_EVR_MRLUPDF_Pos (26U) +#define I3C_EVR_MRLUPDF_Pos (26UL) #define I3C_EVR_MRLUPDF_Msk (0x1UL << I3C_EVR_MRLUPDF_Pos) /*!< 0x04000000 */ #define I3C_EVR_MRLUPDF I3C_EVR_MRLUPDF_Msk /*!< Max Read Length Update Flag */ -#define I3C_EVR_RSTF_Pos (27U) +#define I3C_EVR_RSTF_Pos (27UL) #define I3C_EVR_RSTF_Msk (0x1UL << I3C_EVR_RSTF_Pos) /*!< 0x08000000 */ #define I3C_EVR_RSTF I3C_EVR_RSTF_Msk /*!< Reset Flag, due to Reset pattern received */ -#define I3C_EVR_ASUPDF_Pos (28U) +#define I3C_EVR_ASUPDF_Pos (28UL) #define I3C_EVR_ASUPDF_Msk (0x1UL << I3C_EVR_ASUPDF_Pos) /*!< 0x10000000 */ #define I3C_EVR_ASUPDF I3C_EVR_ASUPDF_Msk /*!< Activity State Flag */ -#define I3C_EVR_INTUPDF_Pos (29U) +#define I3C_EVR_INTUPDF_Pos (29UL) #define I3C_EVR_INTUPDF_Msk (0x1UL << I3C_EVR_INTUPDF_Pos) /*!< 0x20000000 */ #define I3C_EVR_INTUPDF I3C_EVR_INTUPDF_Msk /*!< Interrupt Update Flag */ -#define I3C_EVR_DEFF_Pos (30U) +#define I3C_EVR_DEFF_Pos (30UL) #define I3C_EVR_DEFF_Msk (0x1UL << I3C_EVR_DEFF_Pos) /*!< 0x40000000 */ #define I3C_EVR_DEFF I3C_EVR_DEFF_Msk /*!< List of Targets Command Received Flag */ -#define I3C_EVR_GRPF_Pos (31U) +#define I3C_EVR_GRPF_Pos (31UL) #define I3C_EVR_GRPF_Msk (0x1UL << I3C_EVR_GRPF_Pos) /*!< 0x80000000 */ #define I3C_EVR_GRPF I3C_EVR_GRPF_Msk /*!< List of Group Addresses Command Received Flag */ /******************* Bit definition for I3C_IER register ********************/ -#define I3C_IER_CFNFIE_Pos (2U) +#define I3C_IER_CFNFIE_Pos (2UL) #define I3C_IER_CFNFIE_Msk (0x1UL << I3C_IER_CFNFIE_Pos) /*!< 0x00000004 */ #define I3C_IER_CFNFIE I3C_IER_CFNFIE_Msk /*!< Control FIFO Not Full Interrupt Enable */ -#define I3C_IER_SFNEIE_Pos (3U) +#define I3C_IER_SFNEIE_Pos (3UL) #define I3C_IER_SFNEIE_Msk (0x1UL << I3C_IER_SFNEIE_Pos) /*!< 0x00000008 */ #define I3C_IER_SFNEIE I3C_IER_SFNEIE_Msk /*!< Status FIFO Not Empty Interrupt Enable */ -#define I3C_IER_TXFNFIE_Pos (4U) +#define I3C_IER_TXFNFIE_Pos (4UL) #define I3C_IER_TXFNFIE_Msk (0x1UL << I3C_IER_TXFNFIE_Pos) /*!< 0x00000010 */ #define I3C_IER_TXFNFIE I3C_IER_TXFNFIE_Msk /*!< TX FIFO Not Full Interrupt Enable */ -#define I3C_IER_RXFNEIE_Pos (5U) +#define I3C_IER_RXFNEIE_Pos (5UL) #define I3C_IER_RXFNEIE_Msk (0x1UL << I3C_IER_RXFNEIE_Pos) /*!< 0x00000020 */ #define I3C_IER_RXFNEIE I3C_IER_RXFNEIE_Msk /*!< RX FIFO Not Empty Interrupt Enable */ -#define I3C_IER_FCIE_Pos (9U) +#define I3C_IER_FCIE_Pos (9UL) #define I3C_IER_FCIE_Msk (0x1UL << I3C_IER_FCIE_Pos) /*!< 0x00000200 */ #define I3C_IER_FCIE I3C_IER_FCIE_Msk /*!< Frame Complete Interrupt Enable */ -#define I3C_IER_RXTGTENDIE_Pos (10U) +#define I3C_IER_RXTGTENDIE_Pos (10UL) #define I3C_IER_RXTGTENDIE_Msk (0x1UL << I3C_IER_RXTGTENDIE_Pos) /*!< 0x00000400 */ #define I3C_IER_RXTGTENDIE I3C_IER_RXTGTENDIE_Msk /*!< Reception Target End Interrupt Enable */ -#define I3C_IER_ERRIE_Pos (11U) +#define I3C_IER_ERRIE_Pos (11UL) #define I3C_IER_ERRIE_Msk (0x1UL << I3C_IER_ERRIE_Pos) /*!< 0x00000800 */ #define I3C_IER_ERRIE I3C_IER_ERRIE_Msk /*!< Error Interrupt Enable */ -#define I3C_IER_IBIIE_Pos (15U) +#define I3C_IER_IBIIE_Pos (15UL) #define I3C_IER_IBIIE_Msk (0x1UL << I3C_IER_IBIIE_Pos) /*!< 0x00008000 */ #define I3C_IER_IBIIE I3C_IER_IBIIE_Msk /*!< IBI Interrupt Enable */ -#define I3C_IER_IBIENDIE_Pos (16U) +#define I3C_IER_IBIENDIE_Pos (16UL) #define I3C_IER_IBIENDIE_Msk (0x1UL << I3C_IER_IBIENDIE_Pos) /*!< 0x00010000 */ #define I3C_IER_IBIENDIE I3C_IER_IBIENDIE_Msk /*!< IBI End Interrupt Enable */ -#define I3C_IER_CRIE_Pos (17U) +#define I3C_IER_CRIE_Pos (17UL) #define I3C_IER_CRIE_Msk (0x1UL << I3C_IER_CRIE_Pos) /*!< 0x00020000 */ #define I3C_IER_CRIE I3C_IER_CRIE_Msk /*!< Controller-role Interrupt Enable */ -#define I3C_IER_CRUPDIE_Pos (18U) +#define I3C_IER_CRUPDIE_Pos (18UL) #define I3C_IER_CRUPDIE_Msk (0x1UL << I3C_IER_CRUPDIE_Pos) /*!< 0x00040000 */ #define I3C_IER_CRUPDIE I3C_IER_CRUPDIE_Msk /*!< Controller-role Update Interrupt Enable */ -#define I3C_IER_HJIE_Pos (19U) +#define I3C_IER_HJIE_Pos (19UL) #define I3C_IER_HJIE_Msk (0x1UL << I3C_IER_HJIE_Pos) /*!< 0x00080000 */ #define I3C_IER_HJIE I3C_IER_HJIE_Msk /*!< Hot Join Interrupt Enable */ -#define I3C_IER_WKPIE_Pos (21U) +#define I3C_IER_WKPIE_Pos (21UL) #define I3C_IER_WKPIE_Msk (0x1UL << I3C_IER_WKPIE_Pos) /*!< 0x00200000 */ #define I3C_IER_WKPIE I3C_IER_WKPIE_Msk /*!< Wake Up Interrupt Enable */ -#define I3C_IER_GETIE_Pos (22U) +#define I3C_IER_GETIE_Pos (22UL) #define I3C_IER_GETIE_Msk (0x1UL << I3C_IER_GETIE_Pos) /*!< 0x00400000 */ #define I3C_IER_GETIE I3C_IER_GETIE_Msk /*!< Get type CCC received Interrupt Enable */ -#define I3C_IER_STAIE_Pos (23U) +#define I3C_IER_STAIE_Pos (23UL) #define I3C_IER_STAIE_Msk (0x1UL << I3C_IER_STAIE_Pos) /*!< 0x00800000 */ #define I3C_IER_STAIE I3C_IER_STAIE_Msk /*!< Get Status Interrupt Enable */ -#define I3C_IER_DAUPDIE_Pos (24U) +#define I3C_IER_DAUPDIE_Pos (24UL) #define I3C_IER_DAUPDIE_Msk (0x1UL << I3C_IER_DAUPDIE_Pos) /*!< 0x01000000 */ #define I3C_IER_DAUPDIE I3C_IER_DAUPDIE_Msk /*!< Dynamic Address Update Interrupt Enable */ -#define I3C_IER_MWLUPDIE_Pos (25U) +#define I3C_IER_MWLUPDIE_Pos (25UL) #define I3C_IER_MWLUPDIE_Msk (0x1UL << I3C_IER_MWLUPDIE_Pos) /*!< 0x02000000 */ #define I3C_IER_MWLUPDIE I3C_IER_MWLUPDIE_Msk /*!< Max Write Length Update Interrupt Enable */ -#define I3C_IER_MRLUPDIE_Pos (26U) +#define I3C_IER_MRLUPDIE_Pos (26UL) #define I3C_IER_MRLUPDIE_Msk (0x1UL << I3C_IER_MRLUPDIE_Pos) /*!< 0x04000000 */ #define I3C_IER_MRLUPDIE I3C_IER_MRLUPDIE_Msk /*!< Max Read Length Update Interrupt Enable */ -#define I3C_IER_RSTIE_Pos (27U) +#define I3C_IER_RSTIE_Pos (27UL) #define I3C_IER_RSTIE_Msk (0x1UL << I3C_IER_RSTIE_Pos) /*!< 0x08000000 */ #define I3C_IER_RSTIE I3C_IER_RSTIE_Msk /*!< Reset Interrupt Enabled, due to Reset pattern received */ -#define I3C_IER_ASUPDIE_Pos (28U) +#define I3C_IER_ASUPDIE_Pos (28UL) #define I3C_IER_ASUPDIE_Msk (0x1UL << I3C_IER_ASUPDIE_Pos) /*!< 0x10000000 */ #define I3C_IER_ASUPDIE I3C_IER_ASUPDIE_Msk /*!< Activity State Interrupt Enable */ -#define I3C_IER_INTUPDIE_Pos (29U) +#define I3C_IER_INTUPDIE_Pos (29UL) #define I3C_IER_INTUPDIE_Msk (0x1UL << I3C_IER_INTUPDIE_Pos) /*!< 0x20000000 */ #define I3C_IER_INTUPDIE I3C_IER_INTUPDIE_Msk /*!< Interrupt Update Interrupt Enable */ -#define I3C_IER_DEFIE_Pos (30U) +#define I3C_IER_DEFIE_Pos (30UL) #define I3C_IER_DEFIE_Msk (0x1UL << I3C_IER_DEFIE_Pos) /*!< 0x40000000 */ #define I3C_IER_DEFIE I3C_IER_DEFIE_Msk /*!< List of Targets Command Received Interrupt Enable */ -#define I3C_IER_GRPIE_Pos (31U) +#define I3C_IER_GRPIE_Pos (31UL) #define I3C_IER_GRPIE_Msk (0x1UL << I3C_IER_GRPIE_Pos) /*!< 0x80000000 */ #define I3C_IER_GRPIE I3C_IER_GRPIE_Msk /*!< List of Group Addresses Command Received Interrupt Enable */ /******************* Bit definition for I3C_CEVR register *******************/ -#define I3C_CEVR_CFCF_Pos (9U) +#define I3C_CEVR_CFCF_Pos (9UL) #define I3C_CEVR_CFCF_Msk (0x1UL << I3C_CEVR_CFCF_Pos) /*!< 0x00000200 */ #define I3C_CEVR_CFCF I3C_CEVR_CFCF_Msk /*!< Frame Complete Clear Flag */ -#define I3C_CEVR_CRXTGTENDF_Pos (10U) +#define I3C_CEVR_CRXTGTENDF_Pos (10UL) #define I3C_CEVR_CRXTGTENDF_Msk (0x1UL << I3C_CEVR_CRXTGTENDF_Pos) /*!< 0x00000400 */ #define I3C_CEVR_CRXTGTENDF I3C_CEVR_CRXTGTENDF_Msk /*!< Reception Target End Clear Flag */ -#define I3C_CEVR_CERRF_Pos (11U) +#define I3C_CEVR_CERRF_Pos (11UL) #define I3C_CEVR_CERRF_Msk (0x1UL << I3C_CEVR_CERRF_Pos) /*!< 0x00000800 */ #define I3C_CEVR_CERRF I3C_CEVR_CERRF_Msk /*!< Error Clear Flag */ -#define I3C_CEVR_CIBIF_Pos (15U) +#define I3C_CEVR_CIBIF_Pos (15UL) #define I3C_CEVR_CIBIF_Msk (0x1UL << I3C_CEVR_CIBIF_Pos) /*!< 0x00008000 */ #define I3C_CEVR_CIBIF I3C_CEVR_CIBIF_Msk /*!< IBI Clear Flag */ -#define I3C_CEVR_CIBIENDF_Pos (16U) +#define I3C_CEVR_CIBIENDF_Pos (16UL) #define I3C_CEVR_CIBIENDF_Msk (0x1UL << I3C_CEVR_CIBIENDF_Pos) /*!< 0x00010000 */ #define I3C_CEVR_CIBIENDF I3C_CEVR_CIBIENDF_Msk /*!< IBI End Clear Flag */ -#define I3C_CEVR_CCRF_Pos (17U) +#define I3C_CEVR_CCRF_Pos (17UL) #define I3C_CEVR_CCRF_Msk (0x1UL << I3C_CEVR_CCRF_Pos) /*!< 0x00020000 */ #define I3C_CEVR_CCRF I3C_CEVR_CCRF_Msk /*!< Controller-role Clear Flag */ -#define I3C_CEVR_CCRUPDF_Pos (18U) +#define I3C_CEVR_CCRUPDF_Pos (18UL) #define I3C_CEVR_CCRUPDF_Msk (0x1UL << I3C_CEVR_CCRUPDF_Pos) /*!< 0x00040000 */ #define I3C_CEVR_CCRUPDF I3C_CEVR_CCRUPDF_Msk /*!< Controller-role Update Clear Flag */ -#define I3C_CEVR_CHJF_Pos (19U) +#define I3C_CEVR_CHJF_Pos (19UL) #define I3C_CEVR_CHJF_Msk (0x1UL << I3C_CEVR_CHJF_Pos) /*!< 0x00080000 */ #define I3C_CEVR_CHJF I3C_CEVR_CHJF_Msk /*!< Hot Join Clear Flag */ -#define I3C_CEVR_CWKPF_Pos (21U) +#define I3C_CEVR_CWKPF_Pos (21UL) #define I3C_CEVR_CWKPF_Msk (0x1UL << I3C_CEVR_CWKPF_Pos) /*!< 0x00200000 */ #define I3C_CEVR_CWKPF I3C_CEVR_CWKPF_Msk /*!< Wake Up Clear Flag */ -#define I3C_CEVR_CGETF_Pos (22U) +#define I3C_CEVR_CGETF_Pos (22UL) #define I3C_CEVR_CGETF_Msk (0x1UL << I3C_CEVR_CGETF_Pos) /*!< 0x00400000 */ #define I3C_CEVR_CGETF I3C_CEVR_CGETF_Msk /*!< Get type CCC received Clear Flag */ -#define I3C_CEVR_CSTAF_Pos (23U) +#define I3C_CEVR_CSTAF_Pos (23UL) #define I3C_CEVR_CSTAF_Msk (0x1UL << I3C_CEVR_CSTAF_Pos) /*!< 0x00800000 */ #define I3C_CEVR_CSTAF I3C_CEVR_CSTAF_Msk /*!< Get Status Clear Flag */ -#define I3C_CEVR_CDAUPDF_Pos (24U) +#define I3C_CEVR_CDAUPDF_Pos (24UL) #define I3C_CEVR_CDAUPDF_Msk (0x1UL << I3C_CEVR_CDAUPDF_Pos) /*!< 0x01000000 */ #define I3C_CEVR_CDAUPDF I3C_CEVR_CDAUPDF_Msk /*!< Dynamic Address Update Clear Flag */ -#define I3C_CEVR_CMWLUPDF_Pos (25U) +#define I3C_CEVR_CMWLUPDF_Pos (25UL) #define I3C_CEVR_CMWLUPDF_Msk (0x1UL << I3C_CEVR_CMWLUPDF_Pos) /*!< 0x02000000 */ #define I3C_CEVR_CMWLUPDF I3C_CEVR_CMWLUPDF_Msk /*!< Max Write Length Update Clear Flag */ -#define I3C_CEVR_CMRLUPDF_Pos (26U) +#define I3C_CEVR_CMRLUPDF_Pos (26UL) #define I3C_CEVR_CMRLUPDF_Msk (0x1UL << I3C_CEVR_CMRLUPDF_Pos) /*!< 0x04000000 */ #define I3C_CEVR_CMRLUPDF I3C_CEVR_CMRLUPDF_Msk /*!< Max Read Length Update Clear Flag */ -#define I3C_CEVR_CRSTF_Pos (27U) +#define I3C_CEVR_CRSTF_Pos (27UL) #define I3C_CEVR_CRSTF_Msk (0x1UL << I3C_CEVR_CRSTF_Pos) /*!< 0x08000000 */ #define I3C_CEVR_CRSTF I3C_CEVR_CRSTF_Msk /*!< Reset Flag, due to Reset pattern received */ -#define I3C_CEVR_CASUPDF_Pos (28U) +#define I3C_CEVR_CASUPDF_Pos (28UL) #define I3C_CEVR_CASUPDF_Msk (0x1UL << I3C_CEVR_CASUPDF_Pos) /*!< 0x10000000 */ #define I3C_CEVR_CASUPDF I3C_CEVR_CASUPDF_Msk /*!< Activity State Clear Flag */ -#define I3C_CEVR_CINTUPDF_Pos (29U) +#define I3C_CEVR_CINTUPDF_Pos (29UL) #define I3C_CEVR_CINTUPDF_Msk (0x1UL << I3C_CEVR_CINTUPDF_Pos) /*!< 0x20000000 */ #define I3C_CEVR_CINTUPDF I3C_CEVR_CINTUPDF_Msk /*!< Interrupt Update Clear Flag */ -#define I3C_CEVR_CDEFF_Pos (30U) +#define I3C_CEVR_CDEFF_Pos (30UL) #define I3C_CEVR_CDEFF_Msk (0x1UL << I3C_CEVR_CDEFF_Pos) /*!< 0x40000000 */ #define I3C_CEVR_CDEFF I3C_CEVR_CDEFF_Msk /*!< List of Targets Command Received Clear Flag */ -#define I3C_CEVR_CGRPF_Pos (31U) +#define I3C_CEVR_CGRPF_Pos (31UL) #define I3C_CEVR_CGRPF_Msk (0x1UL << I3C_CEVR_CGRPF_Pos) /*!< 0x80000000 */ #define I3C_CEVR_CGRPF I3C_CEVR_CGRPF_Msk /*!< List of Group Addresses Command Received Clear Flag */ /******************* Bit definition for I3C_MISR register *******************/ -#define I3C_MISR_CFNFMIS_Pos (2U) +#define I3C_MISR_CFNFMIS_Pos (2UL) #define I3C_MISR_CFNFMIS_Msk (0x1UL << I3C_MISR_CFNFMIS_Pos) /*!< 0x00000004 */ #define I3C_MISR_CFNFMIS I3C_MISR_CFNFMIS_Msk /*!< Control FIFO Not Full Mask Interrupt Status */ -#define I3C_MISR_SFNEMIS_Pos (3U) +#define I3C_MISR_SFNEMIS_Pos (3UL) #define I3C_MISR_SFNEMIS_Msk (0x1UL << I3C_MISR_SFNEMIS_Pos) /*!< 0x00000008 */ #define I3C_MISR_SFNEMIS I3C_MISR_SFNEMIS_Msk /*!< Status FIFO Not Empty Mask Interrupt Status */ -#define I3C_MISR_TXFNFMIS_Pos (4U) +#define I3C_MISR_TXFNFMIS_Pos (4UL) #define I3C_MISR_TXFNFMIS_Msk (0x1UL << I3C_MISR_TXFNFMIS_Pos) /*!< 0x00000010 */ #define I3C_MISR_TXFNFMIS I3C_MISR_TXFNFMIS_Msk /*!< TX FIFO Not Full Mask Interrupt Status */ -#define I3C_MISR_RXFNEMIS_Pos (5U) +#define I3C_MISR_RXFNEMIS_Pos (5UL) #define I3C_MISR_RXFNEMIS_Msk (0x1UL << I3C_MISR_RXFNEMIS_Pos) /*!< 0x00000020 */ #define I3C_MISR_RXFNEMIS I3C_MISR_RXFNEMIS_Msk /*!< RX FIFO Not Empty Mask Interrupt Status */ -#define I3C_MISR_FCMIS_Pos (9U) +#define I3C_MISR_FCMIS_Pos (9UL) #define I3C_MISR_FCMIS_Msk (0x1UL << I3C_MISR_FCMIS_Pos) /*!< 0x00000200 */ #define I3C_MISR_FCMIS I3C_MISR_FCMIS_Msk /*!< Frame Complete Mask Interrupt Status */ -#define I3C_MISR_RXTGTENDMIS_Pos (10U) +#define I3C_MISR_RXTGTENDMIS_Pos (10UL) #define I3C_MISR_RXTGTENDMIS_Msk (0x1UL << I3C_MISR_RXTGTENDMIS_Pos) /*!< 0x00000400 */ #define I3C_MISR_RXTGTENDMIS I3C_MISR_RXTGTENDMIS_Msk /*!< Reception Target End Mask Interrupt Status */ -#define I3C_MISR_ERRMIS_Pos (11U) +#define I3C_MISR_ERRMIS_Pos (11UL) #define I3C_MISR_ERRMIS_Msk (0x1UL << I3C_MISR_ERRMIS_Pos) /*!< 0x00000800 */ #define I3C_MISR_ERRMIS I3C_MISR_ERRMIS_Msk /*!< Error Mask Interrupt Status */ -#define I3C_MISR_IBIMIS_Pos (15U) +#define I3C_MISR_IBIMIS_Pos (15UL) #define I3C_MISR_IBIMIS_Msk (0x1UL << I3C_MISR_IBIMIS_Pos) /*!< 0x00008000 */ #define I3C_MISR_IBIMIS I3C_MISR_IBIMIS_Msk /*!< IBI Mask Interrupt Status */ -#define I3C_MISR_IBIENDMIS_Pos (16U) +#define I3C_MISR_IBIENDMIS_Pos (16UL) #define I3C_MISR_IBIENDMIS_Msk (0x1UL << I3C_MISR_IBIENDMIS_Pos) /*!< 0x00010000 */ #define I3C_MISR_IBIENDMIS I3C_MISR_IBIENDMIS_Msk /*!< IBI End Mask Interrupt Status */ -#define I3C_MISR_CRMIS_Pos (17U) +#define I3C_MISR_CRMIS_Pos (17UL) #define I3C_MISR_CRMIS_Msk (0x1UL << I3C_MISR_CRMIS_Pos) /*!< 0x00020000 */ #define I3C_MISR_CRMIS I3C_MISR_CRMIS_Msk /*!< Controller-role Mask Interrupt Status */ -#define I3C_MISR_CRUPDMIS_Pos (18U) +#define I3C_MISR_CRUPDMIS_Pos (18UL) #define I3C_MISR_CRUPDMIS_Msk (0x1UL << I3C_MISR_CRUPDMIS_Pos) /*!< 0x00040000 */ #define I3C_MISR_CRUPDMIS I3C_MISR_CRUPDMIS_Msk /*!< Controller-role Update Mask Interrupt Status */ -#define I3C_MISR_HJMIS_Pos (19U) +#define I3C_MISR_HJMIS_Pos (19UL) #define I3C_MISR_HJMIS_Msk (0x1UL << I3C_MISR_HJMIS_Pos) /*!< 0x00080000 */ #define I3C_MISR_HJMIS I3C_MISR_HJMIS_Msk /*!< Hot Join Mask Interrupt Status */ -#define I3C_MISR_WKPMIS_Pos (21U) +#define I3C_MISR_WKPMIS_Pos (21UL) #define I3C_MISR_WKPMIS_Msk (0x1UL << I3C_MISR_WKPMIS_Pos) /*!< 0x00200000 */ #define I3C_MISR_WKPMIS I3C_MISR_WKPMIS_Msk /*!< Wake Up Mask Interrupt Status */ -#define I3C_MISR_GETMIS_Pos (22U) +#define I3C_MISR_GETMIS_Pos (22UL) #define I3C_MISR_GETMIS_Msk (0x1UL << I3C_MISR_GETMIS_Pos) /*!< 0x00400000 */ #define I3C_MISR_GETMIS I3C_MISR_GETMIS_Msk /*!< Get type CCC received Mask Interrupt Status */ -#define I3C_MISR_STAMIS_Pos (23U) +#define I3C_MISR_STAMIS_Pos (23UL) #define I3C_MISR_STAMIS_Msk (0x1UL << I3C_MISR_STAMIS_Pos) /*!< 0x00800000 */ #define I3C_MISR_STAMIS I3C_MISR_STAMIS_Msk /*!< Get Status Mask Interrupt Status */ -#define I3C_MISR_DAUPDMIS_Pos (24U) +#define I3C_MISR_DAUPDMIS_Pos (24UL) #define I3C_MISR_DAUPDMIS_Msk (0x1UL << I3C_MISR_DAUPDMIS_Pos) /*!< 0x01000000 */ #define I3C_MISR_DAUPDMIS I3C_MISR_DAUPDMIS_Msk /*!< Dynamic Address Update Mask Interrupt Status */ -#define I3C_MISR_MWLUPDMIS_Pos (25U) +#define I3C_MISR_MWLUPDMIS_Pos (25UL) #define I3C_MISR_MWLUPDMIS_Msk (0x1UL << I3C_MISR_MWLUPDMIS_Pos) /*!< 0x02000000 */ #define I3C_MISR_MWLUPDMIS I3C_MISR_MWLUPDMIS_Msk /*!< Max Write Length Update Mask Interrupt Status */ -#define I3C_MISR_MRLUPDMIS_Pos (26U) +#define I3C_MISR_MRLUPDMIS_Pos (26UL) #define I3C_MISR_MRLUPDMIS_Msk (0x1UL << I3C_MISR_MRLUPDMIS_Pos) /*!< 0x04000000 */ #define I3C_MISR_MRLUPDMIS I3C_MISR_MRLUPDMIS_Msk /*!< Max Read Length Update Mask Interrupt Status */ -#define I3C_MISR_RSTMIS_Pos (27U) +#define I3C_MISR_RSTMIS_Pos (27UL) #define I3C_MISR_RSTMIS_Msk (0x1UL << I3C_MISR_RSTMIS_Pos) /*!< 0x08000000 */ #define I3C_MISR_RSTMIS I3C_MISR_RSTMIS_Msk /*!< Reset Mask Interrupt Status, due to Reset pattern received */ -#define I3C_MISR_ASUPDMIS_Pos (28U) +#define I3C_MISR_ASUPDMIS_Pos (28UL) #define I3C_MISR_ASUPDMIS_Msk (0x1UL << I3C_MISR_ASUPDMIS_Pos) /*!< 0x10000000 */ #define I3C_MISR_ASUPDMIS I3C_MISR_ASUPDMIS_Msk /*!< Activity State Mask Interrupt Status */ -#define I3C_MISR_INTUPDMIS_Pos (29U) +#define I3C_MISR_INTUPDMIS_Pos (29UL) #define I3C_MISR_INTUPDMIS_Msk (0x1UL << I3C_MISR_INTUPDMIS_Pos) /*!< 0x20000000 */ #define I3C_MISR_INTUPDMIS I3C_MISR_INTUPDMIS_Msk /*!< Interrupt Update Mask Interrupt Status */ -#define I3C_MISR_DEFMIS_Pos (30U) +#define I3C_MISR_DEFMIS_Pos (30UL) #define I3C_MISR_DEFMIS_Msk (0x1UL << I3C_MISR_DEFMIS_Pos) /*!< 0x40000000 */ #define I3C_MISR_DEFMIS I3C_MISR_DEFMIS_Msk /*!< List of Targets Command Received Mask Interrupt Status */ -#define I3C_MISR_GRPMIS_Pos (31U) +#define I3C_MISR_GRPMIS_Pos (31UL) #define I3C_MISR_GRPMIS_Msk (0x1UL << I3C_MISR_GRPMIS_Pos) /*!< 0x80000000 */ #define I3C_MISR_GRPMIS I3C_MISR_GRPMIS_Msk /*!< List of Group Addresses Command Received Mask Interrupt Status */ /****************** Bit definition for I3C_DEVR0 register *******************/ -#define I3C_DEVR0_DAVAL_Pos (0U) +#define I3C_DEVR0_DAVAL_Pos (0UL) #define I3C_DEVR0_DAVAL_Msk (0x1UL << I3C_DEVR0_DAVAL_Pos) /*!< 0x00000001 */ #define I3C_DEVR0_DAVAL I3C_DEVR0_DAVAL_Msk /*!< Dynamic Address Validity */ -#define I3C_DEVR0_DA_Pos (1U) +#define I3C_DEVR0_DA_Pos (1UL) #define I3C_DEVR0_DA_Msk (0x7FUL << I3C_DEVR0_DA_Pos) /*!< 0x000000FE */ #define I3C_DEVR0_DA I3C_DEVR0_DA_Msk /*!< Own Target Device Address */ -#define I3C_DEVR0_IBIEN_Pos (16U) +#define I3C_DEVR0_IBIEN_Pos (16UL) #define I3C_DEVR0_IBIEN_Msk (0x1UL << I3C_DEVR0_IBIEN_Pos) /*!< 0x00010000 */ #define I3C_DEVR0_IBIEN I3C_DEVR0_IBIEN_Msk /*!< IBI Enable */ -#define I3C_DEVR0_CREN_Pos (17U) +#define I3C_DEVR0_CREN_Pos (17UL) #define I3C_DEVR0_CREN_Msk (0x1UL << I3C_DEVR0_CREN_Pos) /*!< 0x00020000 */ #define I3C_DEVR0_CREN I3C_DEVR0_CREN_Msk /*!< Controller-role Enable */ -#define I3C_DEVR0_HJEN_Pos (19U) +#define I3C_DEVR0_HJEN_Pos (19UL) #define I3C_DEVR0_HJEN_Msk (0x1UL << I3C_DEVR0_HJEN_Pos) /*!< 0x00080000 */ #define I3C_DEVR0_HJEN I3C_DEVR0_HJEN_Msk /*!< Hot Join Enable */ -#define I3C_DEVR0_AS_Pos (20U) +#define I3C_DEVR0_AS_Pos (20UL) #define I3C_DEVR0_AS_Msk (0x3UL << I3C_DEVR0_AS_Pos) /*!< 0x00300000 */ #define I3C_DEVR0_AS I3C_DEVR0_AS_Msk /*!< Activity State value update after ENTAx received */ #define I3C_DEVR0_AS_0 (0x1UL << I3C_DEVR0_AS_Pos) /*!< 0x00100000 */ #define I3C_DEVR0_AS_1 (0x2UL << I3C_DEVR0_AS_Pos) /*!< 0x00200000 */ -#define I3C_DEVR0_RSTACT_Pos (22U) +#define I3C_DEVR0_RSTACT_Pos (22UL) #define I3C_DEVR0_RSTACT_Msk (0x3UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00C000000 */ #define I3C_DEVR0_RSTACT I3C_DEVR0_RSTACT_Msk /*!< Reset Action value update after RSTACT received */ #define I3C_DEVR0_RSTACT_0 (0x1UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00400000 */ #define I3C_DEVR0_RSTACT_1 (0x2UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00800000 */ -#define I3C_DEVR0_RSTVAL_Pos (24U) +#define I3C_DEVR0_RSTVAL_Pos (24UL) #define I3C_DEVR0_RSTVAL_Msk (0x1UL << I3C_DEVR0_RSTVAL_Pos) /*!< 0x01000000 */ #define I3C_DEVR0_RSTVAL I3C_DEVR0_RSTVAL_Msk /*!< Reset Action Valid */ /****************** Bit definition for I3C_DEVRX register *******************/ -#define I3C_DEVRX_DA_Pos (1U) +#define I3C_DEVRX_DA_Pos (1UL) #define I3C_DEVRX_DA_Msk (0x7FUL << I3C_DEVRX_DA_Pos) /*!< 0x000000FE */ #define I3C_DEVRX_DA I3C_DEVRX_DA_Msk /*!< Dynamic Address Target x */ -#define I3C_DEVRX_IBIACK_Pos (16U) +#define I3C_DEVRX_IBIACK_Pos (16UL) #define I3C_DEVRX_IBIACK_Msk (0x1UL << I3C_DEVRX_IBIACK_Pos) /*!< 0x00010000 */ #define I3C_DEVRX_IBIACK I3C_DEVRX_IBIACK_Msk /*!< IBI Acknowledge from Target x */ -#define I3C_DEVRX_CRACK_Pos (17U) +#define I3C_DEVRX_CRACK_Pos (17UL) #define I3C_DEVRX_CRACK_Msk (0x1UL << I3C_DEVRX_CRACK_Pos) /*!< 0x00020000 */ #define I3C_DEVRX_CRACK I3C_DEVRX_CRACK_Msk /*!< Controller-role Acknowledge from Target x */ -#define I3C_DEVRX_IBIDEN_Pos (18U) +#define I3C_DEVRX_IBIDEN_Pos (18UL) #define I3C_DEVRX_IBIDEN_Msk (0x1UL << I3C_DEVRX_IBIDEN_Pos) /*!< 0x00040000 */ #define I3C_DEVRX_IBIDEN I3C_DEVRX_IBIDEN_Msk /*!< IBI Additional Data Enable */ -#define I3C_DEVRX_SUSP_Pos (19U) +#define I3C_DEVRX_SUSP_Pos (19UL) #define I3C_DEVRX_SUSP_Msk (0x1UL << I3C_DEVRX_SUSP_Pos) /*!< 0x00080000 */ #define I3C_DEVRX_SUSP I3C_DEVRX_SUSP_Msk /*!< Suspended Transfer */ -#define I3C_DEVRX_DIS_Pos (31U) +#define I3C_DEVRX_DIS_Pos (31UL) #define I3C_DEVRX_DIS_Msk (0x1UL << I3C_DEVRX_DIS_Pos) /*!< 0x80000000 */ #define I3C_DEVRX_DIS I3C_DEVRX_DIS_Msk /*!< Disable Register access */ /****************** Bit definition for I3C_MAXRLR register ******************/ -#define I3C_MAXRLR_MRL_Pos (0U) +#define I3C_MAXRLR_MRL_Pos (0UL) #define I3C_MAXRLR_MRL_Msk (0xFFFFUL << I3C_MAXRLR_MRL_Pos) /*!< 0x0000FFFF */ #define I3C_MAXRLR_MRL I3C_MAXRLR_MRL_Msk /*!< Maximum Read Length */ -#define I3C_MAXRLR_IBIP_Pos (16U) +#define I3C_MAXRLR_IBIP_Pos (16UL) #define I3C_MAXRLR_IBIP_Msk (0x7UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00070000 */ #define I3C_MAXRLR_IBIP I3C_MAXRLR_IBIP_Msk /*!< IBI Payload size */ #define I3C_MAXRLR_IBIP_0 (0x1UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00010000 */ @@ -14647,138 +14914,138 @@ typedef struct #define I3C_MAXRLR_IBIP_2 (0x4UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00040000 */ /****************** Bit definition for I3C_MAXWLR register ******************/ -#define I3C_MAXWLR_MWL_Pos (0U) +#define I3C_MAXWLR_MWL_Pos (0UL) #define I3C_MAXWLR_MWL_Msk (0xFFFFUL << I3C_MAXWLR_MWL_Pos) /*!< 0x0000FFFF */ #define I3C_MAXWLR_MWL I3C_MAXWLR_MWL_Msk /*!< Maximum Write Length */ /**************** Bit definition for I3C_TIMINGR0 register ******************/ -#define I3C_TIMINGR0_SCLL_PP_Pos (0U) +#define I3C_TIMINGR0_SCLL_PP_Pos (0UL) #define I3C_TIMINGR0_SCLL_PP_Msk (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos) /*!< 0x000000FF */ #define I3C_TIMINGR0_SCLL_PP I3C_TIMINGR0_SCLL_PP_Msk /*!< SCL Low duration during I3C Push-Pull phases */ -#define I3C_TIMINGR0_SCLH_I3C_Pos (8U) +#define I3C_TIMINGR0_SCLH_I3C_Pos (8UL) #define I3C_TIMINGR0_SCLH_I3C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos) /*!< 0x0000FF00 */ #define I3C_TIMINGR0_SCLH_I3C I3C_TIMINGR0_SCLH_I3C_Msk /*!< SCL High duration during I3C Open-drain and Push-Pull phases */ -#define I3C_TIMINGR0_SCLL_OD_Pos (16U) +#define I3C_TIMINGR0_SCLL_OD_Pos (16UL) #define I3C_TIMINGR0_SCLL_OD_Msk (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos) /*!< 0x00FF0000 */ #define I3C_TIMINGR0_SCLL_OD I3C_TIMINGR0_SCLL_OD_Msk /*!< SCL Low duration during I3C Open-drain phases and I2C transfer */ -#define I3C_TIMINGR0_SCLH_I2C_Pos (24U) +#define I3C_TIMINGR0_SCLH_I2C_Pos (24UL) #define I3C_TIMINGR0_SCLH_I2C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos) /*!< 0xFF000000 */ #define I3C_TIMINGR0_SCLH_I2C I3C_TIMINGR0_SCLH_I2C_Msk /*!< SCL High duration during I2C transfer */ /**************** Bit definition for I3C_TIMINGR1 register ******************/ -#define I3C_TIMINGR1_AVAL_Pos (0U) +#define I3C_TIMINGR1_AVAL_Pos (0UL) #define I3C_TIMINGR1_AVAL_Msk (0xFFUL << I3C_TIMINGR1_AVAL_Pos) /*!< 0x000000FF */ #define I3C_TIMINGR1_AVAL I3C_TIMINGR1_AVAL_Msk /*!< Timing for I3C Bus Idle or Available condition */ -#define I3C_TIMINGR1_ASNCR_Pos (8U) +#define I3C_TIMINGR1_ASNCR_Pos (8UL) #define I3C_TIMINGR1_ASNCR_Msk (0x3UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000300 */ #define I3C_TIMINGR1_ASNCR I3C_TIMINGR1_ASNCR_Msk /*!< Activity State of the New Controller */ #define I3C_TIMINGR1_ASNCR_0 (0x1UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000100 */ #define I3C_TIMINGR1_ASNCR_1 (0x2UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000200 */ -#define I3C_TIMINGR1_FREE_Pos (16U) +#define I3C_TIMINGR1_FREE_Pos (16UL) #define I3C_TIMINGR1_FREE_Msk (0x7FUL << I3C_TIMINGR1_FREE_Pos) /*!< 0x007F0000 */ #define I3C_TIMINGR1_FREE I3C_TIMINGR1_FREE_Msk /*!< Timing for I3C Bus Free condition */ -#define I3C_TIMINGR1_SDA_HD_Pos (28U) +#define I3C_TIMINGR1_SDA_HD_Pos (28UL) #define I3C_TIMINGR1_SDA_HD_Msk (0x3UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x30000000 */ #define I3C_TIMINGR1_SDA_HD I3C_TIMINGR1_SDA_HD_Msk /*!< SDA Hold Duration */ #define I3C_TIMINGR1_SDA_HD_0 (0x1UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x10000000 */ #define I3C_TIMINGR1_SDA_HD_1 (0x2UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x20000000 */ /**************** Bit definition for I3C_TIMINGR2 register ******************/ -#define I3C_TIMINGR2_STALLT_Pos (0U) +#define I3C_TIMINGR2_STALLT_Pos (0UL) #define I3C_TIMINGR2_STALLT_Msk (0x1UL << I3C_TIMINGR2_STALLT_Pos) /*!< 0x00000001 */ #define I3C_TIMINGR2_STALLT I3C_TIMINGR2_STALLT_Msk /*!< Stall on T bit */ -#define I3C_TIMINGR2_STALLD_Pos (1U) +#define I3C_TIMINGR2_STALLD_Pos (1UL) #define I3C_TIMINGR2_STALLD_Msk (0x1UL << I3C_TIMINGR2_STALLD_Pos) /*!< 0x00000002 */ #define I3C_TIMINGR2_STALLD I3C_TIMINGR2_STALLD_Msk /*!< Stall on PAR bit of data bytes */ -#define I3C_TIMINGR2_STALLC_Pos (2U) +#define I3C_TIMINGR2_STALLC_Pos (2UL) #define I3C_TIMINGR2_STALLC_Msk (0x1UL << I3C_TIMINGR2_STALLC_Pos) /*!< 0x00000004 */ #define I3C_TIMINGR2_STALLC I3C_TIMINGR2_STALLC_Msk /*!< Stall on PAR bit of CCC byte */ -#define I3C_TIMINGR2_STALLA_Pos (3U) +#define I3C_TIMINGR2_STALLA_Pos (3UL) #define I3C_TIMINGR2_STALLA_Msk (0x1UL << I3C_TIMINGR2_STALLA_Pos) /*!< 0x00000008 */ #define I3C_TIMINGR2_STALLA I3C_TIMINGR2_STALLA_Msk /*!< Stall on ACK bit */ -#define I3C_TIMINGR2_STALLR_Pos (4U) +#define I3C_TIMINGR2_STALLR_Pos (4UL) #define I3C_TIMINGR2_STALLR_Msk (0x1UL << I3C_TIMINGR2_STALLR_Pos) /*!< 0x00000010 */ #define I3C_TIMINGR2_STALLR I3C_TIMINGR2_STALLR_Msk /*!< Stall on I2C Read ACK bit */ -#define I3C_TIMINGR2_STALLS_Pos (5U) +#define I3C_TIMINGR2_STALLS_Pos (5UL) #define I3C_TIMINGR2_STALLS_Msk (0x1UL << I3C_TIMINGR2_STALLS_Pos) /*!< 0x00000020 */ #define I3C_TIMINGR2_STALLS I3C_TIMINGR2_STALLS_Msk /*!< Stall on I2C Write ACK bit */ -#define I3C_TIMINGR2_STALLL_Pos (6U) +#define I3C_TIMINGR2_STALLL_Pos (6UL) #define I3C_TIMINGR2_STALLL_Msk (0x1UL << I3C_TIMINGR2_STALLL_Pos) /*!< 0x00000040 */ #define I3C_TIMINGR2_STALLL I3C_TIMINGR2_STALLL_Msk /*!< Stall on I2C Address ACK bit */ -#define I3C_TIMINGR2_STALL_Pos (8U) +#define I3C_TIMINGR2_STALL_Pos (8UL) #define I3C_TIMINGR2_STALL_Msk (0xFFUL << I3C_TIMINGR2_STALL_Pos) /*!< 0x0000FF00 */ #define I3C_TIMINGR2_STALL I3C_TIMINGR2_STALL_Msk /*!< Controller Stall duration */ /******************* Bit definition for I3C_BCR register ********************/ -#define I3C_BCR_BCR_Pos (0U) +#define I3C_BCR_BCR_Pos (0UL) #define I3C_BCR_BCR_Msk (0xFFUL << I3C_BCR_BCR_Pos) /*!< 0x000000FF */ #define I3C_BCR_BCR I3C_BCR_BCR_Msk /*!< Bus Characteristics */ -#define I3C_BCR_BCR0_Pos (0U) +#define I3C_BCR_BCR0_Pos (0UL) #define I3C_BCR_BCR0_Msk (0x1UL << I3C_BCR_BCR0_Pos) /*!< 0x00000001 */ #define I3C_BCR_BCR0 I3C_BCR_BCR0_Msk /*!< Max Data Speed Limitation */ -#define I3C_BCR_BCR1_Pos (1U) +#define I3C_BCR_BCR1_Pos (1UL) #define I3C_BCR_BCR1_Msk (0x1UL << I3C_BCR_BCR1_Pos) /*!< 0x00000002 */ #define I3C_BCR_BCR1 I3C_BCR_BCR1_Msk /*!< IBI Request capable */ -#define I3C_BCR_BCR2_Pos (2U) +#define I3C_BCR_BCR2_Pos (2UL) #define I3C_BCR_BCR2_Msk (0x1UL << I3C_BCR_BCR2_Pos) /*!< 0x00000004 */ #define I3C_BCR_BCR2 I3C_BCR_BCR2_Msk /*!< IBI Payload additional Mandatory Data Byte */ -#define I3C_BCR_BCR3_Pos (3U) +#define I3C_BCR_BCR3_Pos (3UL) #define I3C_BCR_BCR3_Msk (0x1UL << I3C_BCR_BCR3_Pos) /*!< 0x00000008 */ #define I3C_BCR_BCR3 I3C_BCR_BCR3_Msk /*!< Offline capable */ -#define I3C_BCR_BCR4_Pos (4U) +#define I3C_BCR_BCR4_Pos (4UL) #define I3C_BCR_BCR4_Msk (0x1UL << I3C_BCR_BCR4_Pos) /*!< 0x00000010 */ #define I3C_BCR_BCR4 I3C_BCR_BCR4_Msk /*!< Virtual target support */ -#define I3C_BCR_BCR5_Pos (5U) +#define I3C_BCR_BCR5_Pos (5UL) #define I3C_BCR_BCR5_Msk (0x1UL << I3C_BCR_BCR5_Pos) /*!< 0x00000020 */ #define I3C_BCR_BCR5 I3C_BCR_BCR5_Msk /*!< Advanced capabilities */ -#define I3C_BCR_BCR6_Pos (6U) +#define I3C_BCR_BCR6_Pos (6UL) #define I3C_BCR_BCR6_Msk (0x1UL << I3C_BCR_BCR6_Pos) /*!< 0x00000040 */ #define I3C_BCR_BCR6 I3C_BCR_BCR6_Msk /*!< Device Role shared during Dynamic Address Assignment */ /******************* Bit definition for I3C_DCR register ********************/ -#define I3C_DCR_DCR_Pos (0U) +#define I3C_DCR_DCR_Pos (0UL) #define I3C_DCR_DCR_Msk (0xFFUL << I3C_DCR_DCR_Pos) /*!< 0x000000FF */ #define I3C_DCR_DCR I3C_DCR_DCR_Msk /*!< Devices Characteristics */ /***************** Bit definition for I3C_GETCAPR register ******************/ -#define I3C_GETCAPR_CAPPEND_Pos (14U) +#define I3C_GETCAPR_CAPPEND_Pos (14UL) #define I3C_GETCAPR_CAPPEND_Msk (0x1UL << I3C_GETCAPR_CAPPEND_Pos) /*!< 0x00004000 */ #define I3C_GETCAPR_CAPPEND I3C_GETCAPR_CAPPEND_Msk /*!< IBI Request with Mandatory Data Byte */ /***************** Bit definition for I3C_CRCAPR register *******************/ -#define I3C_CRCAPR_CAPDHOFF_Pos (3U) +#define I3C_CRCAPR_CAPDHOFF_Pos (3UL) #define I3C_CRCAPR_CAPDHOFF_Msk (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos) /*!< 0x00000008 */ #define I3C_CRCAPR_CAPDHOFF I3C_CRCAPR_CAPDHOFF_Msk /*!< Controller-role handoff needed */ -#define I3C_CRCAPR_CAPGRP_Pos (9U) +#define I3C_CRCAPR_CAPGRP_Pos (9UL) #define I3C_CRCAPR_CAPGRP_Msk (0x1UL << I3C_CRCAPR_CAPGRP_Pos) /*!< 0x00000200 */ #define I3C_CRCAPR_CAPGRP I3C_CRCAPR_CAPGRP_Msk /*!< Group Address handoff supported */ /**************** Bit definition for I3C_GETMXDSR register ******************/ -#define I3C_GETMXDSR_HOFFAS_Pos (0U) +#define I3C_GETMXDSR_HOFFAS_Pos (0UL) #define I3C_GETMXDSR_HOFFAS_Msk (0x3UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000003 */ #define I3C_GETMXDSR_HOFFAS I3C_GETMXDSR_HOFFAS_Msk /*!< Handoff Activity State */ #define I3C_GETMXDSR_HOFFAS_0 (0x1UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000001 */ #define I3C_GETMXDSR_HOFFAS_1 (0x2UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000002 */ -#define I3C_GETMXDSR_FMT_Pos (8U) +#define I3C_GETMXDSR_FMT_Pos (8UL) #define I3C_GETMXDSR_FMT_Msk (0x3UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000300 */ #define I3C_GETMXDSR_FMT I3C_GETMXDSR_FMT_Msk /*!< Get Max Data Speed response in format 2 */ #define I3C_GETMXDSR_FMT_0 (0x1UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000100 */ #define I3C_GETMXDSR_FMT_1 (0x2UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000200 */ -#define I3C_GETMXDSR_RDTURN_Pos (16U) +#define I3C_GETMXDSR_RDTURN_Pos (16UL) #define I3C_GETMXDSR_RDTURN_Msk (0xFFUL << I3C_GETMXDSR_RDTURN_Pos) /*!< 0x00FF0000 */ #define I3C_GETMXDSR_RDTURN I3C_GETMXDSR_RDTURN_Msk /*!< Max Read Turnaround Middle Byte */ -#define I3C_GETMXDSR_TSCO_Pos (24U) +#define I3C_GETMXDSR_TSCO_Pos (24UL) #define I3C_GETMXDSR_TSCO_Msk (0x1UL << I3C_GETMXDSR_TSCO_Pos) /*!< 0x01000000 */ #define I3C_GETMXDSR_TSCO I3C_GETMXDSR_TSCO_Msk /*!< Clock-to-data Turnaround time */ /****************** Bit definition for I3C_EPIDR register *******************/ -#define I3C_EPIDR_MIPIID_Pos (12U) +#define I3C_EPIDR_MIPIID_Pos (12UL) #define I3C_EPIDR_MIPIID_Msk (0xFUL << I3C_EPIDR_MIPIID_Pos) /*!< 0x0000F000 */ #define I3C_EPIDR_MIPIID I3C_EPIDR_MIPIID_Msk /*!< MIPI Instance ID */ -#define I3C_EPIDR_IDTSEL_Pos (16U) +#define I3C_EPIDR_IDTSEL_Pos (16UL) #define I3C_EPIDR_IDTSEL_Msk (0x1UL << I3C_EPIDR_IDTSEL_Pos) /*!< 0x00010000 */ #define I3C_EPIDR_IDTSEL I3C_EPIDR_IDTSEL_Msk /*!< ID Type Selector */ -#define I3C_EPIDR_MIPIMID_Pos (17U) +#define I3C_EPIDR_MIPIMID_Pos (17UL) #define I3C_EPIDR_MIPIMID_Msk (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos) /*!< 0xFFFE0000 */ #define I3C_EPIDR_MIPIMID I3C_EPIDR_MIPIMID_Msk /*!< MIPI Manufacturer ID */ @@ -14788,85 +15055,85 @@ typedef struct /* */ /******************************************************************************/ /****************** Bit definition for ICACHE_CR register *******************/ -#define ICACHE_CR_EN_Pos (0U) +#define ICACHE_CR_EN_Pos (0UL) #define ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) /*!< 0x00000001 */ #define ICACHE_CR_EN ICACHE_CR_EN_Msk /*!< Enable */ -#define ICACHE_CR_CACHEINV_Pos (1U) +#define ICACHE_CR_CACHEINV_Pos (1UL) #define ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ #define ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk /*!< Cache invalidation */ -#define ICACHE_CR_WAYSEL_Pos (2U) +#define ICACHE_CR_WAYSEL_Pos (2UL) #define ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) /*!< 0x00000004 */ #define ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk /*!< Ways selection */ -#define ICACHE_CR_HITMEN_Pos (16U) +#define ICACHE_CR_HITMEN_Pos (16UL) #define ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) /*!< 0x00010000 */ #define ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk /*!< Hit monitor enable */ -#define ICACHE_CR_MISSMEN_Pos (17U) +#define ICACHE_CR_MISSMEN_Pos (17UL) #define ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) /*!< 0x00020000 */ #define ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk /*!< Miss monitor enable */ -#define ICACHE_CR_HITMRST_Pos (18U) +#define ICACHE_CR_HITMRST_Pos (18UL) #define ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) /*!< 0x00040000 */ #define ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk /*!< Hit monitor reset */ -#define ICACHE_CR_MISSMRST_Pos (19U) +#define ICACHE_CR_MISSMRST_Pos (19UL) #define ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) /*!< 0x00080000 */ #define ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk /*!< Miss monitor reset */ /****************** Bit definition for ICACHE_SR register *******************/ -#define ICACHE_SR_BUSYF_Pos (0U) +#define ICACHE_SR_BUSYF_Pos (0UL) #define ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ #define ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk /*!< Busy flag */ -#define ICACHE_SR_BSYENDF_Pos (1U) +#define ICACHE_SR_BSYENDF_Pos (1UL) #define ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ #define ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk /*!< Busy end flag */ -#define ICACHE_SR_ERRF_Pos (2U) +#define ICACHE_SR_ERRF_Pos (2UL) #define ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) /*!< 0x00000004 */ #define ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk /*!< Cache error flag */ /****************** Bit definition for ICACHE_IER register ******************/ -#define ICACHE_IER_BSYENDIE_Pos (1U) +#define ICACHE_IER_BSYENDIE_Pos (1UL) #define ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ #define ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */ -#define ICACHE_IER_ERRIE_Pos (2U) +#define ICACHE_IER_ERRIE_Pos (2UL) #define ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ #define ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk /*!< Cache error interrupt enable */ /****************** Bit definition for ICACHE_FCR register ******************/ -#define ICACHE_FCR_CBSYENDF_Pos (1U) +#define ICACHE_FCR_CBSYENDF_Pos (1UL) #define ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ #define ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk /*!< Busy end flag clear */ -#define ICACHE_FCR_CERRF_Pos (2U) +#define ICACHE_FCR_CERRF_Pos (2UL) #define ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ #define ICACHE_FCR_CERRF ICACHE_FCR_CERRF_Msk /*!< Cache error flag clear */ /****************** Bit definition for ICACHE_HMONR register ****************/ -#define ICACHE_HMONR_HITMON_Pos (0U) +#define ICACHE_HMONR_HITMON_Pos (0UL) #define ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */ #define ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk /*!< Cache hit monitor register */ /****************** Bit definition for ICACHE_MMONR register ****************/ -#define ICACHE_MMONR_MISSMON_Pos (0U) +#define ICACHE_MMONR_MISSMON_Pos (0UL) #define ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */ #define ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk /*!< Cache miss monitor register */ /****************** Bit definition for ICACHE_CRRx register *****************/ -#define ICACHE_CRRx_BASEADDR_Pos (0U) +#define ICACHE_CRRx_BASEADDR_Pos (0UL) #define ICACHE_CRRx_BASEADDR_Msk (0xFFUL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x000000FF */ #define ICACHE_CRRx_BASEADDR ICACHE_CRRx_BASEADDR_Msk /*!< Base address of region X to remap */ -#define ICACHE_CRRx_RSIZE_Pos (9U) +#define ICACHE_CRRx_RSIZE_Pos (9UL) #define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00 */ #define ICACHE_CRRx_RSIZE ICACHE_CRRx_RSIZE_Msk /*!< Region X size */ #define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200 */ #define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400 */ #define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800 */ -#define ICACHE_CRRx_REN_Pos (15U) +#define ICACHE_CRRx_REN_Pos (15UL) #define ICACHE_CRRx_REN_Msk (0x1UL << ICACHE_CRRx_REN_Pos) /*!< 0x00008000 */ #define ICACHE_CRRx_REN ICACHE_CRRx_REN_Msk /*!< Region X enable */ -#define ICACHE_CRRx_REMAPADDR_Pos (16U) +#define ICACHE_CRRx_REMAPADDR_Pos (16UL) #define ICACHE_CRRx_REMAPADDR_Msk (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x07FF0000 */ #define ICACHE_CRRx_REMAPADDR ICACHE_CRRx_REMAPADDR_Msk /*!< Remap address of Region X to be remapped */ -#define ICACHE_CRRx_MSTSEL_Pos (28U) +#define ICACHE_CRRx_MSTSEL_Pos (28UL) #define ICACHE_CRRx_MSTSEL_Msk (0x1UL << ICACHE_CRRx_MSTSEL_Pos) /*!< 0x10000000 */ #define ICACHE_CRRx_MSTSEL ICACHE_CRRx_MSTSEL_Msk /*!< Region X AHB cache master selection */ -#define ICACHE_CRRx_HBURST_Pos (31U) +#define ICACHE_CRRx_HBURST_Pos (31UL) #define ICACHE_CRRx_HBURST_Msk (0x1UL << ICACHE_CRRx_HBURST_Pos) /*!< 0x80000000 */ #define ICACHE_CRRx_HBURST ICACHE_CRRx_HBURST_Msk /*!< Region X output burst type */ @@ -14876,12 +15143,12 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Pos (0UL) #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -19051,85 +19327,85 @@ typedef struct #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -19138,124 +19414,124 @@ typedef struct #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Pos (5UL) #define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_TAMPTSCR register ******************/ -#define RTC_TAMPTSCR_TAMP1TS_Pos (0U) +#define RTC_TAMPTSCR_TAMP1TS_Pos (0UL) #define RTC_TAMPTSCR_TAMP1TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP1TS_Pos) /*!< 0x00000001 */ #define RTC_TAMPTSCR_TAMP1TS RTC_TAMPTSCR_TAMP1TS_Msk -#define RTC_TAMPTSCR_TAMP2TS_Pos (1U) +#define RTC_TAMPTSCR_TAMP2TS_Pos (1UL) #define RTC_TAMPTSCR_TAMP2TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP2TS_Pos) /*!< 0x00000002 */ #define RTC_TAMPTSCR_TAMP2TS RTC_TAMPTSCR_TAMP2TS_Msk -#define RTC_TAMPTSCR_TAMP3TS_Pos (2U) +#define RTC_TAMPTSCR_TAMP3TS_Pos (2UL) #define RTC_TAMPTSCR_TAMP3TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP3TS_Pos) /*!< 0x00000004 */ #define RTC_TAMPTSCR_TAMP3TS RTC_TAMPTSCR_TAMP3TS_Msk -#define RTC_TAMPTSCR_TAMP4TS_Pos (3U) +#define RTC_TAMPTSCR_TAMP4TS_Pos (3UL) #define RTC_TAMPTSCR_TAMP4TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP4TS_Pos) /*!< 0x00000008 */ #define RTC_TAMPTSCR_TAMP4TS RTC_TAMPTSCR_TAMP4TS_Msk -#define RTC_TAMPTSCR_TAMP5TS_Pos (4U) +#define RTC_TAMPTSCR_TAMP5TS_Pos (4UL) #define RTC_TAMPTSCR_TAMP5TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP5TS_Pos) /*!< 0x00000010 */ #define RTC_TAMPTSCR_TAMP5TS RTC_TAMPTSCR_TAMP5TS_Msk -#define RTC_TAMPTSCR_ITAMPTS_Pos (16U) +#define RTC_TAMPTSCR_ITAMPTS_Pos (16UL) #define RTC_TAMPTSCR_ITAMPTS_Msk (0x1UL << RTC_TAMPTSCR_ITAMPTS_Pos) /*!< 0x00010000 */ #define RTC_TAMPTSCR_ITAMPTS RTC_TAMPTSCR_ITAMPTS_Msk /******************** Bits definition for RTC_TSIDR register ******************/ -#define RTC_TSIDR_TSID_Pos (0U) +#define RTC_TSIDR_TSID_Pos (0UL) #define RTC_TSIDR_TSID_Msk (0x3FUL << RTC_TSIDR_TSID_Pos) /*!< 0x0000003F */ #define RTC_TSIDR_TSID RTC_TSIDR_TSID_Msk #define RTC_TSIDR_TSID_0 (0x1UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000001 */ @@ -19266,12 +19542,12 @@ typedef struct #define RTC_TSIDR_TSID_5 (0x20UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000020 */ /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -19281,49 +19557,49 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for SAI_xCR1 register *******************/ -#define SAI_xCR1_MODE_Pos (0U) +#define SAI_xCR1_MODE_Pos (0UL) #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + /******************************************************************************/ /* */ /* VREFBUF */ /* */ /******************************************************************************/ /******************* Bit definition for VREFBUF_CSR register ****************/ -#define VREFBUF_CSR_ENVR_Pos (0U) +#define VREFBUF_CSR_ENVR_Pos (0UL) #define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ #define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!(1)) */ -/*!< TRGOEN configuration */ -#define HSP_ITFENR_TRGOEN_Pos (12U) + +#define HSP_ITFENR_TRGOEN_Pos (12UL) #define HSP_ITFENR_TRGOEN_Msk (0x1UL << HSP_ITFENR_TRGOEN_Pos) /*!< 0x00001000 */ #define HSP_ITFENR_TRGOEN HSP_ITFENR_TRGOEN_Msk /*!< TRGOEN (TRGO enable bit (1)) */ -/*!< TRGI0EN configuration */ -#define HSP_ITFENR_TRGI0EN_Pos (16U) + +#define HSP_ITFENR_TRGI0EN_Pos (16UL) #define HSP_ITFENR_TRGI0EN_Msk (0x1UL << HSP_ITFENR_TRGI0EN_Pos) /*!< 0x00010000 */ #define HSP_ITFENR_TRGI0EN HSP_ITFENR_TRGI0EN_Msk /*!< TRGI0EN (TRGIN0 enable bit (1)) */ -/*!< TRGI1EN configuration */ -#define HSP_ITFENR_TRGI1EN_Pos (17U) + +#define HSP_ITFENR_TRGI1EN_Pos (17UL) #define HSP_ITFENR_TRGI1EN_Msk (0x1UL << HSP_ITFENR_TRGI1EN_Pos) /*!< 0x00020000 */ #define HSP_ITFENR_TRGI1EN HSP_ITFENR_TRGI1EN_Msk /*!< TRGI1EN (TRGIN1 enable bit (1)) */ -/*!< TRGI2EN configuration */ -#define HSP_ITFENR_TRGI2EN_Pos (18U) + +#define HSP_ITFENR_TRGI2EN_Pos (18UL) #define HSP_ITFENR_TRGI2EN_Msk (0x1UL << HSP_ITFENR_TRGI2EN_Pos) /*!< 0x00040000 */ #define HSP_ITFENR_TRGI2EN HSP_ITFENR_TRGI2EN_Msk /*!< TRGI2EN (TRGIN2 enable bit (1)) */ -/*!< TRGI3EN configuration */ -#define HSP_ITFENR_TRGI3EN_Pos (19U) + +#define HSP_ITFENR_TRGI3EN_Pos (19UL) #define HSP_ITFENR_TRGI3EN_Msk (0x1UL << HSP_ITFENR_TRGI3EN_Pos) /*!< 0x00080000 */ #define HSP_ITFENR_TRGI3EN HSP_ITFENR_TRGI3EN_Msk /*!< TRGI3EN (TRGIN3 enable bit (1)) */ -/*!< TRGI4EN configuration */ -#define HSP_ITFENR_TRGI4EN_Pos (20U) + +#define HSP_ITFENR_TRGI4EN_Pos (20UL) #define HSP_ITFENR_TRGI4EN_Msk (0x1UL << HSP_ITFENR_TRGI4EN_Pos) /*!< 0x00100000 */ #define HSP_ITFENR_TRGI4EN HSP_ITFENR_TRGI4EN_Msk /*!< TRGI4EN (TRGIN4 enable bit (1)) */ -/*!< TRGI5EN configuration */ -#define HSP_ITFENR_TRGI5EN_Pos (21U) + +#define HSP_ITFENR_TRGI5EN_Pos (21UL) #define HSP_ITFENR_TRGI5EN_Msk (0x1UL << HSP_ITFENR_TRGI5EN_Pos) /*!< 0x00200000 */ #define HSP_ITFENR_TRGI5EN HSP_ITFENR_TRGI5EN_Msk /*!< TRGI5EN (TRGIN5 enable bit (1)) */ -/*!< TRGI6EN configuration */ -#define HSP_ITFENR_TRGI6EN_Pos (22U) + +#define HSP_ITFENR_TRGI6EN_Pos (22UL) #define HSP_ITFENR_TRGI6EN_Msk (0x1UL << HSP_ITFENR_TRGI6EN_Pos) /*!< 0x00400000 */ #define HSP_ITFENR_TRGI6EN HSP_ITFENR_TRGI6EN_Msk /*!< TRGI6EN (TRGIN6 enable bit (1)) */ -/*!< TRGI7EN configuration */ -#define HSP_ITFENR_TRGI7EN_Pos (23U) + +#define HSP_ITFENR_TRGI7EN_Pos (23UL) #define HSP_ITFENR_TRGI7EN_Msk (0x1UL << HSP_ITFENR_TRGI7EN_Pos) /*!< 0x00800000 */ #define HSP_ITFENR_TRGI7EN HSP_ITFENR_TRGI7EN_Msk /*!< TRGI7EN (TRGIN7 enable bit (1)) */ -/*!< TRGI8EN configuration */ -#define HSP_ITFENR_TRGI8EN_Pos (24U) + +#define HSP_ITFENR_TRGI8EN_Pos (24UL) #define HSP_ITFENR_TRGI8EN_Msk (0x1UL << HSP_ITFENR_TRGI8EN_Pos) /*!< 0x01000000 */ #define HSP_ITFENR_TRGI8EN HSP_ITFENR_TRGI8EN_Msk /*!< TRGI8EN (TRGIN8 enable bit (1)) */ -/*!< TRGI9EN configuration */ -#define HSP_ITFENR_TRGI9EN_Pos (25U) + +#define HSP_ITFENR_TRGI9EN_Pos (25UL) #define HSP_ITFENR_TRGI9EN_Msk (0x1UL << HSP_ITFENR_TRGI9EN_Pos) /*!< 0x02000000 */ #define HSP_ITFENR_TRGI9EN HSP_ITFENR_TRGI9EN_Msk /*!< TRGI9EN (TRGIN9 enable bit (1)) */ -/*!< DCMDDIS configuration */ -#define HSP_ITFENR_DCMDDIS_Pos (27U) + +#define HSP_ITFENR_DCMDDIS_Pos (27UL) #define HSP_ITFENR_DCMDDIS_Msk (0x1UL << HSP_ITFENR_DCMDDIS_Pos) /*!< 0x08000000 */ #define HSP_ITFENR_DCMDDIS HSP_ITFENR_DCMDDIS_Msk /*!< DCMDDIS (Direct command interface disable bit ) */ -/*!< CSEGEN configuration */ -#define HSP_ITFENR_CSEGEN_Pos (28U) + +#define HSP_ITFENR_CSEGEN_Pos (28UL) #define HSP_ITFENR_CSEGEN_Msk (0x1UL << HSP_ITFENR_CSEGEN_Pos) /*!< 0x10000000 */ #define HSP_ITFENR_CSEGEN HSP_ITFENR_CSEGEN_Msk /*!< CSEGEN (CSEG interface enable bit (1)) */ -/*!< CDEGEN configuration */ -#define HSP_ITFENR_CDEGEN_Pos (29U) + +#define HSP_ITFENR_CDEGEN_Pos (29UL) #define HSP_ITFENR_CDEGEN_Msk (0x1UL << HSP_ITFENR_CDEGEN_Pos) /*!< 0x20000000 */ #define HSP_ITFENR_CDEGEN HSP_ITFENR_CDEGEN_Msk /*!< CDEGEN (CDEG interface enable bit ) */ -/*!< HSEGEN configuration */ -#define HSP_ITFENR_HSEGEN_Pos (30U) + +#define HSP_ITFENR_HSEGEN_Pos (30UL) #define HSP_ITFENR_HSEGEN_Msk (0x1UL << HSP_ITFENR_HSEGEN_Pos) /*!< 0x40000000 */ #define HSP_ITFENR_HSEGEN HSP_ITFENR_HSEGEN_Msk /*!< HSEGEN (HSEG interface enable bit ) */ -/*!< HDEGEN configuration */ -#define HSP_ITFENR_HDEGEN_Pos (31U) + +#define HSP_ITFENR_HDEGEN_Pos (31UL) #define HSP_ITFENR_HDEGEN_Msk (0x1UL << HSP_ITFENR_HDEGEN_Pos) /*!< 0x80000000 */ #define HSP_ITFENR_HDEGEN HSP_ITFENR_HDEGEN_Msk /*!< HDEGEN (HDEG interface enable bit ) */ /******************** Bit definition for HSP_EVTSRC0R register ********************/ -/*!< EVT1SRC configuration */ -#define HSP_EVTSRC0R_EVT1SRC_Pos (0U) +#define HSP_EVTSRC0R_EVT1SRC_Pos (0UL) #define HSP_EVTSRC0R_EVT1SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT1SRC_Pos) /*!< 0x00000007 */ #define HSP_EVTSRC0R_EVT1SRC HSP_EVTSRC0R_EVT1SRC_Msk /*!< EVT1SRC[2:0] bits (Event source selection for priority encoder input 1) */ #define HSP_EVTSRC0R_EVT1SRC_0 (0x1UL << HSP_EVTSRC0R_EVT1SRC_Pos) /*!< 0x00000001 */ #define HSP_EVTSRC0R_EVT1SRC_1 (0x2UL << HSP_EVTSRC0R_EVT1SRC_Pos) /*!< 0x00000002 */ #define HSP_EVTSRC0R_EVT1SRC_2 (0x4UL << HSP_EVTSRC0R_EVT1SRC_Pos) /*!< 0x00000004 */ -/*!< EVT2SRC configuration */ -#define HSP_EVTSRC0R_EVT2SRC_Pos (4U) + +#define HSP_EVTSRC0R_EVT2SRC_Pos (4UL) #define HSP_EVTSRC0R_EVT2SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT2SRC_Pos) /*!< 0x00000070 */ #define HSP_EVTSRC0R_EVT2SRC HSP_EVTSRC0R_EVT2SRC_Msk /*!< EVT2SRC[2:0] bits (Event source selection for priority encoder input 2) */ #define HSP_EVTSRC0R_EVT2SRC_0 (0x1UL << HSP_EVTSRC0R_EVT2SRC_Pos) /*!< 0x00000010 */ #define HSP_EVTSRC0R_EVT2SRC_1 (0x2UL << HSP_EVTSRC0R_EVT2SRC_Pos) /*!< 0x00000020 */ #define HSP_EVTSRC0R_EVT2SRC_2 (0x4UL << HSP_EVTSRC0R_EVT2SRC_Pos) /*!< 0x00000040 */ -/*!< EVT3SRC configuration */ -#define HSP_EVTSRC0R_EVT3SRC_Pos (8U) + +#define HSP_EVTSRC0R_EVT3SRC_Pos (8UL) #define HSP_EVTSRC0R_EVT3SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT3SRC_Pos) /*!< 0x00000700 */ #define HSP_EVTSRC0R_EVT3SRC HSP_EVTSRC0R_EVT3SRC_Msk /*!< EVT3SRC[2:0] bits (Event source selection for priority encoder input 3) */ #define HSP_EVTSRC0R_EVT3SRC_0 (0x1UL << HSP_EVTSRC0R_EVT3SRC_Pos) /*!< 0x00000100 */ #define HSP_EVTSRC0R_EVT3SRC_1 (0x2UL << HSP_EVTSRC0R_EVT3SRC_Pos) /*!< 0x00000200 */ #define HSP_EVTSRC0R_EVT3SRC_2 (0x4UL << HSP_EVTSRC0R_EVT3SRC_Pos) /*!< 0x00000400 */ -/*!< EVT4SRC configuration */ -#define HSP_EVTSRC0R_EVT4SRC_Pos (12U) + +#define HSP_EVTSRC0R_EVT4SRC_Pos (12UL) #define HSP_EVTSRC0R_EVT4SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT4SRC_Pos) /*!< 0x00007000 */ #define HSP_EVTSRC0R_EVT4SRC HSP_EVTSRC0R_EVT4SRC_Msk /*!< EVT4SRC[2:0] bits (Event source selection for priority encoder input 4) */ #define HSP_EVTSRC0R_EVT4SRC_0 (0x1UL << HSP_EVTSRC0R_EVT4SRC_Pos) /*!< 0x00001000 */ #define HSP_EVTSRC0R_EVT4SRC_1 (0x2UL << HSP_EVTSRC0R_EVT4SRC_Pos) /*!< 0x00002000 */ #define HSP_EVTSRC0R_EVT4SRC_2 (0x4UL << HSP_EVTSRC0R_EVT4SRC_Pos) /*!< 0x00004000 */ -/*!< EVT5SRC configuration */ -#define HSP_EVTSRC0R_EVT5SRC_Pos (16U) + +#define HSP_EVTSRC0R_EVT5SRC_Pos (16UL) #define HSP_EVTSRC0R_EVT5SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT5SRC_Pos) /*!< 0x00070000 */ #define HSP_EVTSRC0R_EVT5SRC HSP_EVTSRC0R_EVT5SRC_Msk /*!< EVT5SRC[2:0] bits (Event source selection for priority encoder input 5) */ #define HSP_EVTSRC0R_EVT5SRC_0 (0x1UL << HSP_EVTSRC0R_EVT5SRC_Pos) /*!< 0x00010000 */ #define HSP_EVTSRC0R_EVT5SRC_1 (0x2UL << HSP_EVTSRC0R_EVT5SRC_Pos) /*!< 0x00020000 */ #define HSP_EVTSRC0R_EVT5SRC_2 (0x4UL << HSP_EVTSRC0R_EVT5SRC_Pos) /*!< 0x00040000 */ -/*!< EVT6SRC configuration */ -#define HSP_EVTSRC0R_EVT6SRC_Pos (20U) + +#define HSP_EVTSRC0R_EVT6SRC_Pos (20UL) #define HSP_EVTSRC0R_EVT6SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT6SRC_Pos) /*!< 0x00700000 */ #define HSP_EVTSRC0R_EVT6SRC HSP_EVTSRC0R_EVT6SRC_Msk /*!< EVT6SRC[2:0] bits (Event source selection for priority encoder input 6) */ #define HSP_EVTSRC0R_EVT6SRC_0 (0x1UL << HSP_EVTSRC0R_EVT6SRC_Pos) /*!< 0x00100000 */ #define HSP_EVTSRC0R_EVT6SRC_1 (0x2UL << HSP_EVTSRC0R_EVT6SRC_Pos) /*!< 0x00200000 */ #define HSP_EVTSRC0R_EVT6SRC_2 (0x4UL << HSP_EVTSRC0R_EVT6SRC_Pos) /*!< 0x00400000 */ -/*!< EVT7SRC configuration */ -#define HSP_EVTSRC0R_EVT7SRC_Pos (24U) + +#define HSP_EVTSRC0R_EVT7SRC_Pos (24UL) #define HSP_EVTSRC0R_EVT7SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT7SRC_Pos) /*!< 0x07000000 */ #define HSP_EVTSRC0R_EVT7SRC HSP_EVTSRC0R_EVT7SRC_Msk /*!< EVT7SRC[2:0] bits (Event source selection for priority encoder input 7) */ #define HSP_EVTSRC0R_EVT7SRC_0 (0x1UL << HSP_EVTSRC0R_EVT7SRC_Pos) /*!< 0x01000000 */ #define HSP_EVTSRC0R_EVT7SRC_1 (0x2UL << HSP_EVTSRC0R_EVT7SRC_Pos) /*!< 0x02000000 */ #define HSP_EVTSRC0R_EVT7SRC_2 (0x4UL << HSP_EVTSRC0R_EVT7SRC_Pos) /*!< 0x04000000 */ -/*!< EVT8SRC configuration */ -#define HSP_EVTSRC0R_EVT8SRC_Pos (28U) + +#define HSP_EVTSRC0R_EVT8SRC_Pos (28UL) #define HSP_EVTSRC0R_EVT8SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT8SRC_Pos) /*!< 0x70000000 */ #define HSP_EVTSRC0R_EVT8SRC HSP_EVTSRC0R_EVT8SRC_Msk /*!< EVT8SRC[2:0] bits (Event source selection for priority encoder input 8) */ #define HSP_EVTSRC0R_EVT8SRC_0 (0x1UL << HSP_EVTSRC0R_EVT8SRC_Pos) /*!< 0x10000000 */ @@ -11646,57 +13112,56 @@ typedef struct #define HSP_EVTSRC0R_EVT8SRC_2 (0x4UL << HSP_EVTSRC0R_EVT8SRC_Pos) /*!< 0x40000000 */ /******************** Bit definition for HSP_EVTSRC1R register ********************/ -/*!< EVT9SRC configuration */ -#define HSP_EVTSRC1R_EVT9SRC_Pos (0U) +#define HSP_EVTSRC1R_EVT9SRC_Pos (0UL) #define HSP_EVTSRC1R_EVT9SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT9SRC_Pos) /*!< 0x00000007 */ #define HSP_EVTSRC1R_EVT9SRC HSP_EVTSRC1R_EVT9SRC_Msk /*!< EVT9SRC[2:0] bits (Event source selection for priority encoder input 9) */ #define HSP_EVTSRC1R_EVT9SRC_0 (0x1UL << HSP_EVTSRC1R_EVT9SRC_Pos) /*!< 0x00000001 */ #define HSP_EVTSRC1R_EVT9SRC_1 (0x2UL << HSP_EVTSRC1R_EVT9SRC_Pos) /*!< 0x00000002 */ #define HSP_EVTSRC1R_EVT9SRC_2 (0x4UL << HSP_EVTSRC1R_EVT9SRC_Pos) /*!< 0x00000004 */ -/*!< EVT10SRC configuration */ -#define HSP_EVTSRC1R_EVT10SRC_Pos (4U) + +#define HSP_EVTSRC1R_EVT10SRC_Pos (4UL) #define HSP_EVTSRC1R_EVT10SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT10SRC_Pos) /*!< 0x00000070 */ #define HSP_EVTSRC1R_EVT10SRC HSP_EVTSRC1R_EVT10SRC_Msk /*!< EVT10SRC[2:0] bits (Event source selection for priority encoder input 10) */ #define HSP_EVTSRC1R_EVT10SRC_0 (0x1UL << HSP_EVTSRC1R_EVT10SRC_Pos) /*!< 0x00000010 */ #define HSP_EVTSRC1R_EVT10SRC_1 (0x2UL << HSP_EVTSRC1R_EVT10SRC_Pos) /*!< 0x00000020 */ #define HSP_EVTSRC1R_EVT10SRC_2 (0x4UL << HSP_EVTSRC1R_EVT10SRC_Pos) /*!< 0x00000040 */ -/*!< EVT11SRC configuration */ -#define HSP_EVTSRC1R_EVT11SRC_Pos (8U) + +#define HSP_EVTSRC1R_EVT11SRC_Pos (8UL) #define HSP_EVTSRC1R_EVT11SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT11SRC_Pos) /*!< 0x00000700 */ #define HSP_EVTSRC1R_EVT11SRC HSP_EVTSRC1R_EVT11SRC_Msk /*!< EVT11SRC[2:0] bits (Event source selection for priority encoder input 11) */ #define HSP_EVTSRC1R_EVT11SRC_0 (0x1UL << HSP_EVTSRC1R_EVT11SRC_Pos) /*!< 0x00000100 */ #define HSP_EVTSRC1R_EVT11SRC_1 (0x2UL << HSP_EVTSRC1R_EVT11SRC_Pos) /*!< 0x00000200 */ #define HSP_EVTSRC1R_EVT11SRC_2 (0x4UL << HSP_EVTSRC1R_EVT11SRC_Pos) /*!< 0x00000400 */ -/*!< EVT12SRC configuration */ -#define HSP_EVTSRC1R_EVT12SRC_Pos (12U) + +#define HSP_EVTSRC1R_EVT12SRC_Pos (12UL) #define HSP_EVTSRC1R_EVT12SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT12SRC_Pos) /*!< 0x00007000 */ #define HSP_EVTSRC1R_EVT12SRC HSP_EVTSRC1R_EVT12SRC_Msk /*!< EVT12SRC[2:0] bits (Event source selection for priority encoder input 12) */ #define HSP_EVTSRC1R_EVT12SRC_0 (0x1UL << HSP_EVTSRC1R_EVT12SRC_Pos) /*!< 0x00001000 */ #define HSP_EVTSRC1R_EVT12SRC_1 (0x2UL << HSP_EVTSRC1R_EVT12SRC_Pos) /*!< 0x00002000 */ #define HSP_EVTSRC1R_EVT12SRC_2 (0x4UL << HSP_EVTSRC1R_EVT12SRC_Pos) /*!< 0x00004000 */ -/*!< EVT13SRC configuration */ -#define HSP_EVTSRC1R_EVT13SRC_Pos (16U) + +#define HSP_EVTSRC1R_EVT13SRC_Pos (16UL) #define HSP_EVTSRC1R_EVT13SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT13SRC_Pos) /*!< 0x00070000 */ #define HSP_EVTSRC1R_EVT13SRC HSP_EVTSRC1R_EVT13SRC_Msk /*!< EVT13SRC[2:0] bits (Event source selection for priority encoder input 13) */ #define HSP_EVTSRC1R_EVT13SRC_0 (0x1UL << HSP_EVTSRC1R_EVT13SRC_Pos) /*!< 0x00010000 */ #define HSP_EVTSRC1R_EVT13SRC_1 (0x2UL << HSP_EVTSRC1R_EVT13SRC_Pos) /*!< 0x00020000 */ #define HSP_EVTSRC1R_EVT13SRC_2 (0x4UL << HSP_EVTSRC1R_EVT13SRC_Pos) /*!< 0x00040000 */ -/*!< EVT14SRC configuration */ -#define HSP_EVTSRC1R_EVT14SRC_Pos (20U) + +#define HSP_EVTSRC1R_EVT14SRC_Pos (20UL) #define HSP_EVTSRC1R_EVT14SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT14SRC_Pos) /*!< 0x00700000 */ #define HSP_EVTSRC1R_EVT14SRC HSP_EVTSRC1R_EVT14SRC_Msk /*!< EVT14SRC[2:0] bits (Event source selection for priority encoder input 14) */ #define HSP_EVTSRC1R_EVT14SRC_0 (0x1UL << HSP_EVTSRC1R_EVT14SRC_Pos) /*!< 0x00100000 */ #define HSP_EVTSRC1R_EVT14SRC_1 (0x2UL << HSP_EVTSRC1R_EVT14SRC_Pos) /*!< 0x00200000 */ #define HSP_EVTSRC1R_EVT14SRC_2 (0x4UL << HSP_EVTSRC1R_EVT14SRC_Pos) /*!< 0x00400000 */ -/*!< EVT15SRC configuration */ -#define HSP_EVTSRC1R_EVT15SRC_Pos (24U) + +#define HSP_EVTSRC1R_EVT15SRC_Pos (24UL) #define HSP_EVTSRC1R_EVT15SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT15SRC_Pos) /*!< 0x07000000 */ #define HSP_EVTSRC1R_EVT15SRC HSP_EVTSRC1R_EVT15SRC_Msk /*!< EVT15SRC[2:0] bits (Event source selection for priority encoder input 15) */ #define HSP_EVTSRC1R_EVT15SRC_0 (0x1UL << HSP_EVTSRC1R_EVT15SRC_Pos) /*!< 0x01000000 */ #define HSP_EVTSRC1R_EVT15SRC_1 (0x2UL << HSP_EVTSRC1R_EVT15SRC_Pos) /*!< 0x02000000 */ #define HSP_EVTSRC1R_EVT15SRC_2 (0x4UL << HSP_EVTSRC1R_EVT15SRC_Pos) /*!< 0x04000000 */ -/*!< EVT16SRC configuration */ -#define HSP_EVTSRC1R_EVT16SRC_Pos (28U) + +#define HSP_EVTSRC1R_EVT16SRC_Pos (28UL) #define HSP_EVTSRC1R_EVT16SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT16SRC_Pos) /*!< 0x70000000 */ #define HSP_EVTSRC1R_EVT16SRC HSP_EVTSRC1R_EVT16SRC_Msk /*!< EVT16SRC[2:0] bits (Event source selection for priority encoder input 16) */ #define HSP_EVTSRC1R_EVT16SRC_0 (0x1UL << HSP_EVTSRC1R_EVT16SRC_Pos) /*!< 0x10000000 */ @@ -11704,43 +13169,42 @@ typedef struct #define HSP_EVTSRC1R_EVT16SRC_2 (0x4UL << HSP_EVTSRC1R_EVT16SRC_Pos) /*!< 0x40000000 */ /******************** Bit definition for HSP_EVTSRC2R register ********************/ -/*!< EVT17SRC configuration */ -#define HSP_EVTSRC2R_EVT17SRC_Pos (0U) +#define HSP_EVTSRC2R_EVT17SRC_Pos (0UL) #define HSP_EVTSRC2R_EVT17SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT17SRC_Pos) /*!< 0x00000007 */ #define HSP_EVTSRC2R_EVT17SRC HSP_EVTSRC2R_EVT17SRC_Msk /*!< EVT17SRC[2:0] bits (Event source selection for priority encoder input 17) */ #define HSP_EVTSRC2R_EVT17SRC_0 (0x1UL << HSP_EVTSRC2R_EVT17SRC_Pos) /*!< 0x00000001 */ #define HSP_EVTSRC2R_EVT17SRC_1 (0x2UL << HSP_EVTSRC2R_EVT17SRC_Pos) /*!< 0x00000002 */ #define HSP_EVTSRC2R_EVT17SRC_2 (0x4UL << HSP_EVTSRC2R_EVT17SRC_Pos) /*!< 0x00000004 */ -/*!< EVT18SRC configuration */ -#define HSP_EVTSRC2R_EVT18SRC_Pos (4U) + +#define HSP_EVTSRC2R_EVT18SRC_Pos (4UL) #define HSP_EVTSRC2R_EVT18SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT18SRC_Pos) /*!< 0x00000070 */ #define HSP_EVTSRC2R_EVT18SRC HSP_EVTSRC2R_EVT18SRC_Msk /*!< EVT18SRC[2:0] bits (Event source selection for priority encoder input 18) */ #define HSP_EVTSRC2R_EVT18SRC_0 (0x1UL << HSP_EVTSRC2R_EVT18SRC_Pos) /*!< 0x00000010 */ #define HSP_EVTSRC2R_EVT18SRC_1 (0x2UL << HSP_EVTSRC2R_EVT18SRC_Pos) /*!< 0x00000020 */ #define HSP_EVTSRC2R_EVT18SRC_2 (0x4UL << HSP_EVTSRC2R_EVT18SRC_Pos) /*!< 0x00000040 */ -/*!< EVT19SRC configuration */ -#define HSP_EVTSRC2R_EVT19SRC_Pos (8U) + +#define HSP_EVTSRC2R_EVT19SRC_Pos (8UL) #define HSP_EVTSRC2R_EVT19SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT19SRC_Pos) /*!< 0x00000700 */ #define HSP_EVTSRC2R_EVT19SRC HSP_EVTSRC2R_EVT19SRC_Msk /*!< EVT19SRC[2:0] bits (Event source selection for priority encoder input 19) */ #define HSP_EVTSRC2R_EVT19SRC_0 (0x1UL << HSP_EVTSRC2R_EVT19SRC_Pos) /*!< 0x00000100 */ #define HSP_EVTSRC2R_EVT19SRC_1 (0x2UL << HSP_EVTSRC2R_EVT19SRC_Pos) /*!< 0x00000200 */ #define HSP_EVTSRC2R_EVT19SRC_2 (0x4UL << HSP_EVTSRC2R_EVT19SRC_Pos) /*!< 0x00000400 */ -/*!< EVT20SRC configuration */ -#define HSP_EVTSRC2R_EVT20SRC_Pos (12U) + +#define HSP_EVTSRC2R_EVT20SRC_Pos (12UL) #define HSP_EVTSRC2R_EVT20SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT20SRC_Pos) /*!< 0x00007000 */ #define HSP_EVTSRC2R_EVT20SRC HSP_EVTSRC2R_EVT20SRC_Msk /*!< EVT20SRC[2:0] bits (Event source selection for priority encoder input 20) */ #define HSP_EVTSRC2R_EVT20SRC_0 (0x1UL << HSP_EVTSRC2R_EVT20SRC_Pos) /*!< 0x00001000 */ #define HSP_EVTSRC2R_EVT20SRC_1 (0x2UL << HSP_EVTSRC2R_EVT20SRC_Pos) /*!< 0x00002000 */ #define HSP_EVTSRC2R_EVT20SRC_2 (0x4UL << HSP_EVTSRC2R_EVT20SRC_Pos) /*!< 0x00004000 */ -/*!< EVT21SRC configuration */ -#define HSP_EVTSRC2R_EVT21SRC_Pos (16U) + +#define HSP_EVTSRC2R_EVT21SRC_Pos (16UL) #define HSP_EVTSRC2R_EVT21SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT21SRC_Pos) /*!< 0x00070000 */ #define HSP_EVTSRC2R_EVT21SRC HSP_EVTSRC2R_EVT21SRC_Msk /*!< EVT21SRC[2:0] bits (Event source selection for priority encoder input 21) */ #define HSP_EVTSRC2R_EVT21SRC_0 (0x1UL << HSP_EVTSRC2R_EVT21SRC_Pos) /*!< 0x00010000 */ #define HSP_EVTSRC2R_EVT21SRC_1 (0x2UL << HSP_EVTSRC2R_EVT21SRC_Pos) /*!< 0x00020000 */ #define HSP_EVTSRC2R_EVT21SRC_2 (0x4UL << HSP_EVTSRC2R_EVT21SRC_Pos) /*!< 0x00040000 */ -/*!< EVT22SRC configuration */ -#define HSP_EVTSRC2R_EVT22SRC_Pos (20U) + +#define HSP_EVTSRC2R_EVT22SRC_Pos (20UL) #define HSP_EVTSRC2R_EVT22SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT22SRC_Pos) /*!< 0x00700000 */ #define HSP_EVTSRC2R_EVT22SRC HSP_EVTSRC2R_EVT22SRC_Msk /*!< EVT22SRC[2:0] bits (Event source selection for priority encoder input 22) */ #define HSP_EVTSRC2R_EVT22SRC_0 (0x1UL << HSP_EVTSRC2R_EVT22SRC_Pos) /*!< 0x00100000 */ @@ -11748,262 +13212,111 @@ typedef struct #define HSP_EVTSRC2R_EVT22SRC_2 (0x4UL << HSP_EVTSRC2R_EVT22SRC_Pos) /*!< 0x00400000 */ /******************** Bit definition for HSP_BUFFCFGR register ********************/ -/*!< BUFF0DIR configuration */ -#define HSP_BUFFCFGR_BUFF0DIR_Pos (0U) +#define HSP_BUFFCFGR_BUFF0DIR_Pos (0UL) #define HSP_BUFFCFGR_BUFF0DIR_Msk (0x1UL << HSP_BUFFCFGR_BUFF0DIR_Pos) /*!< 0x00000001 */ #define HSP_BUFFCFGR_BUFF0DIR HSP_BUFFCFGR_BUFF0DIR_Msk /*!< BUFF0DIR (Direction selection of BUFF0 (1)) */ -/*!< BUFF1DIR configuration */ -#define HSP_BUFFCFGR_BUFF1DIR_Pos (1U) + +#define HSP_BUFFCFGR_BUFF1DIR_Pos (1UL) #define HSP_BUFFCFGR_BUFF1DIR_Msk (0x1UL << HSP_BUFFCFGR_BUFF1DIR_Pos) /*!< 0x00000002 */ #define HSP_BUFFCFGR_BUFF1DIR HSP_BUFFCFGR_BUFF1DIR_Msk /*!< BUFF1DIR (Direction selection of BUFF1 (1)) */ -/*!< BUFF2DIR configuration */ -#define HSP_BUFFCFGR_BUFF2DIR_Pos (2U) + +#define HSP_BUFFCFGR_BUFF2DIR_Pos (2UL) #define HSP_BUFFCFGR_BUFF2DIR_Msk (0x1UL << HSP_BUFFCFGR_BUFF2DIR_Pos) /*!< 0x00000004 */ #define HSP_BUFFCFGR_BUFF2DIR HSP_BUFFCFGR_BUFF2DIR_Msk /*!< BUFF2DIR (Direction selection of BUFF2 (1)) */ -/*!< BUFF3DIR configuration */ -#define HSP_BUFFCFGR_BUFF3DIR_Pos (3U) + +#define HSP_BUFFCFGR_BUFF3DIR_Pos (3UL) #define HSP_BUFFCFGR_BUFF3DIR_Msk (0x1UL << HSP_BUFFCFGR_BUFF3DIR_Pos) /*!< 0x00000008 */ #define HSP_BUFFCFGR_BUFF3DIR HSP_BUFFCFGR_BUFF3DIR_Msk /*!< BUFF3DIR (Direction selection of BUFF3 (1)) */ -/*!< I2FEN configuration */ -#define HSP_BUFFCFGR_I2FEN_Pos (8U) + +#define HSP_BUFFCFGR_I2FEN_Pos (8UL) #define HSP_BUFFCFGR_I2FEN_Msk (0x1UL << HSP_BUFFCFGR_I2FEN_Pos) /*!< 0x00000100 */ #define HSP_BUFFCFGR_I2FEN HSP_BUFFCFGR_I2FEN_Msk /*!< I2FEN (integer to float32 conversion (1)) */ -/*!< COMB0 configuration */ -#define HSP_BUFFCFGR_COMB0_Pos (16U) + +#define HSP_BUFFCFGR_COMB0_Pos (16UL) #define HSP_BUFFCFGR_COMB0_Msk (0x1UL << HSP_BUFFCFGR_COMB0_Pos) /*!< 0x00010000 */ #define HSP_BUFFCFGR_COMB0 HSP_BUFFCFGR_COMB0_Msk /*!< COMB0 (BUFCMB control for buff_evt[0] (1)) */ -/*!< COMB1 configuration */ -#define HSP_BUFFCFGR_COMB1_Pos (17U) + +#define HSP_BUFFCFGR_COMB1_Pos (17UL) #define HSP_BUFFCFGR_COMB1_Msk (0x1UL << HSP_BUFFCFGR_COMB1_Pos) /*!< 0x00020000 */ #define HSP_BUFFCFGR_COMB1 HSP_BUFFCFGR_COMB1_Msk /*!< COMB1 (BUFCMB control for buff_evt[1] (1)) */ -/*!< COMB2 configuration */ -#define HSP_BUFFCFGR_COMB2_Pos (18U) + +#define HSP_BUFFCFGR_COMB2_Pos (18UL) #define HSP_BUFFCFGR_COMB2_Msk (0x1UL << HSP_BUFFCFGR_COMB2_Pos) /*!< 0x00040000 */ #define HSP_BUFFCFGR_COMB2 HSP_BUFFCFGR_COMB2_Msk /*!< COMB2 (BUFCMB control for buff_evt[2] ) */ -/******************** Bit definition for HSP_BUFF0DR register ********************/ -/*!< BUFFDAT configuration */ -#define HSP_BUFF0DR_BUFFDAT_Pos (0U) -#define HSP_BUFF0DR_BUFFDAT_Msk (0xFFFFFFFFUL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0xFFFFFFFF */ -#define HSP_BUFF0DR_BUFFDAT HSP_BUFF0DR_BUFFDAT_Msk /*!< BUFFDAT[31:0] bits (Data buffer) */ -#define HSP_BUFF0DR_BUFFDAT_0 (0x00001UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00000001 */ -#define HSP_BUFF0DR_BUFFDAT_1 (0x00002UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00000002 */ -#define HSP_BUFF0DR_BUFFDAT_2 (0x00004UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00000004 */ -#define HSP_BUFF0DR_BUFFDAT_3 (0x00008UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00000008 */ -#define HSP_BUFF0DR_BUFFDAT_4 (0x00010UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00000010 */ -#define HSP_BUFF0DR_BUFFDAT_5 (0x00020UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00000020 */ -#define HSP_BUFF0DR_BUFFDAT_6 (0x00040UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00000040 */ -#define HSP_BUFF0DR_BUFFDAT_7 (0x00080UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00000080 */ -#define HSP_BUFF0DR_BUFFDAT_8 (0x00100UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00000100 */ -#define HSP_BUFF0DR_BUFFDAT_9 (0x00200UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00000200 */ -#define HSP_BUFF0DR_BUFFDAT_10 (0x00400UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00000400 */ -#define HSP_BUFF0DR_BUFFDAT_11 (0x00800UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00000800 */ -#define HSP_BUFF0DR_BUFFDAT_12 (0x01000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00001000 */ -#define HSP_BUFF0DR_BUFFDAT_13 (0x02000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00002000 */ -#define HSP_BUFF0DR_BUFFDAT_14 (0x04000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00004000 */ -#define HSP_BUFF0DR_BUFFDAT_15 (0x08000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00008000 */ -#define HSP_BUFF0DR_BUFFDAT_16 (0x10000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00010000 */ -#define HSP_BUFF0DR_BUFFDAT_17 (0x20000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00020000 */ -#define HSP_BUFF0DR_BUFFDAT_18 (0x40000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00040000 */ -#define HSP_BUFF0DR_BUFFDAT_19 (0x80000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00080000 */ -#define HSP_BUFF0DR_BUFFDAT_20 (0x100000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00100000 */ -#define HSP_BUFF0DR_BUFFDAT_21 (0x200000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00200000 */ -#define HSP_BUFF0DR_BUFFDAT_22 (0x400000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00400000 */ -#define HSP_BUFF0DR_BUFFDAT_23 (0x800000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x00800000 */ -#define HSP_BUFF0DR_BUFFDAT_24 (0x1000000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x01000000 */ -#define HSP_BUFF0DR_BUFFDAT_25 (0x2000000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x02000000 */ -#define HSP_BUFF0DR_BUFFDAT_26 (0x4000000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x04000000 */ -#define HSP_BUFF0DR_BUFFDAT_27 (0x8000000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x08000000 */ -#define HSP_BUFF0DR_BUFFDAT_28 (0x10000000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x10000000 */ -#define HSP_BUFF0DR_BUFFDAT_29 (0x20000000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x20000000 */ -#define HSP_BUFF0DR_BUFFDAT_30 (0x40000000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x40000000 */ -#define HSP_BUFF0DR_BUFFDAT_31 (0x80000000UL << HSP_BUFF0DR_BUFFDAT_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for HSP_BUFF1DR register ********************/ -/*!< BUFFDAT configuration */ -#define HSP_BUFF1DR_BUFFDAT_Pos (0U) -#define HSP_BUFF1DR_BUFFDAT_Msk (0xFFFFFFFFUL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0xFFFFFFFF */ -#define HSP_BUFF1DR_BUFFDAT HSP_BUFF1DR_BUFFDAT_Msk /*!< BUFFDAT[31:0] bits (Data buffer) */ -#define HSP_BUFF1DR_BUFFDAT_0 (0x00001UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00000001 */ -#define HSP_BUFF1DR_BUFFDAT_1 (0x00002UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00000002 */ -#define HSP_BUFF1DR_BUFFDAT_2 (0x00004UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00000004 */ -#define HSP_BUFF1DR_BUFFDAT_3 (0x00008UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00000008 */ -#define HSP_BUFF1DR_BUFFDAT_4 (0x00010UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00000010 */ -#define HSP_BUFF1DR_BUFFDAT_5 (0x00020UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00000020 */ -#define HSP_BUFF1DR_BUFFDAT_6 (0x00040UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00000040 */ -#define HSP_BUFF1DR_BUFFDAT_7 (0x00080UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00000080 */ -#define HSP_BUFF1DR_BUFFDAT_8 (0x00100UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00000100 */ -#define HSP_BUFF1DR_BUFFDAT_9 (0x00200UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00000200 */ -#define HSP_BUFF1DR_BUFFDAT_10 (0x00400UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00000400 */ -#define HSP_BUFF1DR_BUFFDAT_11 (0x00800UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00000800 */ -#define HSP_BUFF1DR_BUFFDAT_12 (0x01000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00001000 */ -#define HSP_BUFF1DR_BUFFDAT_13 (0x02000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00002000 */ -#define HSP_BUFF1DR_BUFFDAT_14 (0x04000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00004000 */ -#define HSP_BUFF1DR_BUFFDAT_15 (0x08000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00008000 */ -#define HSP_BUFF1DR_BUFFDAT_16 (0x10000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00010000 */ -#define HSP_BUFF1DR_BUFFDAT_17 (0x20000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00020000 */ -#define HSP_BUFF1DR_BUFFDAT_18 (0x40000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00040000 */ -#define HSP_BUFF1DR_BUFFDAT_19 (0x80000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00080000 */ -#define HSP_BUFF1DR_BUFFDAT_20 (0x100000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00100000 */ -#define HSP_BUFF1DR_BUFFDAT_21 (0x200000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00200000 */ -#define HSP_BUFF1DR_BUFFDAT_22 (0x400000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00400000 */ -#define HSP_BUFF1DR_BUFFDAT_23 (0x800000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x00800000 */ -#define HSP_BUFF1DR_BUFFDAT_24 (0x1000000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x01000000 */ -#define HSP_BUFF1DR_BUFFDAT_25 (0x2000000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x02000000 */ -#define HSP_BUFF1DR_BUFFDAT_26 (0x4000000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x04000000 */ -#define HSP_BUFF1DR_BUFFDAT_27 (0x8000000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x08000000 */ -#define HSP_BUFF1DR_BUFFDAT_28 (0x10000000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x10000000 */ -#define HSP_BUFF1DR_BUFFDAT_29 (0x20000000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x20000000 */ -#define HSP_BUFF1DR_BUFFDAT_30 (0x40000000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x40000000 */ -#define HSP_BUFF1DR_BUFFDAT_31 (0x80000000UL << HSP_BUFF1DR_BUFFDAT_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for HSP_BUFF2DR register ********************/ -/*!< BUFFDAT configuration */ -#define HSP_BUFF2DR_BUFFDAT_Pos (0U) -#define HSP_BUFF2DR_BUFFDAT_Msk (0xFFFFFFFFUL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0xFFFFFFFF */ -#define HSP_BUFF2DR_BUFFDAT HSP_BUFF2DR_BUFFDAT_Msk /*!< BUFFDAT[31:0] bits (Data buffer) */ -#define HSP_BUFF2DR_BUFFDAT_0 (0x00001UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00000001 */ -#define HSP_BUFF2DR_BUFFDAT_1 (0x00002UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00000002 */ -#define HSP_BUFF2DR_BUFFDAT_2 (0x00004UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00000004 */ -#define HSP_BUFF2DR_BUFFDAT_3 (0x00008UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00000008 */ -#define HSP_BUFF2DR_BUFFDAT_4 (0x00010UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00000010 */ -#define HSP_BUFF2DR_BUFFDAT_5 (0x00020UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00000020 */ -#define HSP_BUFF2DR_BUFFDAT_6 (0x00040UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00000040 */ -#define HSP_BUFF2DR_BUFFDAT_7 (0x00080UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00000080 */ -#define HSP_BUFF2DR_BUFFDAT_8 (0x00100UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00000100 */ -#define HSP_BUFF2DR_BUFFDAT_9 (0x00200UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00000200 */ -#define HSP_BUFF2DR_BUFFDAT_10 (0x00400UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00000400 */ -#define HSP_BUFF2DR_BUFFDAT_11 (0x00800UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00000800 */ -#define HSP_BUFF2DR_BUFFDAT_12 (0x01000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00001000 */ -#define HSP_BUFF2DR_BUFFDAT_13 (0x02000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00002000 */ -#define HSP_BUFF2DR_BUFFDAT_14 (0x04000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00004000 */ -#define HSP_BUFF2DR_BUFFDAT_15 (0x08000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00008000 */ -#define HSP_BUFF2DR_BUFFDAT_16 (0x10000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00010000 */ -#define HSP_BUFF2DR_BUFFDAT_17 (0x20000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00020000 */ -#define HSP_BUFF2DR_BUFFDAT_18 (0x40000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00040000 */ -#define HSP_BUFF2DR_BUFFDAT_19 (0x80000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00080000 */ -#define HSP_BUFF2DR_BUFFDAT_20 (0x100000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00100000 */ -#define HSP_BUFF2DR_BUFFDAT_21 (0x200000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00200000 */ -#define HSP_BUFF2DR_BUFFDAT_22 (0x400000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00400000 */ -#define HSP_BUFF2DR_BUFFDAT_23 (0x800000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x00800000 */ -#define HSP_BUFF2DR_BUFFDAT_24 (0x1000000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x01000000 */ -#define HSP_BUFF2DR_BUFFDAT_25 (0x2000000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x02000000 */ -#define HSP_BUFF2DR_BUFFDAT_26 (0x4000000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x04000000 */ -#define HSP_BUFF2DR_BUFFDAT_27 (0x8000000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x08000000 */ -#define HSP_BUFF2DR_BUFFDAT_28 (0x10000000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x10000000 */ -#define HSP_BUFF2DR_BUFFDAT_29 (0x20000000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x20000000 */ -#define HSP_BUFF2DR_BUFFDAT_30 (0x40000000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x40000000 */ -#define HSP_BUFF2DR_BUFFDAT_31 (0x80000000UL << HSP_BUFF2DR_BUFFDAT_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for HSP_BUFF3DR register ********************/ -/*!< BUFFDAT configuration */ -#define HSP_BUFF3DR_BUFFDAT_Pos (0U) -#define HSP_BUFF3DR_BUFFDAT_Msk (0xFFFFFFFFUL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0xFFFFFFFF */ -#define HSP_BUFF3DR_BUFFDAT HSP_BUFF3DR_BUFFDAT_Msk /*!< BUFFDAT[31:0] bits (Data buffer) */ -#define HSP_BUFF3DR_BUFFDAT_0 (0x00001UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00000001 */ -#define HSP_BUFF3DR_BUFFDAT_1 (0x00002UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00000002 */ -#define HSP_BUFF3DR_BUFFDAT_2 (0x00004UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00000004 */ -#define HSP_BUFF3DR_BUFFDAT_3 (0x00008UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00000008 */ -#define HSP_BUFF3DR_BUFFDAT_4 (0x00010UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00000010 */ -#define HSP_BUFF3DR_BUFFDAT_5 (0x00020UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00000020 */ -#define HSP_BUFF3DR_BUFFDAT_6 (0x00040UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00000040 */ -#define HSP_BUFF3DR_BUFFDAT_7 (0x00080UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00000080 */ -#define HSP_BUFF3DR_BUFFDAT_8 (0x00100UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00000100 */ -#define HSP_BUFF3DR_BUFFDAT_9 (0x00200UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00000200 */ -#define HSP_BUFF3DR_BUFFDAT_10 (0x00400UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00000400 */ -#define HSP_BUFF3DR_BUFFDAT_11 (0x00800UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00000800 */ -#define HSP_BUFF3DR_BUFFDAT_12 (0x01000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00001000 */ -#define HSP_BUFF3DR_BUFFDAT_13 (0x02000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00002000 */ -#define HSP_BUFF3DR_BUFFDAT_14 (0x04000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00004000 */ -#define HSP_BUFF3DR_BUFFDAT_15 (0x08000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00008000 */ -#define HSP_BUFF3DR_BUFFDAT_16 (0x10000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00010000 */ -#define HSP_BUFF3DR_BUFFDAT_17 (0x20000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00020000 */ -#define HSP_BUFF3DR_BUFFDAT_18 (0x40000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00040000 */ -#define HSP_BUFF3DR_BUFFDAT_19 (0x80000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00080000 */ -#define HSP_BUFF3DR_BUFFDAT_20 (0x100000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00100000 */ -#define HSP_BUFF3DR_BUFFDAT_21 (0x200000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00200000 */ -#define HSP_BUFF3DR_BUFFDAT_22 (0x400000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00400000 */ -#define HSP_BUFF3DR_BUFFDAT_23 (0x800000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x00800000 */ -#define HSP_BUFF3DR_BUFFDAT_24 (0x1000000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x01000000 */ -#define HSP_BUFF3DR_BUFFDAT_25 (0x2000000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x02000000 */ -#define HSP_BUFF3DR_BUFFDAT_26 (0x4000000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x04000000 */ -#define HSP_BUFF3DR_BUFFDAT_27 (0x8000000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x08000000 */ -#define HSP_BUFF3DR_BUFFDAT_28 (0x10000000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x10000000 */ -#define HSP_BUFF3DR_BUFFDAT_29 (0x20000000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x20000000 */ -#define HSP_BUFF3DR_BUFFDAT_30 (0x40000000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x40000000 */ -#define HSP_BUFF3DR_BUFFDAT_31 (0x80000000UL << HSP_BUFF3DR_BUFFDAT_Pos) /*!< 0x80000000 */ +/******************** Bit definition for HSP_BUFFxDR register ********************/ +#define HSP_BUFFDR_BUFFDAT_Pos (0UL) +#define HSP_BUFFDR_BUFFDAT_Msk (0xFFFFFFFFUL << HSP_BUFFDR_BUFFDAT_Pos) /*!< 0xFFFFFFFF */ +#define HSP_BUFFDR_BUFFDAT HSP_BUFFDR_BUFFDAT_Msk /*!< BUFFDAT[31:0] bits (Data buffer) */ /******************** Bit definition for HSP_TRGINCFGR register ********************/ -/*!< TRG0POL configuration */ -#define HSP_TRGINCFGR_TRG0POL_Pos (0U) +#define HSP_TRGINCFGR_TRG0POL_Pos (0UL) #define HSP_TRGINCFGR_TRG0POL_Msk (0x1UL << HSP_TRGINCFGR_TRG0POL_Pos) /*!< 0x00000001 */ #define HSP_TRGINCFGR_TRG0POL HSP_TRGINCFGR_TRG0POL_Msk /*!< TRG0POL (Polarity selection for TRGIN0) */ -/*!< TRG1POL configuration */ -#define HSP_TRGINCFGR_TRG1POL_Pos (1U) + +#define HSP_TRGINCFGR_TRG1POL_Pos (1UL) #define HSP_TRGINCFGR_TRG1POL_Msk (0x1UL << HSP_TRGINCFGR_TRG1POL_Pos) /*!< 0x00000002 */ #define HSP_TRGINCFGR_TRG1POL HSP_TRGINCFGR_TRG1POL_Msk /*!< TRG1POL (Polarity selection for TRGIN1) */ -/*!< TRG2POL configuration */ -#define HSP_TRGINCFGR_TRG2POL_Pos (2U) + +#define HSP_TRGINCFGR_TRG2POL_Pos (2UL) #define HSP_TRGINCFGR_TRG2POL_Msk (0x1UL << HSP_TRGINCFGR_TRG2POL_Pos) /*!< 0x00000004 */ #define HSP_TRGINCFGR_TRG2POL HSP_TRGINCFGR_TRG2POL_Msk /*!< TRG2POL (Polarity selection for TRGIN2) */ -/*!< TRG3POL configuration */ -#define HSP_TRGINCFGR_TRG3POL_Pos (3U) + +#define HSP_TRGINCFGR_TRG3POL_Pos (3UL) #define HSP_TRGINCFGR_TRG3POL_Msk (0x1UL << HSP_TRGINCFGR_TRG3POL_Pos) /*!< 0x00000008 */ #define HSP_TRGINCFGR_TRG3POL HSP_TRGINCFGR_TRG3POL_Msk /*!< TRG3POL (Polarity selection for TRGIN3) */ -/*!< TRG4POL configuration */ -#define HSP_TRGINCFGR_TRG4POL_Pos (4U) + +#define HSP_TRGINCFGR_TRG4POL_Pos (4UL) #define HSP_TRGINCFGR_TRG4POL_Msk (0x1UL << HSP_TRGINCFGR_TRG4POL_Pos) /*!< 0x00000010 */ #define HSP_TRGINCFGR_TRG4POL HSP_TRGINCFGR_TRG4POL_Msk /*!< TRG4POL (Polarity selection for TRGIN4) */ -/*!< TRG5POL configuration */ -#define HSP_TRGINCFGR_TRG5POL_Pos (5U) + +#define HSP_TRGINCFGR_TRG5POL_Pos (5UL) #define HSP_TRGINCFGR_TRG5POL_Msk (0x1UL << HSP_TRGINCFGR_TRG5POL_Pos) /*!< 0x00000020 */ #define HSP_TRGINCFGR_TRG5POL HSP_TRGINCFGR_TRG5POL_Msk /*!< TRG5POL (Polarity selection for TRGIN5) */ -/*!< TRG6POL configuration */ -#define HSP_TRGINCFGR_TRG6POL_Pos (6U) + +#define HSP_TRGINCFGR_TRG6POL_Pos (6UL) #define HSP_TRGINCFGR_TRG6POL_Msk (0x1UL << HSP_TRGINCFGR_TRG6POL_Pos) /*!< 0x00000040 */ #define HSP_TRGINCFGR_TRG6POL HSP_TRGINCFGR_TRG6POL_Msk /*!< TRG6POL (Polarity selection for TRGIN6) */ -/*!< TRG7POL configuration */ -#define HSP_TRGINCFGR_TRG7POL_Pos (7U) + +#define HSP_TRGINCFGR_TRG7POL_Pos (7UL) #define HSP_TRGINCFGR_TRG7POL_Msk (0x1UL << HSP_TRGINCFGR_TRG7POL_Pos) /*!< 0x00000080 */ #define HSP_TRGINCFGR_TRG7POL HSP_TRGINCFGR_TRG7POL_Msk /*!< TRG7POL (Polarity selection for TRGIN7) */ -/*!< TRG8POL configuration */ -#define HSP_TRGINCFGR_TRG8POL_Pos (8U) + +#define HSP_TRGINCFGR_TRG8POL_Pos (8UL) #define HSP_TRGINCFGR_TRG8POL_Msk (0x1UL << HSP_TRGINCFGR_TRG8POL_Pos) /*!< 0x00000100 */ #define HSP_TRGINCFGR_TRG8POL HSP_TRGINCFGR_TRG8POL_Msk /*!< TRG8POL (Polarity selection for TRGIN8) */ -/*!< TRG9POL configuration */ -#define HSP_TRGINCFGR_TRG9POL_Pos (9U) + +#define HSP_TRGINCFGR_TRG9POL_Pos (9UL) #define HSP_TRGINCFGR_TRG9POL_Msk (0x1UL << HSP_TRGINCFGR_TRG9POL_Pos) /*!< 0x00000200 */ #define HSP_TRGINCFGR_TRG9POL HSP_TRGINCFGR_TRG9POL_Msk /*!< TRG9POL (Polarity selection for TRGIN9) */ /******************** Bit definition for HSP_TRGOCFGR register ********************/ -/*!< TRGO0SRC configuration */ -#define HSP_TRGOCFGR_TRGO0SRC_Pos (0U) +#define HSP_TRGOCFGR_TRGO0SRC_Pos (0UL) #define HSP_TRGOCFGR_TRGO0SRC_Msk (0x3UL << HSP_TRGOCFGR_TRGO0SRC_Pos) /*!< 0x00000003 */ #define HSP_TRGOCFGR_TRGO0SRC HSP_TRGOCFGR_TRGO0SRC_Msk /*!< TRGO0SRC[1:0] bits (Trigger source selection for hsp_trg_out[0] (1)) */ #define HSP_TRGOCFGR_TRGO0SRC_0 (0x1UL << HSP_TRGOCFGR_TRGO0SRC_Pos) /*!< 0x00000001 */ #define HSP_TRGOCFGR_TRGO0SRC_1 (0x2UL << HSP_TRGOCFGR_TRGO0SRC_Pos) /*!< 0x00000002 */ -/*!< TRGO1SRC configuration */ -#define HSP_TRGOCFGR_TRGO1SRC_Pos (2U) + +#define HSP_TRGOCFGR_TRGO1SRC_Pos (2UL) #define HSP_TRGOCFGR_TRGO1SRC_Msk (0x3UL << HSP_TRGOCFGR_TRGO1SRC_Pos) /*!< 0x0000000C */ #define HSP_TRGOCFGR_TRGO1SRC HSP_TRGOCFGR_TRGO1SRC_Msk /*!< TRGO1SRC[1:0] bits (Trigger source selection for hsp_trg_out[1] (1)) */ #define HSP_TRGOCFGR_TRGO1SRC_0 (0x1UL << HSP_TRGOCFGR_TRGO1SRC_Pos) /*!< 0x00000004 */ #define HSP_TRGOCFGR_TRGO1SRC_1 (0x2UL << HSP_TRGOCFGR_TRGO1SRC_Pos) /*!< 0x00000008 */ -/*!< TRGO2SRC configuration */ -#define HSP_TRGOCFGR_TRGO2SRC_Pos (4U) + +#define HSP_TRGOCFGR_TRGO2SRC_Pos (4UL) #define HSP_TRGOCFGR_TRGO2SRC_Msk (0x3UL << HSP_TRGOCFGR_TRGO2SRC_Pos) /*!< 0x00000030 */ #define HSP_TRGOCFGR_TRGO2SRC HSP_TRGOCFGR_TRGO2SRC_Msk /*!< TRGO2SRC[1:0] bits (Trigger source selection for hsp_trg_out[2] (1)) */ #define HSP_TRGOCFGR_TRGO2SRC_0 (0x1UL << HSP_TRGOCFGR_TRGO2SRC_Pos) /*!< 0x00000010 */ #define HSP_TRGOCFGR_TRGO2SRC_1 (0x2UL << HSP_TRGOCFGR_TRGO2SRC_Pos) /*!< 0x00000020 */ -/*!< TRGO3SRC configuration */ -#define HSP_TRGOCFGR_TRGO3SRC_Pos (6U) + +#define HSP_TRGOCFGR_TRGO3SRC_Pos (6UL) #define HSP_TRGOCFGR_TRGO3SRC_Msk (0x3UL << HSP_TRGOCFGR_TRGO3SRC_Pos) /*!< 0x000000C0 */ #define HSP_TRGOCFGR_TRGO3SRC HSP_TRGOCFGR_TRGO3SRC_Msk /*!< TRGO3SRC[1:0] bits (Trigger source selection for hsp_trg_out[3] ) */ #define HSP_TRGOCFGR_TRGO3SRC_0 (0x1UL << HSP_TRGOCFGR_TRGO3SRC_Pos) /*!< 0x00000040 */ #define HSP_TRGOCFGR_TRGO3SRC_1 (0x2UL << HSP_TRGOCFGR_TRGO3SRC_Pos) /*!< 0x00000080 */ /******************** Bit definition for HSP_CSEGR register ********************/ -/*!< CSEVT configuration */ -#define HSP_CSEGR_CSEVT_Pos (1U) +#define HSP_CSEGR_CSEVT_Pos (1UL) #define HSP_CSEGR_CSEVT_Msk (0x3FFFFFUL << HSP_CSEGR_CSEVT_Pos) /*!< 0x007FFFFE */ #define HSP_CSEGR_CSEVT HSP_CSEGR_CSEVT_Msk /*!< CSEVT[21:0] bits (CPU Shared Software Event ) */ #define HSP_CSEGR_CSEVT_0 (0x0001UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000002 */ @@ -12030,24 +13343,16 @@ typedef struct #define HSP_CSEGR_CSEVT_21 (0x200000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00400000 */ /******************** Bit definition for HSP_CDEGR register ********************/ -/*!< CTSKN configuration */ -#define HSP_CDEGR_CTSKN_Pos (0U) +#define HSP_CDEGR_CTSKN_Pos (0UL) #define HSP_CDEGR_CTSKN_Msk (0x3FUL << HSP_CDEGR_CTSKN_Pos) /*!< 0x0000003F */ #define HSP_CDEGR_CTSKN HSP_CDEGR_CTSKN_Msk /*!< CTSKN[5:0] bits (CPU Task number) */ -#define HSP_CDEGR_CTSKN_0 (0x01UL << HSP_CDEGR_CTSKN_Pos) /*!< 0x00000001 */ -#define HSP_CDEGR_CTSKN_1 (0x02UL << HSP_CDEGR_CTSKN_Pos) /*!< 0x00000002 */ -#define HSP_CDEGR_CTSKN_2 (0x04UL << HSP_CDEGR_CTSKN_Pos) /*!< 0x00000004 */ -#define HSP_CDEGR_CTSKN_3 (0x08UL << HSP_CDEGR_CTSKN_Pos) /*!< 0x00000008 */ -#define HSP_CDEGR_CTSKN_4 (0x10UL << HSP_CDEGR_CTSKN_Pos) /*!< 0x00000010 */ -#define HSP_CDEGR_CTSKN_5 (0x20UL << HSP_CDEGR_CTSKN_Pos) /*!< 0x00000020 */ -/*!< CDEGBSY configuration */ -#define HSP_CDEGR_CDEGBSY_Pos (31U) + +#define HSP_CDEGR_CDEGBSY_Pos (31UL) #define HSP_CDEGR_CDEGBSY_Msk (0x1UL << HSP_CDEGR_CDEGBSY_Pos) /*!< 0x80000000 */ #define HSP_CDEGR_CDEGBSY HSP_CDEGR_CDEGBSY_Msk /*!< CDEGBSY (CPU dedicated event generator busy) */ /******************** Bit definition for HSP_TRGINSELR0 register ********************/ -/*!< TRG0SEL configuration */ -#define HSP_TRGINSELR0_TRG0SEL_Pos (0U) +#define HSP_TRGINSELR0_TRG0SEL_Pos (0UL) #define HSP_TRGINSELR0_TRG0SEL_Msk (0x3FUL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x0000003F */ #define HSP_TRGINSELR0_TRG0SEL HSP_TRGINSELR0_TRG0SEL_Msk /*!< TRG0SEL[5:0] bits (Input trigger selection for TRGIN0) */ #define HSP_TRGINSELR0_TRG0SEL_0 (0x01UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000001 */ @@ -12056,8 +13361,8 @@ typedef struct #define HSP_TRGINSELR0_TRG0SEL_3 (0x08UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000008 */ #define HSP_TRGINSELR0_TRG0SEL_4 (0x10UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000010 */ #define HSP_TRGINSELR0_TRG0SEL_5 (0x20UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000020 */ -/*!< TRG1SEL configuration */ -#define HSP_TRGINSELR0_TRG1SEL_Pos (8U) + +#define HSP_TRGINSELR0_TRG1SEL_Pos (8UL) #define HSP_TRGINSELR0_TRG1SEL_Msk (0x3FUL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00003F00 */ #define HSP_TRGINSELR0_TRG1SEL HSP_TRGINSELR0_TRG1SEL_Msk /*!< TRG1SEL[5:0] bits (Input trigger selection for TRGIN1) */ #define HSP_TRGINSELR0_TRG1SEL_0 (0x01UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00000100 */ @@ -12066,8 +13371,8 @@ typedef struct #define HSP_TRGINSELR0_TRG1SEL_3 (0x08UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00000800 */ #define HSP_TRGINSELR0_TRG1SEL_4 (0x10UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00001000 */ #define HSP_TRGINSELR0_TRG1SEL_5 (0x20UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00002000 */ -/*!< TRG2SEL configuration */ -#define HSP_TRGINSELR0_TRG2SEL_Pos (16U) + +#define HSP_TRGINSELR0_TRG2SEL_Pos (16UL) #define HSP_TRGINSELR0_TRG2SEL_Msk (0x3FUL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x003F0000 */ #define HSP_TRGINSELR0_TRG2SEL HSP_TRGINSELR0_TRG2SEL_Msk /*!< TRG2SEL[5:0] bits (Input trigger selection for TRGIN2) */ #define HSP_TRGINSELR0_TRG2SEL_0 (0x01UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00010000 */ @@ -12076,8 +13381,8 @@ typedef struct #define HSP_TRGINSELR0_TRG2SEL_3 (0x08UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00080000 */ #define HSP_TRGINSELR0_TRG2SEL_4 (0x10UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00100000 */ #define HSP_TRGINSELR0_TRG2SEL_5 (0x20UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00200000 */ -/*!< TRG3SEL configuration */ -#define HSP_TRGINSELR0_TRG3SEL_Pos (24U) + +#define HSP_TRGINSELR0_TRG3SEL_Pos (24UL) #define HSP_TRGINSELR0_TRG3SEL_Msk (0x3FUL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x3F000000 */ #define HSP_TRGINSELR0_TRG3SEL HSP_TRGINSELR0_TRG3SEL_Msk /*!< TRG3SEL[5:0] bits (Input trigger selection for TRGIN3) */ #define HSP_TRGINSELR0_TRG3SEL_0 (0x01UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x01000000 */ @@ -12088,8 +13393,7 @@ typedef struct #define HSP_TRGINSELR0_TRG3SEL_5 (0x20UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x20000000 */ /******************** Bit definition for HSP_TRGINSELR1 register ********************/ -/*!< TRG4SEL configuration */ -#define HSP_TRGINSELR1_TRG4SEL_Pos (0U) +#define HSP_TRGINSELR1_TRG4SEL_Pos (0UL) #define HSP_TRGINSELR1_TRG4SEL_Msk (0x3FUL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x0000003F */ #define HSP_TRGINSELR1_TRG4SEL HSP_TRGINSELR1_TRG4SEL_Msk /*!< TRG4SEL[5:0] bits (Input trigger selection for TRGIN4) */ #define HSP_TRGINSELR1_TRG4SEL_0 (0x01UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000001 */ @@ -12098,8 +13402,8 @@ typedef struct #define HSP_TRGINSELR1_TRG4SEL_3 (0x08UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000008 */ #define HSP_TRGINSELR1_TRG4SEL_4 (0x10UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000010 */ #define HSP_TRGINSELR1_TRG4SEL_5 (0x20UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000020 */ -/*!< TRG5SEL configuration */ -#define HSP_TRGINSELR1_TRG5SEL_Pos (8U) + +#define HSP_TRGINSELR1_TRG5SEL_Pos (8UL) #define HSP_TRGINSELR1_TRG5SEL_Msk (0x3FUL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00003F00 */ #define HSP_TRGINSELR1_TRG5SEL HSP_TRGINSELR1_TRG5SEL_Msk /*!< TRG5SEL[5:0] bits (Input trigger selection for TRGIN5) */ #define HSP_TRGINSELR1_TRG5SEL_0 (0x01UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00000100 */ @@ -12108,8 +13412,8 @@ typedef struct #define HSP_TRGINSELR1_TRG5SEL_3 (0x08UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00000800 */ #define HSP_TRGINSELR1_TRG5SEL_4 (0x10UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00001000 */ #define HSP_TRGINSELR1_TRG5SEL_5 (0x20UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00002000 */ -/*!< TRG6SEL configuration */ -#define HSP_TRGINSELR1_TRG6SEL_Pos (16U) + +#define HSP_TRGINSELR1_TRG6SEL_Pos (16UL) #define HSP_TRGINSELR1_TRG6SEL_Msk (0x3FUL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x003F0000 */ #define HSP_TRGINSELR1_TRG6SEL HSP_TRGINSELR1_TRG6SEL_Msk /*!< TRG6SEL[5:0] bits (Input trigger selection for TRGIN6) */ #define HSP_TRGINSELR1_TRG6SEL_0 (0x01UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00010000 */ @@ -12118,8 +13422,8 @@ typedef struct #define HSP_TRGINSELR1_TRG6SEL_3 (0x08UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00080000 */ #define HSP_TRGINSELR1_TRG6SEL_4 (0x10UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00100000 */ #define HSP_TRGINSELR1_TRG6SEL_5 (0x20UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00200000 */ -/*!< TRG7SEL configuration */ -#define HSP_TRGINSELR1_TRG7SEL_Pos (24U) + +#define HSP_TRGINSELR1_TRG7SEL_Pos (24UL) #define HSP_TRGINSELR1_TRG7SEL_Msk (0x3FUL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x3F000000 */ #define HSP_TRGINSELR1_TRG7SEL HSP_TRGINSELR1_TRG7SEL_Msk /*!< TRG7SEL[5:0] bits (Input trigger selection for TRGIN7) */ #define HSP_TRGINSELR1_TRG7SEL_0 (0x01UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x01000000 */ @@ -12130,8 +13434,7 @@ typedef struct #define HSP_TRGINSELR1_TRG7SEL_5 (0x20UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x20000000 */ /******************** Bit definition for HSP_TRGINSELR2 register ********************/ -/*!< TRG8SEL configuration */ -#define HSP_TRGINSELR2_TRG8SEL_Pos (0U) +#define HSP_TRGINSELR2_TRG8SEL_Pos (0UL) #define HSP_TRGINSELR2_TRG8SEL_Msk (0x3FUL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x0000003F */ #define HSP_TRGINSELR2_TRG8SEL HSP_TRGINSELR2_TRG8SEL_Msk /*!< TRG8SEL[5:0] bits (Input trigger selection for TRGIN8) */ #define HSP_TRGINSELR2_TRG8SEL_0 (0x01UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000001 */ @@ -12140,8 +13443,8 @@ typedef struct #define HSP_TRGINSELR2_TRG8SEL_3 (0x08UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000008 */ #define HSP_TRGINSELR2_TRG8SEL_4 (0x10UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000010 */ #define HSP_TRGINSELR2_TRG8SEL_5 (0x20UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000020 */ -/*!< TRG9SEL configuration */ -#define HSP_TRGINSELR2_TRG9SEL_Pos (8U) + +#define HSP_TRGINSELR2_TRG9SEL_Pos (8UL) #define HSP_TRGINSELR2_TRG9SEL_Msk (0x3FUL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00003F00 */ #define HSP_TRGINSELR2_TRG9SEL HSP_TRGINSELR2_TRG9SEL_Msk /*!< TRG9SEL[5:0] bits (Input trigger selection for TRGIN9) */ #define HSP_TRGINSELR2_TRG9SEL_0 (0x01UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00000100 */ @@ -12151,879 +13454,229 @@ typedef struct #define HSP_TRGINSELR2_TRG9SEL_4 (0x10UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00001000 */ #define HSP_TRGINSELR2_TRG9SEL_5 (0x20UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00002000 */ -/******************** Bit definition for HSP_BKO0CFGR register ********************/ -/*!< ACCEREN configuration */ -#define HSP_BKO0CFGR_ACCEREN_Pos (0U) -#define HSP_BKO0CFGR_ACCEREN_Msk (0x1UL << HSP_BKO0CFGR_ACCEREN_Pos) /*!< 0x00000001 */ -#define HSP_BKO0CFGR_ACCEREN HSP_BKO0CFGR_ACCEREN_Msk /*!< ACCEREN (Access error break enable for ACCERRF (1)) */ -/*!< FPUEREN configuration */ -#define HSP_BKO0CFGR_FPUEREN_Pos (1U) -#define HSP_BKO0CFGR_FPUEREN_Msk (0x1UL << HSP_BKO0CFGR_FPUEREN_Pos) /*!< 0x00000002 */ -#define HSP_BKO0CFGR_FPUEREN HSP_BKO0CFGR_FPUEREN_Msk /*!< FPUEREN (FPU error break enable for FPUERRF (1)) */ -/*!< OPCEREN configuration */ -#define HSP_BKO0CFGR_OPCEREN_Pos (2U) -#define HSP_BKO0CFGR_OPCEREN_Msk (0x1UL << HSP_BKO0CFGR_OPCEREN_Pos) /*!< 0x00000004 */ -#define HSP_BKO0CFGR_OPCEREN HSP_BKO0CFGR_OPCEREN_Msk /*!< OPCEREN (Opcode error break enable for OPCOERRF ) */ -/*!< PFCT28EN configuration */ -#define HSP_BKO0CFGR_PFCT28EN_Pos (4U) -#define HSP_BKO0CFGR_PFCT28EN_Msk (0x1UL << HSP_BKO0CFGR_PFCT28EN_Pos) /*!< 0x00000010 */ -#define HSP_BKO0CFGR_PFCT28EN HSP_BKO0CFGR_PFCT28EN_Msk /*!< PFCT28EN (Processing function flag break enable for PFCTF[28] (1)) */ -/*!< PFCT29EN configuration */ -#define HSP_BKO0CFGR_PFCT29EN_Pos (5U) -#define HSP_BKO0CFGR_PFCT29EN_Msk (0x1UL << HSP_BKO0CFGR_PFCT29EN_Pos) /*!< 0x00000020 */ -#define HSP_BKO0CFGR_PFCT29EN HSP_BKO0CFGR_PFCT29EN_Msk /*!< PFCT29EN (Processing function flag break enable for PFCTF[29] (1)) */ -/*!< PFCT30EN configuration */ -#define HSP_BKO0CFGR_PFCT30EN_Pos (6U) -#define HSP_BKO0CFGR_PFCT30EN_Msk (0x1UL << HSP_BKO0CFGR_PFCT30EN_Pos) /*!< 0x00000040 */ -#define HSP_BKO0CFGR_PFCT30EN HSP_BKO0CFGR_PFCT30EN_Msk /*!< PFCT30EN (Processing function flag break enable for PFCTF[30] (1)) */ -/*!< PFCT31EN configuration */ -#define HSP_BKO0CFGR_PFCT31EN_Pos (7U) -#define HSP_BKO0CFGR_PFCT31EN_Msk (0x1UL << HSP_BKO0CFGR_PFCT31EN_Pos) /*!< 0x00000080 */ -#define HSP_BKO0CFGR_PFCT31EN HSP_BKO0CFGR_PFCT31EN_Msk /*!< PFCT31EN (Processing function flag break enable for PFCTF[31] (1)) */ -/*!< FWEREN configuration */ -#define HSP_BKO0CFGR_FWEREN_Pos (12U) -#define HSP_BKO0CFGR_FWEREN_Msk (0x1UL << HSP_BKO0CFGR_FWEREN_Pos) /*!< 0x00001000 */ -#define HSP_BKO0CFGR_FWEREN HSP_BKO0CFGR_FWEREN_Msk /*!< FWEREN (Firmware error break enable for FWERRF (1)) */ -/*!< HDEGOVEN configuration */ -#define HSP_BKO0CFGR_HDEGOVEN_Pos (13U) -#define HSP_BKO0CFGR_HDEGOVEN_Msk (0x1UL << HSP_BKO0CFGR_HDEGOVEN_Pos) /*!< 0x00002000 */ -#define HSP_BKO0CFGR_HDEGOVEN HSP_BKO0CFGR_HDEGOVEN_Msk /*!< HDEGOVEN (HSP dedicated event generator overrun break enable for HDEGOVRF (1)) */ - -/******************** Bit definition for HSP_BKO1CFGR register ********************/ -/*!< ACCEREN configuration */ -#define HSP_BKO1CFGR_ACCEREN_Pos (0U) -#define HSP_BKO1CFGR_ACCEREN_Msk (0x1UL << HSP_BKO1CFGR_ACCEREN_Pos) /*!< 0x00000001 */ -#define HSP_BKO1CFGR_ACCEREN HSP_BKO1CFGR_ACCEREN_Msk /*!< ACCEREN (Access error break enable for ACCERRF (1)) */ -/*!< FPUEREN configuration */ -#define HSP_BKO1CFGR_FPUEREN_Pos (1U) -#define HSP_BKO1CFGR_FPUEREN_Msk (0x1UL << HSP_BKO1CFGR_FPUEREN_Pos) /*!< 0x00000002 */ -#define HSP_BKO1CFGR_FPUEREN HSP_BKO1CFGR_FPUEREN_Msk /*!< FPUEREN (FPU error break enable for FPUERRF (1)) */ -/*!< OPCEREN configuration */ -#define HSP_BKO1CFGR_OPCEREN_Pos (2U) -#define HSP_BKO1CFGR_OPCEREN_Msk (0x1UL << HSP_BKO1CFGR_OPCEREN_Pos) /*!< 0x00000004 */ -#define HSP_BKO1CFGR_OPCEREN HSP_BKO1CFGR_OPCEREN_Msk /*!< OPCEREN (Opcode error break enable for OPCOERRF ) */ -/*!< PFCT28EN configuration */ -#define HSP_BKO1CFGR_PFCT28EN_Pos (4U) -#define HSP_BKO1CFGR_PFCT28EN_Msk (0x1UL << HSP_BKO1CFGR_PFCT28EN_Pos) /*!< 0x00000010 */ -#define HSP_BKO1CFGR_PFCT28EN HSP_BKO1CFGR_PFCT28EN_Msk /*!< PFCT28EN (Processing function flag break enable for PFCTF[28] (1)) */ -/*!< PFCT29EN configuration */ -#define HSP_BKO1CFGR_PFCT29EN_Pos (5U) -#define HSP_BKO1CFGR_PFCT29EN_Msk (0x1UL << HSP_BKO1CFGR_PFCT29EN_Pos) /*!< 0x00000020 */ -#define HSP_BKO1CFGR_PFCT29EN HSP_BKO1CFGR_PFCT29EN_Msk /*!< PFCT29EN (Processing function flag break enable for PFCTF[29] (1)) */ -/*!< PFCT30EN configuration */ -#define HSP_BKO1CFGR_PFCT30EN_Pos (6U) -#define HSP_BKO1CFGR_PFCT30EN_Msk (0x1UL << HSP_BKO1CFGR_PFCT30EN_Pos) /*!< 0x00000040 */ -#define HSP_BKO1CFGR_PFCT30EN HSP_BKO1CFGR_PFCT30EN_Msk /*!< PFCT30EN (Processing function flag break enable for PFCTF[30] (1)) */ -/*!< PFCT31EN configuration */ -#define HSP_BKO1CFGR_PFCT31EN_Pos (7U) -#define HSP_BKO1CFGR_PFCT31EN_Msk (0x1UL << HSP_BKO1CFGR_PFCT31EN_Pos) /*!< 0x00000080 */ -#define HSP_BKO1CFGR_PFCT31EN HSP_BKO1CFGR_PFCT31EN_Msk /*!< PFCT31EN (Processing function flag break enable for PFCTF[31] (1)) */ -/*!< FWEREN configuration */ -#define HSP_BKO1CFGR_FWEREN_Pos (12U) -#define HSP_BKO1CFGR_FWEREN_Msk (0x1UL << HSP_BKO1CFGR_FWEREN_Pos) /*!< 0x00001000 */ -#define HSP_BKO1CFGR_FWEREN HSP_BKO1CFGR_FWEREN_Msk /*!< FWEREN (Firmware error break enable for FWERRF (1)) */ -/*!< HDEGOVEN configuration */ -#define HSP_BKO1CFGR_HDEGOVEN_Pos (13U) -#define HSP_BKO1CFGR_HDEGOVEN_Msk (0x1UL << HSP_BKO1CFGR_HDEGOVEN_Pos) /*!< 0x00002000 */ -#define HSP_BKO1CFGR_HDEGOVEN HSP_BKO1CFGR_HDEGOVEN_Msk /*!< HDEGOVEN (HSP dedicated event generator overrun break enable for HDEGOVRF (1)) */ - -/******************** Bit definition for HSP_BKO2CFGR register ********************/ -/*!< ACCEREN configuration */ -#define HSP_BKO2CFGR_ACCEREN_Pos (0U) -#define HSP_BKO2CFGR_ACCEREN_Msk (0x1UL << HSP_BKO2CFGR_ACCEREN_Pos) /*!< 0x00000001 */ -#define HSP_BKO2CFGR_ACCEREN HSP_BKO2CFGR_ACCEREN_Msk /*!< ACCEREN (Access error break enable for ACCERRF (1)) */ -/*!< FPUEREN configuration */ -#define HSP_BKO2CFGR_FPUEREN_Pos (1U) -#define HSP_BKO2CFGR_FPUEREN_Msk (0x1UL << HSP_BKO2CFGR_FPUEREN_Pos) /*!< 0x00000002 */ -#define HSP_BKO2CFGR_FPUEREN HSP_BKO2CFGR_FPUEREN_Msk /*!< FPUEREN (FPU error break enable for FPUERRF (1)) */ -/*!< OPCEREN configuration */ -#define HSP_BKO2CFGR_OPCEREN_Pos (2U) -#define HSP_BKO2CFGR_OPCEREN_Msk (0x1UL << HSP_BKO2CFGR_OPCEREN_Pos) /*!< 0x00000004 */ -#define HSP_BKO2CFGR_OPCEREN HSP_BKO2CFGR_OPCEREN_Msk /*!< OPCEREN (Opcode error break enable for OPCOERRF ) */ -/*!< PFCT28EN configuration */ -#define HSP_BKO2CFGR_PFCT28EN_Pos (4U) -#define HSP_BKO2CFGR_PFCT28EN_Msk (0x1UL << HSP_BKO2CFGR_PFCT28EN_Pos) /*!< 0x00000010 */ -#define HSP_BKO2CFGR_PFCT28EN HSP_BKO2CFGR_PFCT28EN_Msk /*!< PFCT28EN (Processing function flag break enable for PFCTF[28] (1)) */ -/*!< PFCT29EN configuration */ -#define HSP_BKO2CFGR_PFCT29EN_Pos (5U) -#define HSP_BKO2CFGR_PFCT29EN_Msk (0x1UL << HSP_BKO2CFGR_PFCT29EN_Pos) /*!< 0x00000020 */ -#define HSP_BKO2CFGR_PFCT29EN HSP_BKO2CFGR_PFCT29EN_Msk /*!< PFCT29EN (Processing function flag break enable for PFCTF[29] (1)) */ -/*!< PFCT30EN configuration */ -#define HSP_BKO2CFGR_PFCT30EN_Pos (6U) -#define HSP_BKO2CFGR_PFCT30EN_Msk (0x1UL << HSP_BKO2CFGR_PFCT30EN_Pos) /*!< 0x00000040 */ -#define HSP_BKO2CFGR_PFCT30EN HSP_BKO2CFGR_PFCT30EN_Msk /*!< PFCT30EN (Processing function flag break enable for PFCTF[30] (1)) */ -/*!< PFCT31EN configuration */ -#define HSP_BKO2CFGR_PFCT31EN_Pos (7U) -#define HSP_BKO2CFGR_PFCT31EN_Msk (0x1UL << HSP_BKO2CFGR_PFCT31EN_Pos) /*!< 0x00000080 */ -#define HSP_BKO2CFGR_PFCT31EN HSP_BKO2CFGR_PFCT31EN_Msk /*!< PFCT31EN (Processing function flag break enable for PFCTF[31] (1)) */ -/*!< FWEREN configuration */ -#define HSP_BKO2CFGR_FWEREN_Pos (12U) -#define HSP_BKO2CFGR_FWEREN_Msk (0x1UL << HSP_BKO2CFGR_FWEREN_Pos) /*!< 0x00001000 */ -#define HSP_BKO2CFGR_FWEREN HSP_BKO2CFGR_FWEREN_Msk /*!< FWEREN (Firmware error break enable for FWERRF (1)) */ -/*!< HDEGOVEN configuration */ -#define HSP_BKO2CFGR_HDEGOVEN_Pos (13U) -#define HSP_BKO2CFGR_HDEGOVEN_Msk (0x1UL << HSP_BKO2CFGR_HDEGOVEN_Pos) /*!< 0x00002000 */ -#define HSP_BKO2CFGR_HDEGOVEN HSP_BKO2CFGR_HDEGOVEN_Msk /*!< HDEGOVEN (HSP dedicated event generator overrun break enable for HDEGOVRF (1)) */ - -/******************** Bit definition for HSP_BKO3CFGR register ********************/ -/*!< ACCEREN configuration */ -#define HSP_BKO3CFGR_ACCEREN_Pos (0U) -#define HSP_BKO3CFGR_ACCEREN_Msk (0x1UL << HSP_BKO3CFGR_ACCEREN_Pos) /*!< 0x00000001 */ -#define HSP_BKO3CFGR_ACCEREN HSP_BKO3CFGR_ACCEREN_Msk /*!< ACCEREN (Access error break enable for ACCERRF (1)) */ -/*!< FPUEREN configuration */ -#define HSP_BKO3CFGR_FPUEREN_Pos (1U) -#define HSP_BKO3CFGR_FPUEREN_Msk (0x1UL << HSP_BKO3CFGR_FPUEREN_Pos) /*!< 0x00000002 */ -#define HSP_BKO3CFGR_FPUEREN HSP_BKO3CFGR_FPUEREN_Msk /*!< FPUEREN (FPU error break enable for FPUERRF (1)) */ -/*!< OPCEREN configuration */ -#define HSP_BKO3CFGR_OPCEREN_Pos (2U) -#define HSP_BKO3CFGR_OPCEREN_Msk (0x1UL << HSP_BKO3CFGR_OPCEREN_Pos) /*!< 0x00000004 */ -#define HSP_BKO3CFGR_OPCEREN HSP_BKO3CFGR_OPCEREN_Msk /*!< OPCEREN (Opcode error break enable for OPCOERRF ) */ -/*!< PFCT28EN configuration */ -#define HSP_BKO3CFGR_PFCT28EN_Pos (4U) -#define HSP_BKO3CFGR_PFCT28EN_Msk (0x1UL << HSP_BKO3CFGR_PFCT28EN_Pos) /*!< 0x00000010 */ -#define HSP_BKO3CFGR_PFCT28EN HSP_BKO3CFGR_PFCT28EN_Msk /*!< PFCT28EN (Processing function flag break enable for PFCTF[28] (1)) */ -/*!< PFCT29EN configuration */ -#define HSP_BKO3CFGR_PFCT29EN_Pos (5U) -#define HSP_BKO3CFGR_PFCT29EN_Msk (0x1UL << HSP_BKO3CFGR_PFCT29EN_Pos) /*!< 0x00000020 */ -#define HSP_BKO3CFGR_PFCT29EN HSP_BKO3CFGR_PFCT29EN_Msk /*!< PFCT29EN (Processing function flag break enable for PFCTF[29] (1)) */ -/*!< PFCT30EN configuration */ -#define HSP_BKO3CFGR_PFCT30EN_Pos (6U) -#define HSP_BKO3CFGR_PFCT30EN_Msk (0x1UL << HSP_BKO3CFGR_PFCT30EN_Pos) /*!< 0x00000040 */ -#define HSP_BKO3CFGR_PFCT30EN HSP_BKO3CFGR_PFCT30EN_Msk /*!< PFCT30EN (Processing function flag break enable for PFCTF[30] (1)) */ -/*!< PFCT31EN configuration */ -#define HSP_BKO3CFGR_PFCT31EN_Pos (7U) -#define HSP_BKO3CFGR_PFCT31EN_Msk (0x1UL << HSP_BKO3CFGR_PFCT31EN_Pos) /*!< 0x00000080 */ -#define HSP_BKO3CFGR_PFCT31EN HSP_BKO3CFGR_PFCT31EN_Msk /*!< PFCT31EN (Processing function flag break enable for PFCTF[31] (1)) */ -/*!< FWEREN configuration */ -#define HSP_BKO3CFGR_FWEREN_Pos (12U) -#define HSP_BKO3CFGR_FWEREN_Msk (0x1UL << HSP_BKO3CFGR_FWEREN_Pos) /*!< 0x00001000 */ -#define HSP_BKO3CFGR_FWEREN HSP_BKO3CFGR_FWEREN_Msk /*!< FWEREN (Firmware error break enable for FWERRF (1)) */ -/*!< HDEGOVEN configuration */ -#define HSP_BKO3CFGR_HDEGOVEN_Pos (13U) -#define HSP_BKO3CFGR_HDEGOVEN_Msk (0x1UL << HSP_BKO3CFGR_HDEGOVEN_Pos) /*!< 0x00002000 */ -#define HSP_BKO3CFGR_HDEGOVEN HSP_BKO3CFGR_HDEGOVEN_Msk /*!< HDEGOVEN (HSP dedicated event generator overrun break enable for HDEGOVRF (1)) */ +/******************** Bit definition for HSP_BKOxCFGR register ********************/ +#define HSP_BKOCFGR_ACCEREN_Pos (0U) +#define HSP_BKOCFGR_ACCEREN_Msk (0x1UL << HSP_BKOCFGR_ACCEREN_Pos) /*!< 0x00000001 */ +#define HSP_BKOCFGR_ACCEREN HSP_BKOCFGR_ACCEREN_Msk /*!< ACCEREN (Access error break enable for ACCERRF (1)) */ + +#define HSP_BKOCFGR_FPUEREN_Pos (1U) +#define HSP_BKOCFGR_FPUEREN_Msk (0x1UL << HSP_BKOCFGR_FPUEREN_Pos) /*!< 0x00000002 */ +#define HSP_BKOCFGR_FPUEREN HSP_BKOCFGR_FPUEREN_Msk /*!< FPUEREN (FPU error break enable for FPUERRF (1)) */ + +#define HSP_BKOCFGR_OPCEREN_Pos (2U) +#define HSP_BKOCFGR_OPCEREN_Msk (0x1UL << HSP_BKOCFGR_OPCEREN_Pos) /*!< 0x00000004 */ +#define HSP_BKOCFGR_OPCEREN HSP_BKOCFGR_OPCEREN_Msk /*!< OPCEREN (Opcode error break enable for OPCOERRF ) */ + +#define HSP_BKOCFGR_PFCT28EN_Pos (4U) +#define HSP_BKOCFGR_PFCT28EN_Msk (0x1UL << HSP_BKOCFGR_PFCT28EN_Pos) /*!< 0x00000010 */ +#define HSP_BKOCFGR_PFCT28EN HSP_BKOCFGR_PFCT28EN_Msk /*!< PFCT28EN (Processing function flag break enable for PFCTF[28] (1)) */ + +#define HSP_BKOCFGR_PFCT29EN_Pos (5U) +#define HSP_BKOCFGR_PFCT29EN_Msk (0x1UL << HSP_BKOCFGR_PFCT29EN_Pos) /*!< 0x00000020 */ +#define HSP_BKOCFGR_PFCT29EN HSP_BKOCFGR_PFCT29EN_Msk /*!< PFCT29EN (Processing function flag break enable for PFCTF[29] (1)) */ + +#define HSP_BKOCFGR_PFCT30EN_Pos (6U) +#define HSP_BKOCFGR_PFCT30EN_Msk (0x1UL << HSP_BKOCFGR_PFCT30EN_Pos) /*!< 0x00000040 */ +#define HSP_BKOCFGR_PFCT30EN HSP_BKOCFGR_PFCT30EN_Msk /*!< PFCT30EN (Processing function flag break enable for PFCTF[30] (1)) */ + +#define HSP_BKOCFGR_PFCT31EN_Pos (7U) +#define HSP_BKOCFGR_PFCT31EN_Msk (0x1UL << HSP_BKOCFGR_PFCT31EN_Pos) /*!< 0x00000080 */ +#define HSP_BKOCFGR_PFCT31EN HSP_BKOCFGR_PFCT31EN_Msk /*!< PFCT31EN (Processing function flag break enable for PFCTF[31] (1)) */ + +#define HSP_BKOCFGR_FWEREN_Pos (12U) +#define HSP_BKOCFGR_FWEREN_Msk (0x1UL << HSP_BKOCFGR_FWEREN_Pos) /*!< 0x00001000 */ +#define HSP_BKOCFGR_FWEREN HSP_BKOCFGR_FWEREN_Msk /*!< FWEREN (Firmware error break enable for FWERRF (1)) */ + +#define HSP_BKOCFGR_HDEGOVEN_Pos (13U) +#define HSP_BKOCFGR_HDEGOVEN_Msk (0x1UL << HSP_BKOCFGR_HDEGOVEN_Pos) /*!< 0x00002000 */ +#define HSP_BKOCFGR_HDEGOVEN HSP_BKOCFGR_HDEGOVEN_Msk /*!< HDEGOVEN (HSP dedicated event generator overrun break enable for HDEGOVRF (1)) */ /******************** Bit definition for HSP_BKICFGR register ********************/ -/*!< ACCEREN configuration */ -#define HSP_BKICFGR_ACCEREN_Pos (0U) +#define HSP_BKICFGR_ACCEREN_Pos (0UL) #define HSP_BKICFGR_ACCEREN_Msk (0x1UL << HSP_BKICFGR_ACCEREN_Pos) /*!< 0x00000001 */ #define HSP_BKICFGR_ACCEREN HSP_BKICFGR_ACCEREN_Msk /*!< ACCEREN (Access error break enable for ACCERRF (1)) */ -/*!< FPUEREN configuration */ -#define HSP_BKICFGR_FPUEREN_Pos (1U) + +#define HSP_BKICFGR_FPUEREN_Pos (1UL) #define HSP_BKICFGR_FPUEREN_Msk (0x1UL << HSP_BKICFGR_FPUEREN_Pos) /*!< 0x00000002 */ #define HSP_BKICFGR_FPUEREN HSP_BKICFGR_FPUEREN_Msk /*!< FPUEREN (FPU error break enable for FPUERRF (1)) */ -/*!< OPCEREN configuration */ -#define HSP_BKICFGR_OPCEREN_Pos (2U) + +#define HSP_BKICFGR_OPCEREN_Pos (2UL) #define HSP_BKICFGR_OPCEREN_Msk (0x1UL << HSP_BKICFGR_OPCEREN_Pos) /*!< 0x00000004 */ #define HSP_BKICFGR_OPCEREN HSP_BKICFGR_OPCEREN_Msk /*!< OPCEREN (Opcode error break enable for OPCOERRF ) */ -/*!< BKIEN configuration */ -#define HSP_BKICFGR_BKIEN_Pos (3U) -#define HSP_BKICFGR_BKIEN_Msk (0x1UL << HSP_BKICFGR_BKIEN_Pos) /*!< 0x00000008 */ -#define HSP_BKICFGR_BKIEN HSP_BKICFGR_BKIEN_Msk /*!< BKIEN (Break enable for hsp_break_in signal (1)) */ -/*!< PFCT28EN configuration */ -#define HSP_BKICFGR_PFCT28EN_Pos (4U) + +#define HSP_BKICFGR_PFCT28EN_Pos (4UL) #define HSP_BKICFGR_PFCT28EN_Msk (0x1UL << HSP_BKICFGR_PFCT28EN_Pos) /*!< 0x00000010 */ #define HSP_BKICFGR_PFCT28EN HSP_BKICFGR_PFCT28EN_Msk /*!< PFCT28EN (Processing function flag break enable for PFCTF[28] (1)) */ -/*!< PFCT29EN configuration */ -#define HSP_BKICFGR_PFCT29EN_Pos (5U) + +#define HSP_BKICFGR_PFCT29EN_Pos (5UL) #define HSP_BKICFGR_PFCT29EN_Msk (0x1UL << HSP_BKICFGR_PFCT29EN_Pos) /*!< 0x00000020 */ #define HSP_BKICFGR_PFCT29EN HSP_BKICFGR_PFCT29EN_Msk /*!< PFCT29EN (Processing function flag break enable for PFCTF[29] (1)) */ -/*!< PFCT30EN configuration */ -#define HSP_BKICFGR_PFCT30EN_Pos (6U) + +#define HSP_BKICFGR_PFCT30EN_Pos (6UL) #define HSP_BKICFGR_PFCT30EN_Msk (0x1UL << HSP_BKICFGR_PFCT30EN_Pos) /*!< 0x00000040 */ #define HSP_BKICFGR_PFCT30EN HSP_BKICFGR_PFCT30EN_Msk /*!< PFCT30EN (Processing function flag break enable for PFCTF[30] (1)) */ -/*!< PFCT31EN configuration */ -#define HSP_BKICFGR_PFCT31EN_Pos (7U) + +#define HSP_BKICFGR_PFCT31EN_Pos (7UL) #define HSP_BKICFGR_PFCT31EN_Msk (0x1UL << HSP_BKICFGR_PFCT31EN_Pos) /*!< 0x00000080 */ #define HSP_BKICFGR_PFCT31EN HSP_BKICFGR_PFCT31EN_Msk /*!< PFCT31EN (Processing function flag break enable for PFCTF[31] (1)) */ -/*!< FWEREN configuration */ -#define HSP_BKICFGR_FWEREN_Pos (12U) + +#define HSP_BKICFGR_FWEREN_Pos (12UL) #define HSP_BKICFGR_FWEREN_Msk (0x1UL << HSP_BKICFGR_FWEREN_Pos) /*!< 0x00001000 */ #define HSP_BKICFGR_FWEREN HSP_BKICFGR_FWEREN_Msk /*!< FWEREN (Firmware error break enable for FWERRF (1)) */ -/*!< HDEGOVEN configuration */ -#define HSP_BKICFGR_HDEGOVEN_Pos (13U) + +#define HSP_BKICFGR_HDEGOVEN_Pos (13UL) #define HSP_BKICFGR_HDEGOVEN_Msk (0x1UL << HSP_BKICFGR_HDEGOVEN_Pos) /*!< 0x00002000 */ #define HSP_BKICFGR_HDEGOVEN HSP_BKICFGR_HDEGOVEN_Msk /*!< HDEGOVEN (HSP dedicated event generator overrun break enable for HDEGOVRF (1)) */ -/*!< FSATEN configuration */ -#define HSP_BKICFGR_FSATEN_Pos (14U) + +#define HSP_BKICFGR_FSATEN_Pos (14UL) #define HSP_BKICFGR_FSATEN_Msk (0x1UL << HSP_BKICFGR_FSATEN_Pos) /*!< 0x00004000 */ #define HSP_BKICFGR_FSATEN HSP_BKICFGR_FSATEN_Msk /*!< FSATEN (FPU saturation break enable for FPUSATF (1)) */ -/*!< SSEN configuration */ -#define HSP_BKICFGR_SSEN_Pos (17U) + +#define HSP_BKICFGR_SSEN_Pos (17UL) #define HSP_BKICFGR_SSEN_Msk (0x1UL << HSP_BKICFGR_SSEN_Pos) /*!< 0x00020000 */ #define HSP_BKICFGR_SSEN HSP_BKICFGR_SSEN_Msk /*!< SSEN (Single step enable (1)) */ -/*!< BKIP configuration */ -#define HSP_BKICFGR_BKIP_Pos (18U) -#define HSP_BKICFGR_BKIP_Msk (0x1UL << HSP_BKICFGR_BKIP_Pos) /*!< 0x00040000 */ -#define HSP_BKICFGR_BKIP HSP_BKICFGR_BKIP_Msk /*!< BKIP (Break enable input polarity (1)) */ /******************** Bit definition for HSP_FWERR register ********************/ -/*!< FWERRN configuration */ -#define HSP_FWERR_FWERRN_Pos (0U) +#define HSP_FWERR_FWERRN_Pos (0UL) #define HSP_FWERR_FWERRN_Msk (0x3FFUL << HSP_FWERR_FWERRN_Pos) /*!< 0x000003FF */ #define HSP_FWERR_FWERRN HSP_FWERR_FWERRN_Msk /*!< FWERRN[9:0] bits (Firmware error number) */ -#define HSP_FWERR_FWERRN_0 (0x001UL << HSP_FWERR_FWERRN_Pos) /*!< 0x00000001 */ -#define HSP_FWERR_FWERRN_1 (0x002UL << HSP_FWERR_FWERRN_Pos) /*!< 0x00000002 */ -#define HSP_FWERR_FWERRN_2 (0x004UL << HSP_FWERR_FWERRN_Pos) /*!< 0x00000004 */ -#define HSP_FWERR_FWERRN_3 (0x008UL << HSP_FWERR_FWERRN_Pos) /*!< 0x00000008 */ -#define HSP_FWERR_FWERRN_4 (0x010UL << HSP_FWERR_FWERRN_Pos) /*!< 0x00000010 */ -#define HSP_FWERR_FWERRN_5 (0x020UL << HSP_FWERR_FWERRN_Pos) /*!< 0x00000020 */ -#define HSP_FWERR_FWERRN_6 (0x040UL << HSP_FWERR_FWERRN_Pos) /*!< 0x00000040 */ -#define HSP_FWERR_FWERRN_7 (0x080UL << HSP_FWERR_FWERRN_Pos) /*!< 0x00000080 */ -#define HSP_FWERR_FWERRN_8 (0x100UL << HSP_FWERR_FWERRN_Pos) /*!< 0x00000100 */ -#define HSP_FWERR_FWERRN_9 (0x200UL << HSP_FWERR_FWERRN_Pos) /*!< 0x00000200 */ /******************** Bit definition for HSP_PARAMR0 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR0_PARAM_Pos (0U) +#define HSP_PARAMR0_PARAM_Pos (0UL) #define HSP_PARAMR0_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR0_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR0_PARAM HSP_PARAMR0_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR0_PARAM_0 (0x00001UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR0_PARAM_1 (0x00002UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR0_PARAM_2 (0x00004UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR0_PARAM_3 (0x00008UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR0_PARAM_4 (0x00010UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR0_PARAM_5 (0x00020UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR0_PARAM_6 (0x00040UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR0_PARAM_7 (0x00080UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR0_PARAM_8 (0x00100UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR0_PARAM_9 (0x00200UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR0_PARAM_10 (0x00400UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR0_PARAM_11 (0x00800UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR0_PARAM_12 (0x01000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR0_PARAM_13 (0x02000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR0_PARAM_14 (0x04000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR0_PARAM_15 (0x08000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR0_PARAM_16 (0x10000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR0_PARAM_17 (0x20000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR0_PARAM_18 (0x40000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR0_PARAM_19 (0x80000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR0_PARAM_20 (0x100000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR0_PARAM_21 (0x200000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR0_PARAM_22 (0x400000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR0_PARAM_23 (0x800000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR0_PARAM_24 (0x1000000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR0_PARAM_25 (0x2000000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR0_PARAM_26 (0x4000000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR0_PARAM_27 (0x8000000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR0_PARAM_28 (0x10000000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR0_PARAM_29 (0x20000000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR0_PARAM_30 (0x40000000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR0_PARAM_31 (0x80000000UL << HSP_PARAMR0_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR1 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR1_PARAM_Pos (0U) +#define HSP_PARAMR1_PARAM_Pos (0UL) #define HSP_PARAMR1_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR1_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR1_PARAM HSP_PARAMR1_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR1_PARAM_0 (0x00001UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR1_PARAM_1 (0x00002UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR1_PARAM_2 (0x00004UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR1_PARAM_3 (0x00008UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR1_PARAM_4 (0x00010UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR1_PARAM_5 (0x00020UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR1_PARAM_6 (0x00040UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR1_PARAM_7 (0x00080UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR1_PARAM_8 (0x00100UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR1_PARAM_9 (0x00200UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR1_PARAM_10 (0x00400UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR1_PARAM_11 (0x00800UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR1_PARAM_12 (0x01000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR1_PARAM_13 (0x02000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR1_PARAM_14 (0x04000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR1_PARAM_15 (0x08000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR1_PARAM_16 (0x10000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR1_PARAM_17 (0x20000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR1_PARAM_18 (0x40000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR1_PARAM_19 (0x80000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR1_PARAM_20 (0x100000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR1_PARAM_21 (0x200000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR1_PARAM_22 (0x400000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR1_PARAM_23 (0x800000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR1_PARAM_24 (0x1000000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR1_PARAM_25 (0x2000000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR1_PARAM_26 (0x4000000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR1_PARAM_27 (0x8000000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR1_PARAM_28 (0x10000000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR1_PARAM_29 (0x20000000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR1_PARAM_30 (0x40000000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR1_PARAM_31 (0x80000000UL << HSP_PARAMR1_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR2 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR2_PARAM_Pos (0U) +#define HSP_PARAMR2_PARAM_Pos (0UL) #define HSP_PARAMR2_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR2_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR2_PARAM HSP_PARAMR2_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR2_PARAM_0 (0x00001UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR2_PARAM_1 (0x00002UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR2_PARAM_2 (0x00004UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR2_PARAM_3 (0x00008UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR2_PARAM_4 (0x00010UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR2_PARAM_5 (0x00020UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR2_PARAM_6 (0x00040UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR2_PARAM_7 (0x00080UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR2_PARAM_8 (0x00100UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR2_PARAM_9 (0x00200UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR2_PARAM_10 (0x00400UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR2_PARAM_11 (0x00800UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR2_PARAM_12 (0x01000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR2_PARAM_13 (0x02000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR2_PARAM_14 (0x04000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR2_PARAM_15 (0x08000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR2_PARAM_16 (0x10000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR2_PARAM_17 (0x20000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR2_PARAM_18 (0x40000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR2_PARAM_19 (0x80000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR2_PARAM_20 (0x100000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR2_PARAM_21 (0x200000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR2_PARAM_22 (0x400000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR2_PARAM_23 (0x800000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR2_PARAM_24 (0x1000000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR2_PARAM_25 (0x2000000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR2_PARAM_26 (0x4000000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR2_PARAM_27 (0x8000000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR2_PARAM_28 (0x10000000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR2_PARAM_29 (0x20000000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR2_PARAM_30 (0x40000000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR2_PARAM_31 (0x80000000UL << HSP_PARAMR2_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR3 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR3_PARAM_Pos (0U) +#define HSP_PARAMR3_PARAM_Pos (0UL) #define HSP_PARAMR3_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR3_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR3_PARAM HSP_PARAMR3_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR3_PARAM_0 (0x00001UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR3_PARAM_1 (0x00002UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR3_PARAM_2 (0x00004UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR3_PARAM_3 (0x00008UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR3_PARAM_4 (0x00010UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR3_PARAM_5 (0x00020UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR3_PARAM_6 (0x00040UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR3_PARAM_7 (0x00080UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR3_PARAM_8 (0x00100UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR3_PARAM_9 (0x00200UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR3_PARAM_10 (0x00400UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR3_PARAM_11 (0x00800UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR3_PARAM_12 (0x01000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR3_PARAM_13 (0x02000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR3_PARAM_14 (0x04000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR3_PARAM_15 (0x08000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR3_PARAM_16 (0x10000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR3_PARAM_17 (0x20000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR3_PARAM_18 (0x40000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR3_PARAM_19 (0x80000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR3_PARAM_20 (0x100000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR3_PARAM_21 (0x200000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR3_PARAM_22 (0x400000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR3_PARAM_23 (0x800000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR3_PARAM_24 (0x1000000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR3_PARAM_25 (0x2000000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR3_PARAM_26 (0x4000000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR3_PARAM_27 (0x8000000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR3_PARAM_28 (0x10000000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR3_PARAM_29 (0x20000000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR3_PARAM_30 (0x40000000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR3_PARAM_31 (0x80000000UL << HSP_PARAMR3_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR4 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR4_PARAM_Pos (0U) +#define HSP_PARAMR4_PARAM_Pos (0UL) #define HSP_PARAMR4_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR4_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR4_PARAM HSP_PARAMR4_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR4_PARAM_0 (0x00001UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR4_PARAM_1 (0x00002UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR4_PARAM_2 (0x00004UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR4_PARAM_3 (0x00008UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR4_PARAM_4 (0x00010UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR4_PARAM_5 (0x00020UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR4_PARAM_6 (0x00040UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR4_PARAM_7 (0x00080UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR4_PARAM_8 (0x00100UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR4_PARAM_9 (0x00200UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR4_PARAM_10 (0x00400UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR4_PARAM_11 (0x00800UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR4_PARAM_12 (0x01000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR4_PARAM_13 (0x02000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR4_PARAM_14 (0x04000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR4_PARAM_15 (0x08000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR4_PARAM_16 (0x10000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR4_PARAM_17 (0x20000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR4_PARAM_18 (0x40000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR4_PARAM_19 (0x80000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR4_PARAM_20 (0x100000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR4_PARAM_21 (0x200000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR4_PARAM_22 (0x400000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR4_PARAM_23 (0x800000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR4_PARAM_24 (0x1000000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR4_PARAM_25 (0x2000000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR4_PARAM_26 (0x4000000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR4_PARAM_27 (0x8000000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR4_PARAM_28 (0x10000000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR4_PARAM_29 (0x20000000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR4_PARAM_30 (0x40000000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR4_PARAM_31 (0x80000000UL << HSP_PARAMR4_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR5 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR5_PARAM_Pos (0U) +#define HSP_PARAMR5_PARAM_Pos (0UL) #define HSP_PARAMR5_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR5_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR5_PARAM HSP_PARAMR5_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR5_PARAM_0 (0x00001UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR5_PARAM_1 (0x00002UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR5_PARAM_2 (0x00004UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR5_PARAM_3 (0x00008UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR5_PARAM_4 (0x00010UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR5_PARAM_5 (0x00020UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR5_PARAM_6 (0x00040UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR5_PARAM_7 (0x00080UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR5_PARAM_8 (0x00100UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR5_PARAM_9 (0x00200UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR5_PARAM_10 (0x00400UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR5_PARAM_11 (0x00800UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR5_PARAM_12 (0x01000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR5_PARAM_13 (0x02000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR5_PARAM_14 (0x04000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR5_PARAM_15 (0x08000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR5_PARAM_16 (0x10000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR5_PARAM_17 (0x20000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR5_PARAM_18 (0x40000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR5_PARAM_19 (0x80000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR5_PARAM_20 (0x100000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR5_PARAM_21 (0x200000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR5_PARAM_22 (0x400000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR5_PARAM_23 (0x800000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR5_PARAM_24 (0x1000000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR5_PARAM_25 (0x2000000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR5_PARAM_26 (0x4000000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR5_PARAM_27 (0x8000000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR5_PARAM_28 (0x10000000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR5_PARAM_29 (0x20000000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR5_PARAM_30 (0x40000000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR5_PARAM_31 (0x80000000UL << HSP_PARAMR5_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR6 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR6_PARAM_Pos (0U) +#define HSP_PARAMR6_PARAM_Pos (0UL) #define HSP_PARAMR6_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR6_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR6_PARAM HSP_PARAMR6_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR6_PARAM_0 (0x00001UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR6_PARAM_1 (0x00002UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR6_PARAM_2 (0x00004UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR6_PARAM_3 (0x00008UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR6_PARAM_4 (0x00010UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR6_PARAM_5 (0x00020UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR6_PARAM_6 (0x00040UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR6_PARAM_7 (0x00080UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR6_PARAM_8 (0x00100UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR6_PARAM_9 (0x00200UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR6_PARAM_10 (0x00400UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR6_PARAM_11 (0x00800UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR6_PARAM_12 (0x01000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR6_PARAM_13 (0x02000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR6_PARAM_14 (0x04000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR6_PARAM_15 (0x08000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR6_PARAM_16 (0x10000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR6_PARAM_17 (0x20000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR6_PARAM_18 (0x40000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR6_PARAM_19 (0x80000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR6_PARAM_20 (0x100000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR6_PARAM_21 (0x200000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR6_PARAM_22 (0x400000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR6_PARAM_23 (0x800000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR6_PARAM_24 (0x1000000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR6_PARAM_25 (0x2000000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR6_PARAM_26 (0x4000000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR6_PARAM_27 (0x8000000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR6_PARAM_28 (0x10000000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR6_PARAM_29 (0x20000000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR6_PARAM_30 (0x40000000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR6_PARAM_31 (0x80000000UL << HSP_PARAMR6_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR7 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR7_PARAM_Pos (0U) +#define HSP_PARAMR7_PARAM_Pos (0UL) #define HSP_PARAMR7_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR7_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR7_PARAM HSP_PARAMR7_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR7_PARAM_0 (0x00001UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR7_PARAM_1 (0x00002UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR7_PARAM_2 (0x00004UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR7_PARAM_3 (0x00008UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR7_PARAM_4 (0x00010UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR7_PARAM_5 (0x00020UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR7_PARAM_6 (0x00040UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR7_PARAM_7 (0x00080UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR7_PARAM_8 (0x00100UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR7_PARAM_9 (0x00200UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR7_PARAM_10 (0x00400UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR7_PARAM_11 (0x00800UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR7_PARAM_12 (0x01000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR7_PARAM_13 (0x02000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR7_PARAM_14 (0x04000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR7_PARAM_15 (0x08000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR7_PARAM_16 (0x10000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR7_PARAM_17 (0x20000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR7_PARAM_18 (0x40000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR7_PARAM_19 (0x80000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR7_PARAM_20 (0x100000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR7_PARAM_21 (0x200000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR7_PARAM_22 (0x400000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR7_PARAM_23 (0x800000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR7_PARAM_24 (0x1000000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR7_PARAM_25 (0x2000000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR7_PARAM_26 (0x4000000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR7_PARAM_27 (0x8000000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR7_PARAM_28 (0x10000000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR7_PARAM_29 (0x20000000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR7_PARAM_30 (0x40000000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR7_PARAM_31 (0x80000000UL << HSP_PARAMR7_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR8 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR8_PARAM_Pos (0U) +#define HSP_PARAMR8_PARAM_Pos (0UL) #define HSP_PARAMR8_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR8_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR8_PARAM HSP_PARAMR8_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR8_PARAM_0 (0x00001UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR8_PARAM_1 (0x00002UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR8_PARAM_2 (0x00004UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR8_PARAM_3 (0x00008UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR8_PARAM_4 (0x00010UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR8_PARAM_5 (0x00020UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR8_PARAM_6 (0x00040UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR8_PARAM_7 (0x00080UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR8_PARAM_8 (0x00100UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR8_PARAM_9 (0x00200UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR8_PARAM_10 (0x00400UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR8_PARAM_11 (0x00800UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR8_PARAM_12 (0x01000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR8_PARAM_13 (0x02000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR8_PARAM_14 (0x04000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR8_PARAM_15 (0x08000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR8_PARAM_16 (0x10000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR8_PARAM_17 (0x20000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR8_PARAM_18 (0x40000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR8_PARAM_19 (0x80000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR8_PARAM_20 (0x100000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR8_PARAM_21 (0x200000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR8_PARAM_22 (0x400000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR8_PARAM_23 (0x800000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR8_PARAM_24 (0x1000000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR8_PARAM_25 (0x2000000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR8_PARAM_26 (0x4000000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR8_PARAM_27 (0x8000000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR8_PARAM_28 (0x10000000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR8_PARAM_29 (0x20000000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR8_PARAM_30 (0x40000000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR8_PARAM_31 (0x80000000UL << HSP_PARAMR8_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR9 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR9_PARAM_Pos (0U) +#define HSP_PARAMR9_PARAM_Pos (0UL) #define HSP_PARAMR9_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR9_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR9_PARAM HSP_PARAMR9_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR9_PARAM_0 (0x00001UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR9_PARAM_1 (0x00002UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR9_PARAM_2 (0x00004UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR9_PARAM_3 (0x00008UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR9_PARAM_4 (0x00010UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR9_PARAM_5 (0x00020UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR9_PARAM_6 (0x00040UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR9_PARAM_7 (0x00080UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR9_PARAM_8 (0x00100UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR9_PARAM_9 (0x00200UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR9_PARAM_10 (0x00400UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR9_PARAM_11 (0x00800UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR9_PARAM_12 (0x01000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR9_PARAM_13 (0x02000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR9_PARAM_14 (0x04000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR9_PARAM_15 (0x08000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR9_PARAM_16 (0x10000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR9_PARAM_17 (0x20000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR9_PARAM_18 (0x40000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR9_PARAM_19 (0x80000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR9_PARAM_20 (0x100000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR9_PARAM_21 (0x200000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR9_PARAM_22 (0x400000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR9_PARAM_23 (0x800000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR9_PARAM_24 (0x1000000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR9_PARAM_25 (0x2000000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR9_PARAM_26 (0x4000000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR9_PARAM_27 (0x8000000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR9_PARAM_28 (0x10000000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR9_PARAM_29 (0x20000000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR9_PARAM_30 (0x40000000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR9_PARAM_31 (0x80000000UL << HSP_PARAMR9_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR10 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR10_PARAM_Pos (0U) +#define HSP_PARAMR10_PARAM_Pos (0UL) #define HSP_PARAMR10_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR10_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR10_PARAM HSP_PARAMR10_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR10_PARAM_0 (0x00001UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR10_PARAM_1 (0x00002UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR10_PARAM_2 (0x00004UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR10_PARAM_3 (0x00008UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR10_PARAM_4 (0x00010UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR10_PARAM_5 (0x00020UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR10_PARAM_6 (0x00040UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR10_PARAM_7 (0x00080UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR10_PARAM_8 (0x00100UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR10_PARAM_9 (0x00200UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR10_PARAM_10 (0x00400UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR10_PARAM_11 (0x00800UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR10_PARAM_12 (0x01000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR10_PARAM_13 (0x02000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR10_PARAM_14 (0x04000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR10_PARAM_15 (0x08000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR10_PARAM_16 (0x10000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR10_PARAM_17 (0x20000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR10_PARAM_18 (0x40000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR10_PARAM_19 (0x80000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR10_PARAM_20 (0x100000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR10_PARAM_21 (0x200000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR10_PARAM_22 (0x400000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR10_PARAM_23 (0x800000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR10_PARAM_24 (0x1000000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR10_PARAM_25 (0x2000000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR10_PARAM_26 (0x4000000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR10_PARAM_27 (0x8000000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR10_PARAM_28 (0x10000000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR10_PARAM_29 (0x20000000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR10_PARAM_30 (0x40000000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR10_PARAM_31 (0x80000000UL << HSP_PARAMR10_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR11 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR11_PARAM_Pos (0U) +#define HSP_PARAMR11_PARAM_Pos (0UL) #define HSP_PARAMR11_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR11_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR11_PARAM HSP_PARAMR11_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR11_PARAM_0 (0x00001UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR11_PARAM_1 (0x00002UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR11_PARAM_2 (0x00004UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR11_PARAM_3 (0x00008UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR11_PARAM_4 (0x00010UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR11_PARAM_5 (0x00020UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR11_PARAM_6 (0x00040UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR11_PARAM_7 (0x00080UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR11_PARAM_8 (0x00100UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR11_PARAM_9 (0x00200UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR11_PARAM_10 (0x00400UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR11_PARAM_11 (0x00800UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR11_PARAM_12 (0x01000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR11_PARAM_13 (0x02000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR11_PARAM_14 (0x04000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR11_PARAM_15 (0x08000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR11_PARAM_16 (0x10000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR11_PARAM_17 (0x20000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR11_PARAM_18 (0x40000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR11_PARAM_19 (0x80000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR11_PARAM_20 (0x100000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR11_PARAM_21 (0x200000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR11_PARAM_22 (0x400000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR11_PARAM_23 (0x800000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR11_PARAM_24 (0x1000000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR11_PARAM_25 (0x2000000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR11_PARAM_26 (0x4000000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR11_PARAM_27 (0x8000000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR11_PARAM_28 (0x10000000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR11_PARAM_29 (0x20000000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR11_PARAM_30 (0x40000000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR11_PARAM_31 (0x80000000UL << HSP_PARAMR11_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR12 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR12_PARAM_Pos (0U) +#define HSP_PARAMR12_PARAM_Pos (0UL) #define HSP_PARAMR12_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR12_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR12_PARAM HSP_PARAMR12_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR12_PARAM_0 (0x00001UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR12_PARAM_1 (0x00002UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR12_PARAM_2 (0x00004UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR12_PARAM_3 (0x00008UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR12_PARAM_4 (0x00010UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR12_PARAM_5 (0x00020UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR12_PARAM_6 (0x00040UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR12_PARAM_7 (0x00080UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR12_PARAM_8 (0x00100UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR12_PARAM_9 (0x00200UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR12_PARAM_10 (0x00400UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR12_PARAM_11 (0x00800UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR12_PARAM_12 (0x01000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR12_PARAM_13 (0x02000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR12_PARAM_14 (0x04000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR12_PARAM_15 (0x08000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR12_PARAM_16 (0x10000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR12_PARAM_17 (0x20000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR12_PARAM_18 (0x40000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR12_PARAM_19 (0x80000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR12_PARAM_20 (0x100000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR12_PARAM_21 (0x200000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR12_PARAM_22 (0x400000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR12_PARAM_23 (0x800000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR12_PARAM_24 (0x1000000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR12_PARAM_25 (0x2000000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR12_PARAM_26 (0x4000000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR12_PARAM_27 (0x8000000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR12_PARAM_28 (0x10000000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR12_PARAM_29 (0x20000000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR12_PARAM_30 (0x40000000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR12_PARAM_31 (0x80000000UL << HSP_PARAMR12_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR13 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR13_PARAM_Pos (0U) +#define HSP_PARAMR13_PARAM_Pos (0UL) #define HSP_PARAMR13_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR13_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR13_PARAM HSP_PARAMR13_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR13_PARAM_0 (0x00001UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR13_PARAM_1 (0x00002UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR13_PARAM_2 (0x00004UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR13_PARAM_3 (0x00008UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR13_PARAM_4 (0x00010UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR13_PARAM_5 (0x00020UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR13_PARAM_6 (0x00040UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR13_PARAM_7 (0x00080UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR13_PARAM_8 (0x00100UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR13_PARAM_9 (0x00200UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR13_PARAM_10 (0x00400UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR13_PARAM_11 (0x00800UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR13_PARAM_12 (0x01000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR13_PARAM_13 (0x02000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR13_PARAM_14 (0x04000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR13_PARAM_15 (0x08000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR13_PARAM_16 (0x10000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR13_PARAM_17 (0x20000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR13_PARAM_18 (0x40000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR13_PARAM_19 (0x80000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR13_PARAM_20 (0x100000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR13_PARAM_21 (0x200000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR13_PARAM_22 (0x400000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR13_PARAM_23 (0x800000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR13_PARAM_24 (0x1000000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR13_PARAM_25 (0x2000000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR13_PARAM_26 (0x4000000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR13_PARAM_27 (0x8000000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR13_PARAM_28 (0x10000000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR13_PARAM_29 (0x20000000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR13_PARAM_30 (0x40000000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR13_PARAM_31 (0x80000000UL << HSP_PARAMR13_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR14 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR14_PARAM_Pos (0U) +#define HSP_PARAMR14_PARAM_Pos (0UL) #define HSP_PARAMR14_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR14_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR14_PARAM HSP_PARAMR14_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR14_PARAM_0 (0x00001UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR14_PARAM_1 (0x00002UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR14_PARAM_2 (0x00004UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR14_PARAM_3 (0x00008UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR14_PARAM_4 (0x00010UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR14_PARAM_5 (0x00020UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR14_PARAM_6 (0x00040UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR14_PARAM_7 (0x00080UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR14_PARAM_8 (0x00100UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR14_PARAM_9 (0x00200UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR14_PARAM_10 (0x00400UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR14_PARAM_11 (0x00800UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR14_PARAM_12 (0x01000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR14_PARAM_13 (0x02000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR14_PARAM_14 (0x04000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR14_PARAM_15 (0x08000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR14_PARAM_16 (0x10000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR14_PARAM_17 (0x20000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR14_PARAM_18 (0x40000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR14_PARAM_19 (0x80000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR14_PARAM_20 (0x100000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR14_PARAM_21 (0x200000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR14_PARAM_22 (0x400000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR14_PARAM_23 (0x800000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR14_PARAM_24 (0x1000000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR14_PARAM_25 (0x2000000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR14_PARAM_26 (0x4000000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR14_PARAM_27 (0x8000000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR14_PARAM_28 (0x10000000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR14_PARAM_29 (0x20000000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR14_PARAM_30 (0x40000000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR14_PARAM_31 (0x80000000UL << HSP_PARAMR14_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_PARAMR15 register ********************/ /*!< PARAM configuration */ -#define HSP_PARAMR15_PARAM_Pos (0U) +#define HSP_PARAMR15_PARAM_Pos (0UL) #define HSP_PARAMR15_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR15_PARAM_Pos) /*!< 0xFFFFFFFF */ #define HSP_PARAMR15_PARAM HSP_PARAMR15_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ -#define HSP_PARAMR15_PARAM_0 (0x00001UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00000001 */ -#define HSP_PARAMR15_PARAM_1 (0x00002UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00000002 */ -#define HSP_PARAMR15_PARAM_2 (0x00004UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00000004 */ -#define HSP_PARAMR15_PARAM_3 (0x00008UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00000008 */ -#define HSP_PARAMR15_PARAM_4 (0x00010UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00000010 */ -#define HSP_PARAMR15_PARAM_5 (0x00020UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00000020 */ -#define HSP_PARAMR15_PARAM_6 (0x00040UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00000040 */ -#define HSP_PARAMR15_PARAM_7 (0x00080UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00000080 */ -#define HSP_PARAMR15_PARAM_8 (0x00100UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00000100 */ -#define HSP_PARAMR15_PARAM_9 (0x00200UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00000200 */ -#define HSP_PARAMR15_PARAM_10 (0x00400UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00000400 */ -#define HSP_PARAMR15_PARAM_11 (0x00800UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00000800 */ -#define HSP_PARAMR15_PARAM_12 (0x01000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00001000 */ -#define HSP_PARAMR15_PARAM_13 (0x02000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00002000 */ -#define HSP_PARAMR15_PARAM_14 (0x04000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00004000 */ -#define HSP_PARAMR15_PARAM_15 (0x08000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00008000 */ -#define HSP_PARAMR15_PARAM_16 (0x10000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00010000 */ -#define HSP_PARAMR15_PARAM_17 (0x20000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00020000 */ -#define HSP_PARAMR15_PARAM_18 (0x40000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00040000 */ -#define HSP_PARAMR15_PARAM_19 (0x80000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00080000 */ -#define HSP_PARAMR15_PARAM_20 (0x100000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00100000 */ -#define HSP_PARAMR15_PARAM_21 (0x200000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00200000 */ -#define HSP_PARAMR15_PARAM_22 (0x400000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00400000 */ -#define HSP_PARAMR15_PARAM_23 (0x800000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x00800000 */ -#define HSP_PARAMR15_PARAM_24 (0x1000000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x01000000 */ -#define HSP_PARAMR15_PARAM_25 (0x2000000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x02000000 */ -#define HSP_PARAMR15_PARAM_26 (0x4000000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x04000000 */ -#define HSP_PARAMR15_PARAM_27 (0x8000000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x08000000 */ -#define HSP_PARAMR15_PARAM_28 (0x10000000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x10000000 */ -#define HSP_PARAMR15_PARAM_29 (0x20000000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x20000000 */ -#define HSP_PARAMR15_PARAM_30 (0x40000000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x40000000 */ -#define HSP_PARAMR15_PARAM_31 (0x80000000UL << HSP_PARAMR15_PARAM_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_SPE_IER register ********************/ -/*!< C2HMRDYIE configuration */ -#define HSP_SPE_IER_C2HMRDYIE_Pos (0U) +#define HSP_SPE_IER_C2HMRDYIE_Pos (0UL) #define HSP_SPE_IER_C2HMRDYIE_Msk (0x1UL << HSP_SPE_IER_C2HMRDYIE_Pos) /*!< 0x00000001 */ #define HSP_SPE_IER_C2HMRDYIE HSP_SPE_IER_C2HMRDYIE_Msk /*!< C2HMRDYIE (CPU to SPE message ready interrupt enable) */ -/*!< H2CMFREEIE configuration */ -#define HSP_SPE_IER_H2CMFREEIE_Pos (1U) + +#define HSP_SPE_IER_H2CMFREEIE_Pos (1UL) #define HSP_SPE_IER_H2CMFREEIE_Msk (0x1UL << HSP_SPE_IER_H2CMFREEIE_Pos) /*!< 0x00000002 */ #define HSP_SPE_IER_H2CMFREEIE HSP_SPE_IER_H2CMFREEIE_Msk /*!< H2CMFREEIE (SPE to CPU message free interrupt enable) */ /******************** Bit definition for HSP_SPE_ISR register ********************/ -/*!< C2HMRDYF configuration */ -#define HSP_SPE_ISR_C2HMRDYF_Pos (0U) +#define HSP_SPE_ISR_C2HMRDYF_Pos (0UL) #define HSP_SPE_ISR_C2HMRDYF_Msk (0x1UL << HSP_SPE_ISR_C2HMRDYF_Pos) /*!< 0x00000001 */ #define HSP_SPE_ISR_C2HMRDYF HSP_SPE_ISR_C2HMRDYF_Msk /*!< C2HMRDYF (CPU to SPE message box status) */ -/*!< H2CMFREEF configuration */ -#define HSP_SPE_ISR_H2CMFREEF_Pos (1U) + +#define HSP_SPE_ISR_H2CMFREEF_Pos (1UL) #define HSP_SPE_ISR_H2CMFREEF_Msk (0x1UL << HSP_SPE_ISR_H2CMFREEF_Pos) /*!< 0x00000002 */ #define HSP_SPE_ISR_H2CMFREEF HSP_SPE_ISR_H2CMFREEF_Msk /*!< H2CMFREEF (SPE to CPU message box status) */ -/*!< RSTREQF configuration */ -#define HSP_SPE_ISR_RSTREQF_Pos (4U) + +#define HSP_SPE_ISR_RSTREQF_Pos (4UL) #define HSP_SPE_ISR_RSTREQF_Msk (0x1UL << HSP_SPE_ISR_RSTREQF_Pos) /*!< 0x00000010 */ #define HSP_SPE_ISR_RSTREQF HSP_SPE_ISR_RSTREQF_Msk /*!< RSTREQF (HSP reset request) */ -/*!< BUF0EVTF configuration */ -#define HSP_SPE_ISR_BUF0EVTF_Pos (12U) + +#define HSP_SPE_ISR_BUF0EVTF_Pos (12UL) #define HSP_SPE_ISR_BUF0EVTF_Msk (0x1UL << HSP_SPE_ISR_BUF0EVTF_Pos) /*!< 0x00001000 */ #define HSP_SPE_ISR_BUF0EVTF HSP_SPE_ISR_BUF0EVTF_Msk /*!< BUF0EVTF (BUF0 status) */ -/*!< BUF1EVTF configuration */ -#define HSP_SPE_ISR_BUF1EVTF_Pos (13U) + +#define HSP_SPE_ISR_BUF1EVTF_Pos (13UL) #define HSP_SPE_ISR_BUF1EVTF_Msk (0x1UL << HSP_SPE_ISR_BUF1EVTF_Pos) /*!< 0x00002000 */ #define HSP_SPE_ISR_BUF1EVTF HSP_SPE_ISR_BUF1EVTF_Msk /*!< BUF1EVTF (BUF1 status) */ -/*!< BUF2EVTF configuration */ -#define HSP_SPE_ISR_BUF2EVTF_Pos (14U) + +#define HSP_SPE_ISR_BUF2EVTF_Pos (14UL) #define HSP_SPE_ISR_BUF2EVTF_Msk (0x1UL << HSP_SPE_ISR_BUF2EVTF_Pos) /*!< 0x00004000 */ #define HSP_SPE_ISR_BUF2EVTF HSP_SPE_ISR_BUF2EVTF_Msk /*!< BUF2EVTF (BUF2 status) */ -/*!< BUF3EVTF configuration */ -#define HSP_SPE_ISR_BUF3EVTF_Pos (15U) + +#define HSP_SPE_ISR_BUF3EVTF_Pos (15UL) #define HSP_SPE_ISR_BUF3EVTF_Msk (0x1UL << HSP_SPE_ISR_BUF3EVTF_Pos) /*!< 0x00008000 */ #define HSP_SPE_ISR_BUF3EVTF HSP_SPE_ISR_BUF3EVTF_Msk /*!< BUF3EVTF (BUF3 status) */ /******************** Bit definition for HSP_TCUCFGR register ********************/ -/*!< TSKCMP0 configuration */ -#define HSP_TCUCFGR_TSKCMP0_Pos (0U) +#define HSP_TCUCFGR_TSKCMP0_Pos (0UL) #define HSP_TCUCFGR_TSKCMP0_Msk (0x3FUL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x0000003F */ #define HSP_TCUCFGR_TSKCMP0 HSP_TCUCFGR_TSKCMP0_Msk /*!< TSKCMP0[5:0] bits (Task compare 0 (1)) */ #define HSP_TCUCFGR_TSKCMP0_0 (0x01UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000001 */ @@ -13032,12 +13685,12 @@ typedef struct #define HSP_TCUCFGR_TSKCMP0_3 (0x08UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000008 */ #define HSP_TCUCFGR_TSKCMP0_4 (0x10UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000010 */ #define HSP_TCUCFGR_TSKCMP0_5 (0x20UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000020 */ -/*!< TC0EN configuration */ -#define HSP_TCUCFGR_TC0EN_Pos (7U) + +#define HSP_TCUCFGR_TC0EN_Pos (7UL) #define HSP_TCUCFGR_TC0EN_Msk (0x1UL << HSP_TCUCFGR_TC0EN_Pos) /*!< 0x00000080 */ #define HSP_TCUCFGR_TC0EN HSP_TCUCFGR_TC0EN_Msk /*!< TC0EN (Task comparator 0 enable (1)) */ -/*!< TSKCMP1 configuration */ -#define HSP_TCUCFGR_TSKCMP1_Pos (8U) + +#define HSP_TCUCFGR_TSKCMP1_Pos (8UL) #define HSP_TCUCFGR_TSKCMP1_Msk (0x3FUL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00003F00 */ #define HSP_TCUCFGR_TSKCMP1 HSP_TCUCFGR_TSKCMP1_Msk /*!< TSKCMP1[5:0] bits (Task compare 1 (1)) */ #define HSP_TCUCFGR_TSKCMP1_0 (0x01UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00000100 */ @@ -13046,12 +13699,12 @@ typedef struct #define HSP_TCUCFGR_TSKCMP1_3 (0x08UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00000800 */ #define HSP_TCUCFGR_TSKCMP1_4 (0x10UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00001000 */ #define HSP_TCUCFGR_TSKCMP1_5 (0x20UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00002000 */ -/*!< TC1EN configuration */ -#define HSP_TCUCFGR_TC1EN_Pos (15U) + +#define HSP_TCUCFGR_TC1EN_Pos (15UL) #define HSP_TCUCFGR_TC1EN_Msk (0x1UL << HSP_TCUCFGR_TC1EN_Pos) /*!< 0x00008000 */ #define HSP_TCUCFGR_TC1EN HSP_TCUCFGR_TC1EN_Msk /*!< TC1EN (Task comparator 1 enable (1)) */ -/*!< TSKCMP2 configuration */ -#define HSP_TCUCFGR_TSKCMP2_Pos (16U) + +#define HSP_TCUCFGR_TSKCMP2_Pos (16UL) #define HSP_TCUCFGR_TSKCMP2_Msk (0x3FUL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x003F0000 */ #define HSP_TCUCFGR_TSKCMP2 HSP_TCUCFGR_TSKCMP2_Msk /*!< TSKCMP2[5:0] bits (Task compare 2 (1)) */ #define HSP_TCUCFGR_TSKCMP2_0 (0x01UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00010000 */ @@ -13060,12 +13713,12 @@ typedef struct #define HSP_TCUCFGR_TSKCMP2_3 (0x08UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00080000 */ #define HSP_TCUCFGR_TSKCMP2_4 (0x10UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00100000 */ #define HSP_TCUCFGR_TSKCMP2_5 (0x20UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00200000 */ -/*!< TC2EN configuration */ -#define HSP_TCUCFGR_TC2EN_Pos (23U) + +#define HSP_TCUCFGR_TC2EN_Pos (23UL) #define HSP_TCUCFGR_TC2EN_Msk (0x1UL << HSP_TCUCFGR_TC2EN_Pos) /*!< 0x00800000 */ #define HSP_TCUCFGR_TC2EN HSP_TCUCFGR_TC2EN_Msk /*!< TC2EN (Task comparator 2 enable (1)) */ -/*!< TSKCMP3 configuration */ -#define HSP_TCUCFGR_TSKCMP3_Pos (24U) + +#define HSP_TCUCFGR_TSKCMP3_Pos (24UL) #define HSP_TCUCFGR_TSKCMP3_Msk (0x3FUL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x3F000000 */ #define HSP_TCUCFGR_TSKCMP3 HSP_TCUCFGR_TSKCMP3_Msk /*!< TSKCMP3[5:0] bits (Task compare 3 (1)) */ #define HSP_TCUCFGR_TSKCMP3_0 (0x01UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x01000000 */ @@ -13074,47 +13727,33 @@ typedef struct #define HSP_TCUCFGR_TSKCMP3_3 (0x08UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x08000000 */ #define HSP_TCUCFGR_TSKCMP3_4 (0x10UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x10000000 */ #define HSP_TCUCFGR_TSKCMP3_5 (0x20UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x20000000 */ -/*!< TC3EN configuration */ -#define HSP_TCUCFGR_TC3EN_Pos (31U) + +#define HSP_TCUCFGR_TC3EN_Pos (31UL) #define HSP_TCUCFGR_TC3EN_Msk (0x1UL << HSP_TCUCFGR_TC3EN_Pos) /*!< 0x80000000 */ #define HSP_TCUCFGR_TC3EN HSP_TCUCFGR_TC3EN_Msk /*!< TC3EN (Task comparator 3 enable ) */ /******************** Bit definition for HSP_TOVLPCR register ********************/ -/*!< TOVLPEN configuration */ -#define HSP_TOVLPCR_TOVLPEN_Pos (0U) +#define HSP_TOVLPCR_TOVLPEN_Pos (0UL) #define HSP_TOVLPCR_TOVLPEN_Msk (0x1UL << HSP_TOVLPCR_TOVLPEN_Pos) /*!< 0x00000001 */ #define HSP_TOVLPCR_TOVLPEN HSP_TOVLPCR_TOVLPEN_Msk /*!< TOVLPEN (Task overlap enable (1)) */ -/*!< LTNB configuration */ -#define HSP_TOVLPCR_LTNB_Pos (8U) + +#define HSP_TOVLPCR_LTNB_Pos (8UL) #define HSP_TOVLPCR_LTNB_Msk (0x3FUL << HSP_TOVLPCR_LTNB_Pos) /*!< 0x00003F00 */ #define HSP_TOVLPCR_LTNB HSP_TOVLPCR_LTNB_Msk /*!< LTNB[5:0] bits (Lower task number value (1)) */ -#define HSP_TOVLPCR_LTNB_0 (0x01UL << HSP_TOVLPCR_LTNB_Pos) /*!< 0x00000100 */ -#define HSP_TOVLPCR_LTNB_1 (0x02UL << HSP_TOVLPCR_LTNB_Pos) /*!< 0x00000200 */ -#define HSP_TOVLPCR_LTNB_2 (0x04UL << HSP_TOVLPCR_LTNB_Pos) /*!< 0x00000400 */ -#define HSP_TOVLPCR_LTNB_3 (0x08UL << HSP_TOVLPCR_LTNB_Pos) /*!< 0x00000800 */ -#define HSP_TOVLPCR_LTNB_4 (0x10UL << HSP_TOVLPCR_LTNB_Pos) /*!< 0x00001000 */ -#define HSP_TOVLPCR_LTNB_5 (0x20UL << HSP_TOVLPCR_LTNB_Pos) /*!< 0x00002000 */ -/*!< HTNB configuration */ -#define HSP_TOVLPCR_HTNB_Pos (16U) + +#define HSP_TOVLPCR_HTNB_Pos (16UL) #define HSP_TOVLPCR_HTNB_Msk (0x3FUL << HSP_TOVLPCR_HTNB_Pos) /*!< 0x003F0000 */ #define HSP_TOVLPCR_HTNB HSP_TOVLPCR_HTNB_Msk /*!< HTNB[5:0] bits (Higher task number value ) */ -#define HSP_TOVLPCR_HTNB_0 (0x01UL << HSP_TOVLPCR_HTNB_Pos) /*!< 0x00010000 */ -#define HSP_TOVLPCR_HTNB_1 (0x02UL << HSP_TOVLPCR_HTNB_Pos) /*!< 0x00020000 */ -#define HSP_TOVLPCR_HTNB_2 (0x04UL << HSP_TOVLPCR_HTNB_Pos) /*!< 0x00040000 */ -#define HSP_TOVLPCR_HTNB_3 (0x08UL << HSP_TOVLPCR_HTNB_Pos) /*!< 0x00080000 */ -#define HSP_TOVLPCR_HTNB_4 (0x10UL << HSP_TOVLPCR_HTNB_Pos) /*!< 0x00100000 */ -#define HSP_TOVLPCR_HTNB_5 (0x20UL << HSP_TOVLPCR_HTNB_Pos) /*!< 0x00200000 */ /******************** Bit definition for HSP_SNPR register ********************/ -/*!< SNPSELA configuration */ -#define HSP_SNPR_SNPSELA_Pos (0U) +#define HSP_SNPR_SNPSELA_Pos (0UL) #define HSP_SNPR_SNPSELA_Msk (0x7UL << HSP_SNPR_SNPSELA_Pos) /*!< 0x00000007 */ #define HSP_SNPR_SNPSELA HSP_SNPR_SNPSELA_Msk /*!< SNPSELA[2:0] bits (Snoop group A signal selection) */ #define HSP_SNPR_SNPSELA_0 (0x1UL << HSP_SNPR_SNPSELA_Pos) /*!< 0x00000001 */ #define HSP_SNPR_SNPSELA_1 (0x2UL << HSP_SNPR_SNPSELA_Pos) /*!< 0x00000002 */ #define HSP_SNPR_SNPSELA_2 (0x4UL << HSP_SNPR_SNPSELA_Pos) /*!< 0x00000004 */ -/*!< SNPSELB configuration */ -#define HSP_SNPR_SNPSELB_Pos (4U) + +#define HSP_SNPR_SNPSELB_Pos (4UL) #define HSP_SNPR_SNPSELB_Msk (0x7UL << HSP_SNPR_SNPSELB_Pos) /*!< 0x00000070 */ #define HSP_SNPR_SNPSELB HSP_SNPR_SNPSELB_Msk /*!< SNPSELB[2:0] bits (Snoop group B signal selection) */ #define HSP_SNPR_SNPSELB_0 (0x1UL << HSP_SNPR_SNPSELB_Pos) /*!< 0x00000010 */ @@ -13122,116 +13761,49 @@ typedef struct #define HSP_SNPR_SNPSELB_2 (0x4UL << HSP_SNPR_SNPSELB_Pos) /*!< 0x00000040 */ /******************** Bit definition for HSP_CCNTR register ********************/ -/*!< CCNTR configuration */ -#define HSP_CCNTR_CCNTR_Pos (0U) +#define HSP_CCNTR_CCNTR_Pos (0UL) #define HSP_CCNTR_CCNTR_Msk (0xFFFFFFFFUL << HSP_CCNTR_CCNTR_Pos) /*!< 0xFFFFFFFF */ #define HSP_CCNTR_CCNTR HSP_CCNTR_CCNTR_Msk /*!< CCNTR[31:0] bits (Conflict counter) */ -#define HSP_CCNTR_CCNTR_0 (0x00001UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00000001 */ -#define HSP_CCNTR_CCNTR_1 (0x00002UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00000002 */ -#define HSP_CCNTR_CCNTR_2 (0x00004UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00000004 */ -#define HSP_CCNTR_CCNTR_3 (0x00008UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00000008 */ -#define HSP_CCNTR_CCNTR_4 (0x00010UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00000010 */ -#define HSP_CCNTR_CCNTR_5 (0x00020UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00000020 */ -#define HSP_CCNTR_CCNTR_6 (0x00040UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00000040 */ -#define HSP_CCNTR_CCNTR_7 (0x00080UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00000080 */ -#define HSP_CCNTR_CCNTR_8 (0x00100UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00000100 */ -#define HSP_CCNTR_CCNTR_9 (0x00200UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00000200 */ -#define HSP_CCNTR_CCNTR_10 (0x00400UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00000400 */ -#define HSP_CCNTR_CCNTR_11 (0x00800UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00000800 */ -#define HSP_CCNTR_CCNTR_12 (0x01000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00001000 */ -#define HSP_CCNTR_CCNTR_13 (0x02000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00002000 */ -#define HSP_CCNTR_CCNTR_14 (0x04000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00004000 */ -#define HSP_CCNTR_CCNTR_15 (0x08000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00008000 */ -#define HSP_CCNTR_CCNTR_16 (0x10000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00010000 */ -#define HSP_CCNTR_CCNTR_17 (0x20000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00020000 */ -#define HSP_CCNTR_CCNTR_18 (0x40000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00040000 */ -#define HSP_CCNTR_CCNTR_19 (0x80000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00080000 */ -#define HSP_CCNTR_CCNTR_20 (0x100000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00100000 */ -#define HSP_CCNTR_CCNTR_21 (0x200000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00200000 */ -#define HSP_CCNTR_CCNTR_22 (0x400000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00400000 */ -#define HSP_CCNTR_CCNTR_23 (0x800000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x00800000 */ -#define HSP_CCNTR_CCNTR_24 (0x1000000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x01000000 */ -#define HSP_CCNTR_CCNTR_25 (0x2000000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x02000000 */ -#define HSP_CCNTR_CCNTR_26 (0x4000000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x04000000 */ -#define HSP_CCNTR_CCNTR_27 (0x8000000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x08000000 */ -#define HSP_CCNTR_CCNTR_28 (0x10000000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x10000000 */ -#define HSP_CCNTR_CCNTR_29 (0x20000000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x20000000 */ -#define HSP_CCNTR_CCNTR_30 (0x40000000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x40000000 */ -#define HSP_CCNTR_CCNTR_31 (0x80000000UL << HSP_CCNTR_CCNTR_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for HSP_CAPDR register ********************/ -/*!< TSTAMP configuration */ -#define HSP_CAPDR_TSTAMP_Pos (0U) -#define HSP_CAPDR_TSTAMP_Msk (0x3FFFUL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00003FFF */ -#define HSP_CAPDR_TSTAMP HSP_CAPDR_TSTAMP_Msk /*!< TSTAMP[13:0] bits (Time-stamp value) */ -#define HSP_CAPDR_TSTAMP_0 (0x001UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00000001 */ -#define HSP_CAPDR_TSTAMP_1 (0x002UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00000002 */ -#define HSP_CAPDR_TSTAMP_2 (0x004UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00000004 */ -#define HSP_CAPDR_TSTAMP_3 (0x008UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00000008 */ -#define HSP_CAPDR_TSTAMP_4 (0x010UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00000010 */ -#define HSP_CAPDR_TSTAMP_5 (0x020UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00000020 */ -#define HSP_CAPDR_TSTAMP_6 (0x040UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00000040 */ -#define HSP_CAPDR_TSTAMP_7 (0x080UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00000080 */ -#define HSP_CAPDR_TSTAMP_8 (0x100UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00000100 */ -#define HSP_CAPDR_TSTAMP_9 (0x200UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00000200 */ -#define HSP_CAPDR_TSTAMP_10 (0x400UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00000400 */ -#define HSP_CAPDR_TSTAMP_11 (0x800UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00000800 */ -#define HSP_CAPDR_TSTAMP_12 (0x1000UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00001000 */ -#define HSP_CAPDR_TSTAMP_13 (0x2000UL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00002000 */ -/*!< IFHIST configuration */ -#define HSP_CAPDR_IFHIST_Pos (14U) -#define HSP_CAPDR_IFHIST_Msk (0xFFUL << HSP_CAPDR_IFHIST_Pos) /*!< 0x003FC000 */ -#define HSP_CAPDR_IFHIST HSP_CAPDR_IFHIST_Msk /*!< IFHIST[7:0] bits (IF condition history) */ -#define HSP_CAPDR_IFHIST_0 (0x001UL << HSP_CAPDR_IFHIST_Pos) /*!< 0x00004000 */ -#define HSP_CAPDR_IFHIST_1 (0x002UL << HSP_CAPDR_IFHIST_Pos) /*!< 0x00008000 */ -#define HSP_CAPDR_IFHIST_2 (0x004UL << HSP_CAPDR_IFHIST_Pos) /*!< 0x00010000 */ -#define HSP_CAPDR_IFHIST_3 (0x008UL << HSP_CAPDR_IFHIST_Pos) /*!< 0x00020000 */ -#define HSP_CAPDR_IFHIST_4 (0x010UL << HSP_CAPDR_IFHIST_Pos) /*!< 0x00040000 */ -#define HSP_CAPDR_IFHIST_5 (0x020UL << HSP_CAPDR_IFHIST_Pos) /*!< 0x00080000 */ -#define HSP_CAPDR_IFHIST_6 (0x040UL << HSP_CAPDR_IFHIST_Pos) /*!< 0x00100000 */ -#define HSP_CAPDR_IFHIST_7 (0x080UL << HSP_CAPDR_IFHIST_Pos) /*!< 0x00200000 */ -/*!< IFCNT configuration */ -#define HSP_CAPDR_IFCNT_Pos (22U) -#define HSP_CAPDR_IFCNT_Msk (0xFUL << HSP_CAPDR_IFCNT_Pos) /*!< 0x03C00000 */ -#define HSP_CAPDR_IFCNT HSP_CAPDR_IFCNT_Msk /*!< IFCNT[3:0] bits (IF instruction counter) */ -#define HSP_CAPDR_IFCNT_0 (0x01UL << HSP_CAPDR_IFCNT_Pos) /*!< 0x00400000 */ -#define HSP_CAPDR_IFCNT_1 (0x02UL << HSP_CAPDR_IFCNT_Pos) /*!< 0x00800000 */ -#define HSP_CAPDR_IFCNT_2 (0x04UL << HSP_CAPDR_IFCNT_Pos) /*!< 0x01000000 */ -#define HSP_CAPDR_IFCNT_3 (0x08UL << HSP_CAPDR_IFCNT_Pos) /*!< 0x02000000 */ -/*!< TSKNB configuration */ -#define HSP_CAPDR_TSKNB_Pos (26U) -#define HSP_CAPDR_TSKNB_Msk (0x3FUL << HSP_CAPDR_TSKNB_Pos) /*!< 0xFC000000 */ -#define HSP_CAPDR_TSKNB HSP_CAPDR_TSKNB_Msk /*!< TSKNB[5:0] bits (Last captured task number) */ -#define HSP_CAPDR_TSKNB_0 (0x01UL << HSP_CAPDR_TSKNB_Pos) /*!< 0x04000000 */ -#define HSP_CAPDR_TSKNB_1 (0x02UL << HSP_CAPDR_TSKNB_Pos) /*!< 0x08000000 */ -#define HSP_CAPDR_TSKNB_2 (0x04UL << HSP_CAPDR_TSKNB_Pos) /*!< 0x10000000 */ -#define HSP_CAPDR_TSKNB_3 (0x08UL << HSP_CAPDR_TSKNB_Pos) /*!< 0x20000000 */ -#define HSP_CAPDR_TSKNB_4 (0x10UL << HSP_CAPDR_TSKNB_Pos) /*!< 0x40000000 */ -#define HSP_CAPDR_TSKNB_5 (0x20UL << HSP_CAPDR_TSKNB_Pos) /*!< 0x80000000 */ -/*!< PFCTNB configuration */ -#define HSP_CAPDR_PFCTNB_Pos (16U) -#define HSP_CAPDR_PFCTNB_Msk (0x3FUL << HSP_CAPDR_PFCTNB_Pos) /*!< 0x003F0000 */ -#define HSP_CAPDR_PFCTNB HSP_CAPDR_PFCTNB_Msk /*!< PFCTNB[5:0] bits (Last captured processing function number) */ -#define HSP_CAPDR_PFCTNB_0 (0x01UL << HSP_CAPDR_PFCTNB_Pos) /*!< 0x00010000 */ -#define HSP_CAPDR_PFCTNB_1 (0x02UL << HSP_CAPDR_PFCTNB_Pos) /*!< 0x00020000 */ -#define HSP_CAPDR_PFCTNB_2 (0x04UL << HSP_CAPDR_PFCTNB_Pos) /*!< 0x00040000 */ -#define HSP_CAPDR_PFCTNB_3 (0x08UL << HSP_CAPDR_PFCTNB_Pos) /*!< 0x00080000 */ -#define HSP_CAPDR_PFCTNB_4 (0x10UL << HSP_CAPDR_PFCTNB_Pos) /*!< 0x00100000 */ -#define HSP_CAPDR_PFCTNB_5 (0x20UL << HSP_CAPDR_PFCTNB_Pos) /*!< 0x00200000 */ + +/****************** Bit definition for HSP_CAPDR register *******************/ +#define HSP_CAPDR_TSTAMP_Pos (0UL) +#define HSP_CAPDR_TSTAMP_Msk (0x3FFFUL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00003FFF */ +#define HSP_CAPDR_TSTAMP HSP_CAPDR_TSTAMP_Msk /*!< Time-stamp value */ +#define HSP_CAPDR_IFHIST_Pos (14UL) +#define HSP_CAPDR_IFHIST_Msk (0xFFUL << HSP_CAPDR_IFHIST_Pos) /*!< 0x003FC000 */ +#define HSP_CAPDR_IFHIST HSP_CAPDR_IFHIST_Msk /*!< IF condition history */ +#define HSP_CAPDR_IFCNT_Pos (22UL) +#define HSP_CAPDR_IFCNT_Msk (0xFUL << HSP_CAPDR_IFCNT_Pos) /*!< 0x03C00000 */ +#define HSP_CAPDR_IFCNT HSP_CAPDR_IFCNT_Msk /*!< IF instruction counter */ +#define HSP_CAPDR_TSKNB_Pos (26UL) +#define HSP_CAPDR_TSKNB_Msk (0x3FUL << HSP_CAPDR_TSKNB_Pos) /*!< 0xFC000000 */ +#define HSP_CAPDR_TSKNB HSP_CAPDR_TSKNB_Msk /*!< Last captured task number */ + +#define HSP_CAPDR_ALT_IFHIST_Pos (0UL) +#define HSP_CAPDR_ALT_IFHIST_Msk (0x7FFFUL << HSP_CAPDR_ALT_IFHIST_Pos) /*!< 0x00007FFF */ +#define HSP_CAPDR_ALT_IFHIST HSP_CAPDR_IFHIST_Msk /*!< IF condition history */ +#define HSP_CAPDR_ALT_PFCTNB_Pos (16UL) +#define HSP_CAPDR_ALT_PFCTNB_Msk (0x3FUL << HSP_CAPDR_ALT_PFCTNB_Pos) /*!< 0x0003F0000 */ +#define HSP_CAPDR_ALT_PFCTNB HSP_CAPDR_TSTAMP_Msk /*!< Processing Function Number */ +#define HSP_CAPDR_ALT_IFCNT_Pos (22UL) +#define HSP_CAPDR_ALT_IFCNT_Msk (0xFUL << HSP_CAPDR_ALT_IFCNT_Pos) /*!< 0x03C00000 */ +#define HSP_CAPDR_ALT_IFCNT HSP_CAPDR_IFCNT_Msk /*!< IF instruction counter */ +#define HSP_CAPDR_ALT_TSKNB_Pos (26UL) +#define HSP_CAPDR_ALT_TSKNB_Msk (0x3FUL << HSP_CAPDR_ALT_TSKNB_Pos) /*!< 0xFC000000 */ +#define HSP_CAPDR_ALT_TSKNB HSP_CAPDR_TSKNB_Msk /*!< Last captured task number */ /******************** Bit definition for HSP_CAPCR register ********************/ -/*!< CAPMOD configuration */ -#define HSP_CAPCR_CAPMOD_Pos (0U) +#define HSP_CAPCR_CAPMOD_Pos (0UL) #define HSP_CAPCR_CAPMOD_Msk (0x3UL << HSP_CAPCR_CAPMOD_Pos) /*!< 0x00000003 */ #define HSP_CAPCR_CAPMOD HSP_CAPCR_CAPMOD_Msk /*!< CAPMOD[1:0] bits (Capture mode ) */ #define HSP_CAPCR_CAPMOD_0 (0x1UL << HSP_CAPCR_CAPMOD_Pos) /*!< 0x00000001 */ #define HSP_CAPCR_CAPMOD_1 (0x2UL << HSP_CAPCR_CAPMOD_Pos) /*!< 0x00000002 */ -/*!< FRCNTEN configuration */ -#define HSP_CAPCR_FRCNTEN_Pos (2U) + +#define HSP_CAPCR_FRCNTEN_Pos (2UL) #define HSP_CAPCR_FRCNTEN_Msk (0x1UL << HSP_CAPCR_FRCNTEN_Pos) /*!< 0x00000004 */ #define HSP_CAPCR_FRCNTEN HSP_CAPCR_FRCNTEN_Msk /*!< FRCNTEN (Free-running counter enable ) */ -/*!< PRESC configuration */ -#define HSP_CAPCR_PRESC_Pos (4U) + +#define HSP_CAPCR_PRESC_Pos (4UL) #define HSP_CAPCR_PRESC_Msk (0x1FUL << HSP_CAPCR_PRESC_Pos) /*!< 0x000001F0 */ #define HSP_CAPCR_PRESC HSP_CAPCR_PRESC_Msk /*!< PRESC[4:0] bits (Time-stamp prescaler value ) */ #define HSP_CAPCR_PRESC_0 (0x01UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000010 */ @@ -13239,174 +13811,171 @@ typedef struct #define HSP_CAPCR_PRESC_2 (0x04UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000040 */ #define HSP_CAPCR_PRESC_3 (0x08UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000080 */ #define HSP_CAPCR_PRESC_4 (0x10UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000100 */ -/*!< TSKFLT configuration */ -#define HSP_CAPCR_TSKFLT_Pos (12U) + +#define HSP_CAPCR_TSKFLT_Pos (12UL) #define HSP_CAPCR_TSKFLT_Msk (0x1UL << HSP_CAPCR_TSKFLT_Pos) /*!< 0x00001000 */ #define HSP_CAPCR_TSKFLT HSP_CAPCR_TSKFLT_Msk /*!< TSKFLT (Task filter enable (1)) */ -/*!< CCNTREN configuration */ -#define HSP_CAPCR_CCNTREN_Pos (16U) + +#define HSP_CAPCR_CCNTREN_Pos (16UL) #define HSP_CAPCR_CCNTREN_Msk (0x1UL << HSP_CAPCR_CCNTREN_Pos) /*!< 0x00010000 */ #define HSP_CAPCR_CCNTREN HSP_CAPCR_CCNTREN_Msk /*!< CCNTREN (Conflict counter enable ) */ /******************** Bit definition for HSP_ERR_IER register ********************/ -/*!< TRGIOVRIE configuration */ -#define HSP_ERR_IER_TRGIOVRIE_Pos (8U) +#define HSP_ERR_IER_TRGIOVRIE_Pos (8UL) #define HSP_ERR_IER_TRGIOVRIE_Msk (0x1UL << HSP_ERR_IER_TRGIOVRIE_Pos) /*!< 0x00000100 */ #define HSP_ERR_IER_TRGIOVRIE HSP_ERR_IER_TRGIOVRIE_Msk /*!< TRGIOVRIE (TRGITF overrun interrupt enable) */ -/*!< B0ERRIE configuration */ -#define HSP_ERR_IER_B0ERRIE_Pos (12U) + +#define HSP_ERR_IER_B0ERRIE_Pos (12UL) #define HSP_ERR_IER_B0ERRIE_Msk (0x1UL << HSP_ERR_IER_B0ERRIE_Pos) /*!< 0x00001000 */ #define HSP_ERR_IER_B0ERRIE HSP_ERR_IER_B0ERRIE_Msk /*!< B0ERRIE (H2CBUFF0 underrun or C2HBUFF0 overrun interrupt enable) */ -/*!< B1ERRIE configuration */ -#define HSP_ERR_IER_B1ERRIE_Pos (13U) + +#define HSP_ERR_IER_B1ERRIE_Pos (13UL) #define HSP_ERR_IER_B1ERRIE_Msk (0x1UL << HSP_ERR_IER_B1ERRIE_Pos) /*!< 0x00002000 */ #define HSP_ERR_IER_B1ERRIE HSP_ERR_IER_B1ERRIE_Msk /*!< B1ERRIE (H2CBUFF1 underrun or C2HBUFF1 overrun interrupt enable) */ -/*!< B2ERRIE configuration */ -#define HSP_ERR_IER_B2ERRIE_Pos (14U) + +#define HSP_ERR_IER_B2ERRIE_Pos (14UL) #define HSP_ERR_IER_B2ERRIE_Msk (0x1UL << HSP_ERR_IER_B2ERRIE_Pos) /*!< 0x00004000 */ #define HSP_ERR_IER_B2ERRIE HSP_ERR_IER_B2ERRIE_Msk /*!< B2ERRIE (H2CBUFF2 underrun or C2HBUFF2 overrun interrupt enable) */ -/*!< B3ERRIE configuration */ -#define HSP_ERR_IER_B3ERRIE_Pos (15U) + +#define HSP_ERR_IER_B3ERRIE_Pos (15UL) #define HSP_ERR_IER_B3ERRIE_Msk (0x1UL << HSP_ERR_IER_B3ERRIE_Pos) /*!< 0x00008000 */ #define HSP_ERR_IER_B3ERRIE HSP_ERR_IER_B3ERRIE_Msk /*!< B3ERRIE (H2CBUFF3 underrun or C2HBUFF3 overrun interrupt enable) */ -/*!< CAPOVRIE configuration */ -#define HSP_ERR_IER_CAPOVRIE_Pos (16U) + +#define HSP_ERR_IER_CAPOVRIE_Pos (16UL) #define HSP_ERR_IER_CAPOVRIE_Msk (0x1UL << HSP_ERR_IER_CAPOVRIE_Pos) /*!< 0x00010000 */ #define HSP_ERR_IER_CAPOVRIE HSP_ERR_IER_CAPOVRIE_Msk /*!< CAPOVRIE (Capture register overrun interrupt enable) */ -/*!< FWERRIE configuration */ -#define HSP_ERR_IER_FWERRIE_Pos (17U) + +#define HSP_ERR_IER_FWERRIE_Pos (17UL) #define HSP_ERR_IER_FWERRIE_Msk (0x1UL << HSP_ERR_IER_FWERRIE_Pos) /*!< 0x00020000 */ #define HSP_ERR_IER_FWERRIE HSP_ERR_IER_FWERRIE_Msk /*!< FWERRIE (Firmware error interrupt enable) */ -/*!< SCHERRIE configuration */ -#define HSP_ERR_IER_SCHERRIE_Pos (18U) + +#define HSP_ERR_IER_SCHERRIE_Pos (18UL) #define HSP_ERR_IER_SCHERRIE_Msk (0x1UL << HSP_ERR_IER_SCHERRIE_Pos) /*!< 0x00040000 */ #define HSP_ERR_IER_SCHERRIE HSP_ERR_IER_SCHERRIE_Msk /*!< SCHERRIE (Scheduler error interrupt enable) */ -/*!< BKINIE configuration */ -#define HSP_ERR_IER_BKINIE_Pos (19U) + +#define HSP_ERR_IER_BKINIE_Pos (19UL) #define HSP_ERR_IER_BKINIE_Msk (0x1UL << HSP_ERR_IER_BKINIE_Pos) /*!< 0x00080000 */ #define HSP_ERR_IER_BKINIE HSP_ERR_IER_BKINIE_Msk /*!< BKINIE (Break input interrupt enable) */ -/*!< HDEGOVRIE configuration */ -#define HSP_ERR_IER_HDEGOVRIE_Pos (20U) + +#define HSP_ERR_IER_HDEGOVRIE_Pos (20UL) #define HSP_ERR_IER_HDEGOVRIE_Msk (0x1UL << HSP_ERR_IER_HDEGOVRIE_Pos) /*!< 0x00100000 */ #define HSP_ERR_IER_HDEGOVRIE HSP_ERR_IER_HDEGOVRIE_Msk /*!< HDEGOVRIE (SPE event overrun interrupt enable) */ -/*!< OPCOERRIE configuration */ -#define HSP_ERR_IER_OPCOERRIE_Pos (22U) + +#define HSP_ERR_IER_OPCOERRIE_Pos (22UL) #define HSP_ERR_IER_OPCOERRIE_Msk (0x1UL << HSP_ERR_IER_OPCOERRIE_Pos) /*!< 0x00400000 */ #define HSP_ERR_IER_OPCOERRIE HSP_ERR_IER_OPCOERRIE_Msk /*!< OPCOERRIE (Invalid Op. code error interrupt enable) */ -/*!< ACCERRIE configuration */ -#define HSP_ERR_IER_ACCERRIE_Pos (23U) + +#define HSP_ERR_IER_ACCERRIE_Pos (23UL) #define HSP_ERR_IER_ACCERRIE_Msk (0x1UL << HSP_ERR_IER_ACCERRIE_Pos) /*!< 0x00800000 */ #define HSP_ERR_IER_ACCERRIE HSP_ERR_IER_ACCERRIE_Msk /*!< ACCERRIE (SPE access error interrupt enable) */ -/*!< UDFIE configuration */ -#define HSP_ERR_IER_UDFIE_Pos (24U) + +#define HSP_ERR_IER_UDFIE_Pos (24UL) #define HSP_ERR_IER_UDFIE_Msk (0x1UL << HSP_ERR_IER_UDFIE_Pos) /*!< 0x01000000 */ #define HSP_ERR_IER_UDFIE HSP_ERR_IER_UDFIE_Msk /*!< UDFIE (FPU Underflow exception interrupt enable) */ -/*!< OVFIE configuration */ -#define HSP_ERR_IER_OVFIE_Pos (25U) + +#define HSP_ERR_IER_OVFIE_Pos (25UL) #define HSP_ERR_IER_OVFIE_Msk (0x1UL << HSP_ERR_IER_OVFIE_Pos) /*!< 0x02000000 */ #define HSP_ERR_IER_OVFIE HSP_ERR_IER_OVFIE_Msk /*!< OVFIE (FPU Overflow exception interrupt enable) */ -/*!< DBZIE configuration */ -#define HSP_ERR_IER_DBZIE_Pos (26U) + +#define HSP_ERR_IER_DBZIE_Pos (26UL) #define HSP_ERR_IER_DBZIE_Msk (0x1UL << HSP_ERR_IER_DBZIE_Pos) /*!< 0x04000000 */ #define HSP_ERR_IER_DBZIE HSP_ERR_IER_DBZIE_Msk /*!< DBZIE (FPU division-by-zero exception interrupt enable) */ -/*!< INVIE configuration */ -#define HSP_ERR_IER_INVIE_Pos (27U) + +#define HSP_ERR_IER_INVIE_Pos (27UL) #define HSP_ERR_IER_INVIE_Msk (0x1UL << HSP_ERR_IER_INVIE_Pos) /*!< 0x08000000 */ #define HSP_ERR_IER_INVIE HSP_ERR_IER_INVIE_Msk /*!< INVIE (FPU Invalid exception interrupt enable) */ -/*!< DENORMIE configuration */ -#define HSP_ERR_IER_DENORMIE_Pos (28U) + +#define HSP_ERR_IER_DENORMIE_Pos (28UL) #define HSP_ERR_IER_DENORMIE_Msk (0x1UL << HSP_ERR_IER_DENORMIE_Pos) /*!< 0x10000000 */ #define HSP_ERR_IER_DENORMIE HSP_ERR_IER_DENORMIE_Msk /*!< DENORMIE (FPU denormal interrupt enable) */ /******************** Bit definition for HSP_EVT_IER register ********************/ -/*!< H2CMRDYIE configuration */ -#define HSP_EVT_IER_H2CMRDYIE_Pos (0U) +#define HSP_EVT_IER_H2CMRDYIE_Pos (0UL) #define HSP_EVT_IER_H2CMRDYIE_Msk (0x1UL << HSP_EVT_IER_H2CMRDYIE_Pos) /*!< 0x00000001 */ #define HSP_EVT_IER_H2CMRDYIE HSP_EVT_IER_H2CMRDYIE_Msk /*!< H2CMRDYIE (HSP to CPU message ready interrupt enable) */ -/*!< C2HMFREEIE configuration */ -#define HSP_EVT_IER_C2HMFREEIE_Pos (1U) + +#define HSP_EVT_IER_C2HMFREEIE_Pos (1UL) #define HSP_EVT_IER_C2HMFREEIE_Msk (0x1UL << HSP_EVT_IER_C2HMFREEIE_Pos) /*!< 0x00000002 */ #define HSP_EVT_IER_C2HMFREEIE HSP_EVT_IER_C2HMFREEIE_Msk /*!< C2HMFREEIE (CPU to HSP message box free interrupt enable) */ -/*!< DCDONEIE configuration */ -#define HSP_EVT_IER_DCDONEIE_Pos (2U) + +#define HSP_EVT_IER_DCDONEIE_Pos (2UL) #define HSP_EVT_IER_DCDONEIE_Msk (0x1UL << HSP_EVT_IER_DCDONEIE_Pos) /*!< 0x00000004 */ #define HSP_EVT_IER_DCDONEIE HSP_EVT_IER_DCDONEIE_Msk /*!< DCDONEIE (Direct command done interrupt enable) */ -/*!< CAPRDYIE configuration */ -#define HSP_EVT_IER_CAPRDYIE_Pos (4U) + +#define HSP_EVT_IER_CAPRDYIE_Pos (4UL) #define HSP_EVT_IER_CAPRDYIE_Msk (0x1UL << HSP_EVT_IER_CAPRDYIE_Pos) /*!< 0x00000010 */ #define HSP_EVT_IER_CAPRDYIE HSP_EVT_IER_CAPRDYIE_Msk /*!< CAPRDYIE (Capture buffer data ready interrupt enable) */ -/*!< CDEGRDYIE configuration */ -#define HSP_EVT_IER_CDEGRDYIE_Pos (7U) + +#define HSP_EVT_IER_CDEGRDYIE_Pos (7UL) #define HSP_EVT_IER_CDEGRDYIE_Msk (0x1UL << HSP_EVT_IER_CDEGRDYIE_Pos) /*!< 0x00000080 */ #define HSP_EVT_IER_CDEGRDYIE HSP_EVT_IER_CDEGRDYIE_Msk /*!< CDEGRDYIE (CPU Dedicated event generator ready interrupt enable) */ -/*!< SOFWFEIE configuration */ -#define HSP_EVT_IER_SOFWFEIE_Pos (8U) + +#define HSP_EVT_IER_SOFWFEIE_Pos (8UL) #define HSP_EVT_IER_SOFWFEIE_Msk (0x1UL << HSP_EVT_IER_SOFWFEIE_Pos) /*!< 0x00000100 */ #define HSP_EVT_IER_SOFWFEIE HSP_EVT_IER_SOFWFEIE_Msk /*!< SOFWFEIE (Start of WFE interrupt enable) */ -/*!< EOFWFEIE configuration */ -#define HSP_EVT_IER_EOFWFEIE_Pos (9U) + +#define HSP_EVT_IER_EOFWFEIE_Pos (9UL) #define HSP_EVT_IER_EOFWFEIE_Msk (0x1UL << HSP_EVT_IER_EOFWFEIE_Pos) /*!< 0x00000200 */ #define HSP_EVT_IER_EOFWFEIE HSP_EVT_IER_EOFWFEIE_Msk /*!< EOFWFEIE (End of WFE interrupt enable) */ -/*!< B0EVTIE configuration */ -#define HSP_EVT_IER_B0EVTIE_Pos (12U) + +#define HSP_EVT_IER_B0EVTIE_Pos (12UL) #define HSP_EVT_IER_B0EVTIE_Msk (0x1UL << HSP_EVT_IER_B0EVTIE_Pos) /*!< 0x00001000 */ #define HSP_EVT_IER_B0EVTIE HSP_EVT_IER_B0EVTIE_Msk /*!< B0EVTIE (BUFF0 event interrupt enable) */ -/*!< B1EVTIE configuration */ -#define HSP_EVT_IER_B1EVTIE_Pos (13U) + +#define HSP_EVT_IER_B1EVTIE_Pos (13UL) #define HSP_EVT_IER_B1EVTIE_Msk (0x1UL << HSP_EVT_IER_B1EVTIE_Pos) /*!< 0x00002000 */ #define HSP_EVT_IER_B1EVTIE HSP_EVT_IER_B1EVTIE_Msk /*!< B1EVTIE (BUFF1 event interrupt enable) */ -/*!< B2EVTIE configuration */ -#define HSP_EVT_IER_B2EVTIE_Pos (14U) + +#define HSP_EVT_IER_B2EVTIE_Pos (14UL) #define HSP_EVT_IER_B2EVTIE_Msk (0x1UL << HSP_EVT_IER_B2EVTIE_Pos) /*!< 0x00004000 */ #define HSP_EVT_IER_B2EVTIE HSP_EVT_IER_B2EVTIE_Msk /*!< B2EVTIE (BUFF2 event interrupt enable) */ -/*!< B3EVTIE configuration */ -#define HSP_EVT_IER_B3EVTIE_Pos (15U) + +#define HSP_EVT_IER_B3EVTIE_Pos (15UL) #define HSP_EVT_IER_B3EVTIE_Msk (0x1UL << HSP_EVT_IER_B3EVTIE_Pos) /*!< 0x00008000 */ #define HSP_EVT_IER_B3EVTIE HSP_EVT_IER_B3EVTIE_Msk /*!< B3EVTIE (BUFF3 event interrupt enable) */ -/*!< SOTECP0IE configuration */ -#define HSP_EVT_IER_SOTECP0IE_Pos (16U) + +#define HSP_EVT_IER_SOTECP0IE_Pos (16UL) #define HSP_EVT_IER_SOTECP0IE_Msk (0x1UL << HSP_EVT_IER_SOTECP0IE_Pos) /*!< 0x00010000 */ #define HSP_EVT_IER_SOTECP0IE HSP_EVT_IER_SOTECP0IE_Msk /*!< SOTECP0IE (Start of task generated by event comparator 0 interrupt enable) */ -/*!< SOTECP1IE configuration */ -#define HSP_EVT_IER_SOTECP1IE_Pos (17U) + +#define HSP_EVT_IER_SOTECP1IE_Pos (17UL) #define HSP_EVT_IER_SOTECP1IE_Msk (0x1UL << HSP_EVT_IER_SOTECP1IE_Pos) /*!< 0x00020000 */ #define HSP_EVT_IER_SOTECP1IE HSP_EVT_IER_SOTECP1IE_Msk /*!< SOTECP1IE (Start of task generated by event comparator 1 interrupt enable) */ -/*!< SOTECP2IE configuration */ -#define HSP_EVT_IER_SOTECP2IE_Pos (18U) + +#define HSP_EVT_IER_SOTECP2IE_Pos (18UL) #define HSP_EVT_IER_SOTECP2IE_Msk (0x1UL << HSP_EVT_IER_SOTECP2IE_Pos) /*!< 0x00040000 */ #define HSP_EVT_IER_SOTECP2IE HSP_EVT_IER_SOTECP2IE_Msk /*!< SOTECP2IE (Start of task generated by event comparator 2 interrupt enable) */ -/*!< SOTECP3IE configuration */ -#define HSP_EVT_IER_SOTECP3IE_Pos (19U) + +#define HSP_EVT_IER_SOTECP3IE_Pos (19UL) #define HSP_EVT_IER_SOTECP3IE_Msk (0x1UL << HSP_EVT_IER_SOTECP3IE_Pos) /*!< 0x00080000 */ #define HSP_EVT_IER_SOTECP3IE HSP_EVT_IER_SOTECP3IE_Msk /*!< SOTECP3IE (Start of task generated by event comparator 3 interrupt enable) */ -/*!< EOTECP0IE configuration */ -#define HSP_EVT_IER_EOTECP0IE_Pos (20U) + +#define HSP_EVT_IER_EOTECP0IE_Pos (20UL) #define HSP_EVT_IER_EOTECP0IE_Msk (0x1UL << HSP_EVT_IER_EOTECP0IE_Pos) /*!< 0x00100000 */ #define HSP_EVT_IER_EOTECP0IE HSP_EVT_IER_EOTECP0IE_Msk /*!< EOTECP0IE (End of task generated by event comparator 0 interrupt enable) */ -/*!< EOTECP1IE configuration */ -#define HSP_EVT_IER_EOTECP1IE_Pos (21U) + +#define HSP_EVT_IER_EOTECP1IE_Pos (21UL) #define HSP_EVT_IER_EOTECP1IE_Msk (0x1UL << HSP_EVT_IER_EOTECP1IE_Pos) /*!< 0x00200000 */ #define HSP_EVT_IER_EOTECP1IE HSP_EVT_IER_EOTECP1IE_Msk /*!< EOTECP1IE (End of task generated by event comparator 1 interrupt enable) */ -/*!< EOTECP2IE configuration */ -#define HSP_EVT_IER_EOTECP2IE_Pos (22U) + +#define HSP_EVT_IER_EOTECP2IE_Pos (22UL) #define HSP_EVT_IER_EOTECP2IE_Msk (0x1UL << HSP_EVT_IER_EOTECP2IE_Pos) /*!< 0x00400000 */ #define HSP_EVT_IER_EOTECP2IE HSP_EVT_IER_EOTECP2IE_Msk /*!< EOTECP2IE (End of task generated by event comparator 2 interrupt enable) */ -/*!< EOTECP3IE configuration */ -#define HSP_EVT_IER_EOTECP3IE_Pos (23U) + +#define HSP_EVT_IER_EOTECP3IE_Pos (23UL) #define HSP_EVT_IER_EOTECP3IE_Msk (0x1UL << HSP_EVT_IER_EOTECP3IE_Pos) /*!< 0x00800000 */ #define HSP_EVT_IER_EOTECP3IE HSP_EVT_IER_EOTECP3IE_Msk /*!< EOTECP3IE (End of task generated by event comparator 3 interrupt enable) */ -/*!< TOVLPIE configuration */ -#define HSP_EVT_IER_TOVLPIE_Pos (28U) + +#define HSP_EVT_IER_TOVLPIE_Pos (28UL) #define HSP_EVT_IER_TOVLPIE_Msk (0x1UL << HSP_EVT_IER_TOVLPIE_Pos) /*!< 0x10000000 */ #define HSP_EVT_IER_TOVLPIE HSP_EVT_IER_TOVLPIE_Msk /*!< TOVLPIE (Task overlap flag interrupt enable) */ -/*!< FPUSATIE configuration */ -#define HSP_EVT_IER_FPUSATIE_Pos (31U) + +#define HSP_EVT_IER_FPUSATIE_Pos (31UL) #define HSP_EVT_IER_FPUSATIE_Msk (0x1UL << HSP_EVT_IER_FPUSATIE_Pos) /*!< 0x80000000 */ #define HSP_EVT_IER_FPUSATIE HSP_EVT_IER_FPUSATIE_Msk /*!< FPUSATIE (Saturation flag interrupt enable) */ /******************** Bit definition for HSP_PFCTEVT_IER register ********************/ -/*!< PFCTIE configuration */ -#define HSP_PFCTEVT_IER_PFCTIE_Pos (0U) +#define HSP_PFCTEVT_IER_PFCTIE_Pos (0UL) #define HSP_PFCTEVT_IER_PFCTIE_Msk (0xFFFFFFFFUL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0xFFFFFFFF */ #define HSP_PFCTEVT_IER_PFCTIE HSP_PFCTEVT_IER_PFCTIE_Msk /*!< PFCTIE[31:0] bits (Processing function flags interrupt enable) */ #define HSP_PFCTEVT_IER_PFCTIE_0 (0x00001UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000001 */ @@ -13443,148 +14012,145 @@ typedef struct #define HSP_PFCTEVT_IER_PFCTIE_31 (0x80000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_ERR_ISR register ********************/ -/*!< TRGIOVRF configuration */ -#define HSP_ERR_ISR_TRGIOVRF_Pos (8U) +#define HSP_ERR_ISR_TRGIOVRF_Pos (8UL) #define HSP_ERR_ISR_TRGIOVRF_Msk (0x1UL << HSP_ERR_ISR_TRGIOVRF_Pos) /*!< 0x00000100 */ #define HSP_ERR_ISR_TRGIOVRF HSP_ERR_ISR_TRGIOVRF_Msk /*!< TRGIOVRF (TRGITF overrun flag) */ -/*!< B0ERRF configuration */ -#define HSP_ERR_ISR_B0ERRF_Pos (12U) + +#define HSP_ERR_ISR_B0ERRF_Pos (12UL) #define HSP_ERR_ISR_B0ERRF_Msk (0x1UL << HSP_ERR_ISR_B0ERRF_Pos) /*!< 0x00001000 */ #define HSP_ERR_ISR_B0ERRF HSP_ERR_ISR_B0ERRF_Msk /*!< B0ERRF (H2CBUFF0 underrun or C2HBUFF0 overrun flag) */ -/*!< B1ERRF configuration */ -#define HSP_ERR_ISR_B1ERRF_Pos (13U) + +#define HSP_ERR_ISR_B1ERRF_Pos (13UL) #define HSP_ERR_ISR_B1ERRF_Msk (0x1UL << HSP_ERR_ISR_B1ERRF_Pos) /*!< 0x00002000 */ #define HSP_ERR_ISR_B1ERRF HSP_ERR_ISR_B1ERRF_Msk /*!< B1ERRF (H2CBUFF1 underrun or C2HBUFF1 overrun flag) */ -/*!< B2ERRF configuration */ -#define HSP_ERR_ISR_B2ERRF_Pos (14U) + +#define HSP_ERR_ISR_B2ERRF_Pos (14UL) #define HSP_ERR_ISR_B2ERRF_Msk (0x1UL << HSP_ERR_ISR_B2ERRF_Pos) /*!< 0x00004000 */ #define HSP_ERR_ISR_B2ERRF HSP_ERR_ISR_B2ERRF_Msk /*!< B2ERRF (H2CBUFF2 underrun or C2HBUFF2 overrun flag) */ -/*!< B3ERRF configuration */ -#define HSP_ERR_ISR_B3ERRF_Pos (15U) + +#define HSP_ERR_ISR_B3ERRF_Pos (15UL) #define HSP_ERR_ISR_B3ERRF_Msk (0x1UL << HSP_ERR_ISR_B3ERRF_Pos) /*!< 0x00008000 */ #define HSP_ERR_ISR_B3ERRF HSP_ERR_ISR_B3ERRF_Msk /*!< B3ERRF (H2CBUFF3 underrun or C2HBUFF3 overrun flag) */ -/*!< CAPOVRF configuration */ -#define HSP_ERR_ISR_CAPOVRF_Pos (16U) + +#define HSP_ERR_ISR_CAPOVRF_Pos (16UL) #define HSP_ERR_ISR_CAPOVRF_Msk (0x1UL << HSP_ERR_ISR_CAPOVRF_Pos) /*!< 0x00010000 */ #define HSP_ERR_ISR_CAPOVRF HSP_ERR_ISR_CAPOVRF_Msk /*!< CAPOVRF (Capture register overrun flag) */ -/*!< FWERRF configuration */ -#define HSP_ERR_ISR_FWERRF_Pos (17U) + +#define HSP_ERR_ISR_FWERRF_Pos (17UL) #define HSP_ERR_ISR_FWERRF_Msk (0x1UL << HSP_ERR_ISR_FWERRF_Pos) /*!< 0x00020000 */ #define HSP_ERR_ISR_FWERRF HSP_ERR_ISR_FWERRF_Msk /*!< FWERRF (Firmware error flag) */ -/*!< SCHERRF configuration */ -#define HSP_ERR_ISR_SCHERRF_Pos (18U) + +#define HSP_ERR_ISR_SCHERRF_Pos (18UL) #define HSP_ERR_ISR_SCHERRF_Msk (0x1UL << HSP_ERR_ISR_SCHERRF_Pos) /*!< 0x00040000 */ #define HSP_ERR_ISR_SCHERRF HSP_ERR_ISR_SCHERRF_Msk /*!< SCHERRF (Scheduler error flag) */ -/*!< BKINF configuration */ -#define HSP_ERR_ISR_BKINF_Pos (19U) + +#define HSP_ERR_ISR_BKINF_Pos (19UL) #define HSP_ERR_ISR_BKINF_Msk (0x1UL << HSP_ERR_ISR_BKINF_Pos) /*!< 0x00080000 */ #define HSP_ERR_ISR_BKINF HSP_ERR_ISR_BKINF_Msk /*!< BKINF (Break input flag) */ -/*!< HDEGOVRF configuration */ -#define HSP_ERR_ISR_HDEGOVRF_Pos (20U) + +#define HSP_ERR_ISR_HDEGOVRF_Pos (20UL) #define HSP_ERR_ISR_HDEGOVRF_Msk (0x1UL << HSP_ERR_ISR_HDEGOVRF_Pos) /*!< 0x00100000 */ #define HSP_ERR_ISR_HDEGOVRF HSP_ERR_ISR_HDEGOVRF_Msk /*!< HDEGOVRF (SPE event overrun flag) */ -/*!< OPCOERRF configuration */ -#define HSP_ERR_ISR_OPCOERRF_Pos (22U) + +#define HSP_ERR_ISR_OPCOERRF_Pos (22UL) #define HSP_ERR_ISR_OPCOERRF_Msk (0x1UL << HSP_ERR_ISR_OPCOERRF_Pos) /*!< 0x00400000 */ #define HSP_ERR_ISR_OPCOERRF HSP_ERR_ISR_OPCOERRF_Msk /*!< OPCOERRF (Invalid OpCode error flag) */ -/*!< ACCERRF configuration */ -#define HSP_ERR_ISR_ACCERRF_Pos (23U) + +#define HSP_ERR_ISR_ACCERRF_Pos (23UL) #define HSP_ERR_ISR_ACCERRF_Msk (0x1UL << HSP_ERR_ISR_ACCERRF_Pos) /*!< 0x00800000 */ #define HSP_ERR_ISR_ACCERRF HSP_ERR_ISR_ACCERRF_Msk /*!< ACCERRF (SPE Access error flag) */ -/*!< FPUERRF configuration */ -#define HSP_ERR_ISR_FPUERRF_Pos (24U) + +#define HSP_ERR_ISR_FPUERRF_Pos (24UL) #define HSP_ERR_ISR_FPUERRF_Msk (0x1UL << HSP_ERR_ISR_FPUERRF_Pos) /*!< 0x01000000 */ #define HSP_ERR_ISR_FPUERRF HSP_ERR_ISR_FPUERRF_Msk /*!< FPUERRF (Computation error flag) */ /******************** Bit definition for HSP_EVT_ISR register ********************/ -/*!< H2CMRDYF configuration */ -#define HSP_EVT_ISR_H2CMRDYF_Pos (0U) +#define HSP_EVT_ISR_H2CMRDYF_Pos (0UL) #define HSP_EVT_ISR_H2CMRDYF_Msk (0x1UL << HSP_EVT_ISR_H2CMRDYF_Pos) /*!< 0x00000001 */ #define HSP_EVT_ISR_H2CMRDYF HSP_EVT_ISR_H2CMRDYF_Msk /*!< H2CMRDYF (HSP to CPU message ready flag) */ -/*!< C2HMFREEF configuration */ -#define HSP_EVT_ISR_C2HMFREEF_Pos (1U) + +#define HSP_EVT_ISR_C2HMFREEF_Pos (1UL) #define HSP_EVT_ISR_C2HMFREEF_Msk (0x1UL << HSP_EVT_ISR_C2HMFREEF_Pos) /*!< 0x00000002 */ #define HSP_EVT_ISR_C2HMFREEF HSP_EVT_ISR_C2HMFREEF_Msk /*!< C2HMFREEF (CPU to HSP message box free flag) */ -/*!< DCDONEF configuration */ -#define HSP_EVT_ISR_DCDONEF_Pos (2U) + +#define HSP_EVT_ISR_DCDONEF_Pos (2UL) #define HSP_EVT_ISR_DCDONEF_Msk (0x1UL << HSP_EVT_ISR_DCDONEF_Pos) /*!< 0x00000004 */ #define HSP_EVT_ISR_DCDONEF HSP_EVT_ISR_DCDONEF_Msk /*!< DCDONEF (Direct command done flag) */ -/*!< CAPRDYF configuration */ -#define HSP_EVT_ISR_CAPRDYF_Pos (4U) + +#define HSP_EVT_ISR_CAPRDYF_Pos (4UL) #define HSP_EVT_ISR_CAPRDYF_Msk (0x1UL << HSP_EVT_ISR_CAPRDYF_Pos) /*!< 0x00000010 */ #define HSP_EVT_ISR_CAPRDYF HSP_EVT_ISR_CAPRDYF_Msk /*!< CAPRDYF (Capture buffer data ready flag) */ -/*!< CDEGRDYF configuration */ -#define HSP_EVT_ISR_CDEGRDYF_Pos (7U) + +#define HSP_EVT_ISR_CDEGRDYF_Pos (7UL) #define HSP_EVT_ISR_CDEGRDYF_Msk (0x1UL << HSP_EVT_ISR_CDEGRDYF_Pos) /*!< 0x00000080 */ #define HSP_EVT_ISR_CDEGRDYF HSP_EVT_ISR_CDEGRDYF_Msk /*!< CDEGRDYF (CPU Dedicated event generator ready flag) */ -/*!< SOFWFEF configuration */ -#define HSP_EVT_ISR_SOFWFEF_Pos (8U) + +#define HSP_EVT_ISR_SOFWFEF_Pos (8UL) #define HSP_EVT_ISR_SOFWFEF_Msk (0x1UL << HSP_EVT_ISR_SOFWFEF_Pos) /*!< 0x00000100 */ #define HSP_EVT_ISR_SOFWFEF HSP_EVT_ISR_SOFWFEF_Msk /*!< SOFWFEF (Start of WFE flag) */ -/*!< EOFWFEF configuration */ -#define HSP_EVT_ISR_EOFWFEF_Pos (9U) + +#define HSP_EVT_ISR_EOFWFEF_Pos (9UL) #define HSP_EVT_ISR_EOFWFEF_Msk (0x1UL << HSP_EVT_ISR_EOFWFEF_Pos) /*!< 0x00000200 */ #define HSP_EVT_ISR_EOFWFEF HSP_EVT_ISR_EOFWFEF_Msk /*!< EOFWFEF (End of WFE flag) */ -/*!< B0EVTF configuration */ -#define HSP_EVT_ISR_B0EVTF_Pos (12U) + +#define HSP_EVT_ISR_B0EVTF_Pos (12UL) #define HSP_EVT_ISR_B0EVTF_Msk (0x1UL << HSP_EVT_ISR_B0EVTF_Pos) /*!< 0x00001000 */ #define HSP_EVT_ISR_B0EVTF HSP_EVT_ISR_B0EVTF_Msk /*!< B0EVTF (BUFF0 event flag) */ -/*!< B1EVTF configuration */ -#define HSP_EVT_ISR_B1EVTF_Pos (13U) + +#define HSP_EVT_ISR_B1EVTF_Pos (13UL) #define HSP_EVT_ISR_B1EVTF_Msk (0x1UL << HSP_EVT_ISR_B1EVTF_Pos) /*!< 0x00002000 */ #define HSP_EVT_ISR_B1EVTF HSP_EVT_ISR_B1EVTF_Msk /*!< B1EVTF (BUFF1 event flag) */ -/*!< B2EVTF configuration */ -#define HSP_EVT_ISR_B2EVTF_Pos (14U) + +#define HSP_EVT_ISR_B2EVTF_Pos (14UL) #define HSP_EVT_ISR_B2EVTF_Msk (0x1UL << HSP_EVT_ISR_B2EVTF_Pos) /*!< 0x00004000 */ #define HSP_EVT_ISR_B2EVTF HSP_EVT_ISR_B2EVTF_Msk /*!< B2EVTF (BUFF2 event flag) */ -/*!< B3EVTF configuration */ -#define HSP_EVT_ISR_B3EVTF_Pos (15U) + +#define HSP_EVT_ISR_B3EVTF_Pos (15UL) #define HSP_EVT_ISR_B3EVTF_Msk (0x1UL << HSP_EVT_ISR_B3EVTF_Pos) /*!< 0x00008000 */ #define HSP_EVT_ISR_B3EVTF HSP_EVT_ISR_B3EVTF_Msk /*!< B3EVTF (BUFF3 event flag) */ -/*!< SOTECP0F configuration */ -#define HSP_EVT_ISR_SOTECP0F_Pos (16U) + +#define HSP_EVT_ISR_SOTECP0F_Pos (16UL) #define HSP_EVT_ISR_SOTECP0F_Msk (0x1UL << HSP_EVT_ISR_SOTECP0F_Pos) /*!< 0x00010000 */ #define HSP_EVT_ISR_SOTECP0F HSP_EVT_ISR_SOTECP0F_Msk /*!< SOTECP0F (Start of task flag, for event comparator 0) */ -/*!< SOTECP1F configuration */ -#define HSP_EVT_ISR_SOTECP1F_Pos (17U) + +#define HSP_EVT_ISR_SOTECP1F_Pos (17UL) #define HSP_EVT_ISR_SOTECP1F_Msk (0x1UL << HSP_EVT_ISR_SOTECP1F_Pos) /*!< 0x00020000 */ #define HSP_EVT_ISR_SOTECP1F HSP_EVT_ISR_SOTECP1F_Msk /*!< SOTECP1F (Start of task flag, for event comparator 1) */ -/*!< SOTECP2F configuration */ -#define HSP_EVT_ISR_SOTECP2F_Pos (18U) + +#define HSP_EVT_ISR_SOTECP2F_Pos (18UL) #define HSP_EVT_ISR_SOTECP2F_Msk (0x1UL << HSP_EVT_ISR_SOTECP2F_Pos) /*!< 0x00040000 */ #define HSP_EVT_ISR_SOTECP2F HSP_EVT_ISR_SOTECP2F_Msk /*!< SOTECP2F (Start of task flag, for event comparator 2) */ -/*!< SOTECP3F configuration */ -#define HSP_EVT_ISR_SOTECP3F_Pos (19U) + +#define HSP_EVT_ISR_SOTECP3F_Pos (19UL) #define HSP_EVT_ISR_SOTECP3F_Msk (0x1UL << HSP_EVT_ISR_SOTECP3F_Pos) /*!< 0x00080000 */ #define HSP_EVT_ISR_SOTECP3F HSP_EVT_ISR_SOTECP3F_Msk /*!< SOTECP3F (Start of task flag, for event comparator 3) */ -/*!< EOTECP0F configuration */ -#define HSP_EVT_ISR_EOTECP0F_Pos (20U) + +#define HSP_EVT_ISR_EOTECP0F_Pos (20UL) #define HSP_EVT_ISR_EOTECP0F_Msk (0x1UL << HSP_EVT_ISR_EOTECP0F_Pos) /*!< 0x00100000 */ #define HSP_EVT_ISR_EOTECP0F HSP_EVT_ISR_EOTECP0F_Msk /*!< EOTECP0F (End of task flag, for event comparator 0) */ -/*!< EOTECP1F configuration */ -#define HSP_EVT_ISR_EOTECP1F_Pos (21U) + +#define HSP_EVT_ISR_EOTECP1F_Pos (21UL) #define HSP_EVT_ISR_EOTECP1F_Msk (0x1UL << HSP_EVT_ISR_EOTECP1F_Pos) /*!< 0x00200000 */ #define HSP_EVT_ISR_EOTECP1F HSP_EVT_ISR_EOTECP1F_Msk /*!< EOTECP1F (End of task flag, for event comparator 1) */ -/*!< EOTECP2F configuration */ -#define HSP_EVT_ISR_EOTECP2F_Pos (22U) + +#define HSP_EVT_ISR_EOTECP2F_Pos (22UL) #define HSP_EVT_ISR_EOTECP2F_Msk (0x1UL << HSP_EVT_ISR_EOTECP2F_Pos) /*!< 0x00400000 */ #define HSP_EVT_ISR_EOTECP2F HSP_EVT_ISR_EOTECP2F_Msk /*!< EOTECP2F (End of task flag, for event comparator 2) */ -/*!< EOTECP3F configuration */ -#define HSP_EVT_ISR_EOTECP3F_Pos (23U) + +#define HSP_EVT_ISR_EOTECP3F_Pos (23UL) #define HSP_EVT_ISR_EOTECP3F_Msk (0x1UL << HSP_EVT_ISR_EOTECP3F_Pos) /*!< 0x00800000 */ #define HSP_EVT_ISR_EOTECP3F HSP_EVT_ISR_EOTECP3F_Msk /*!< EOTECP3F (End of task flag, for event comparator 3) */ -/*!< TOVLPF configuration */ -#define HSP_EVT_ISR_TOVLPF_Pos (28U) + +#define HSP_EVT_ISR_TOVLPF_Pos (28UL) #define HSP_EVT_ISR_TOVLPF_Msk (0x1UL << HSP_EVT_ISR_TOVLPF_Pos) /*!< 0x10000000 */ #define HSP_EVT_ISR_TOVLPF HSP_EVT_ISR_TOVLPF_Msk /*!< TOVLPF (Task overlap flag) */ -/*!< FPUSATF configuration */ -#define HSP_EVT_ISR_FPUSATF_Pos (31U) + +#define HSP_EVT_ISR_FPUSATF_Pos (31UL) #define HSP_EVT_ISR_FPUSATF_Msk (0x1UL << HSP_EVT_ISR_FPUSATF_Pos) /*!< 0x80000000 */ #define HSP_EVT_ISR_FPUSATF HSP_EVT_ISR_FPUSATF_Msk /*!< FPUSATF (FPU saturation flag) */ /******************** Bit definition for HSP_PFCTEVT_ISR register ********************/ -/*!< PFCTF configuration */ -#define HSP_PFCTEVT_ISR_PFCTF_Pos (0U) +#define HSP_PFCTEVT_ISR_PFCTF_Pos (0UL) #define HSP_PFCTEVT_ISR_PFCTF_Msk (0xFFFFFFFFUL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0xFFFFFFFF */ #define HSP_PFCTEVT_ISR_PFCTF HSP_PFCTEVT_ISR_PFCTF_Msk /*!< PFCTF[31:0] bits (Flags generated by SPE processing functions ) */ #define HSP_PFCTEVT_ISR_PFCTF_0 (0x00001UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000001 */ @@ -13621,48 +14187,47 @@ typedef struct #define HSP_PFCTEVT_ISR_PFCTF_31 (0x80000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_ERRINFR register ********************/ -/*!< INEXACT configuration */ -#define HSP_ERRINFR_INEXACT_Pos (0U) +#define HSP_ERRINFR_INEXACT_Pos (0UL) #define HSP_ERRINFR_INEXACT_Msk (0x1UL << HSP_ERRINFR_INEXACT_Pos) /*!< 0x00000001 */ #define HSP_ERRINFR_INEXACT HSP_ERRINFR_INEXACT_Msk /*!< INEXACT (INEXACT exception flag) */ -/*!< UDFLOW configuration */ -#define HSP_ERRINFR_UDFLOW_Pos (1U) + +#define HSP_ERRINFR_UDFLOW_Pos (1UL) #define HSP_ERRINFR_UDFLOW_Msk (0x1UL << HSP_ERRINFR_UDFLOW_Pos) /*!< 0x00000002 */ #define HSP_ERRINFR_UDFLOW HSP_ERRINFR_UDFLOW_Msk /*!< UDFLOW (UNDERFLOW exception flag) */ -/*!< OVFLOW configuration */ -#define HSP_ERRINFR_OVFLOW_Pos (2U) + +#define HSP_ERRINFR_OVFLOW_Pos (2UL) #define HSP_ERRINFR_OVFLOW_Msk (0x1UL << HSP_ERRINFR_OVFLOW_Pos) /*!< 0x00000004 */ #define HSP_ERRINFR_OVFLOW HSP_ERRINFR_OVFLOW_Msk /*!< OVFLOW (OVERFLOW exception flag) */ -/*!< DIVZERO configuration */ -#define HSP_ERRINFR_DIVZERO_Pos (3U) + +#define HSP_ERRINFR_DIVZERO_Pos (3UL) #define HSP_ERRINFR_DIVZERO_Msk (0x1UL << HSP_ERRINFR_DIVZERO_Pos) /*!< 0x00000008 */ #define HSP_ERRINFR_DIVZERO HSP_ERRINFR_DIVZERO_Msk /*!< DIVZERO (Division by zero exception flag) */ -/*!< INVALID configuration */ -#define HSP_ERRINFR_INVALID_Pos (4U) + +#define HSP_ERRINFR_INVALID_Pos (4UL) #define HSP_ERRINFR_INVALID_Msk (0x1UL << HSP_ERRINFR_INVALID_Pos) /*!< 0x00000010 */ #define HSP_ERRINFR_INVALID HSP_ERRINFR_INVALID_Msk /*!< INVALID (INVALID exception flag) */ -/*!< DENORM configuration */ -#define HSP_ERRINFR_DENORM_Pos (5U) + +#define HSP_ERRINFR_DENORM_Pos (5UL) #define HSP_ERRINFR_DENORM_Msk (0x1UL << HSP_ERRINFR_DENORM_Pos) /*!< 0x00000020 */ #define HSP_ERRINFR_DENORM HSP_ERRINFR_DENORM_Msk /*!< DENORM (DENORMAL exception flag) */ -/*!< CMERR configuration */ -#define HSP_ERRINFR_CMERR_Pos (8U) + +#define HSP_ERRINFR_CMERR_Pos (8UL) #define HSP_ERRINFR_CMERR_Msk (0x1UL << HSP_ERRINFR_CMERR_Pos) /*!< 0x00000100 */ #define HSP_ERRINFR_CMERR HSP_ERRINFR_CMERR_Msk /*!< CMERR (Code memory access error flag) */ -/*!< DMERR configuration */ -#define HSP_ERRINFR_DMERR_Pos (9U) + +#define HSP_ERRINFR_DMERR_Pos (9UL) #define HSP_ERRINFR_DMERR_Msk (0x1UL << HSP_ERRINFR_DMERR_Pos) /*!< 0x00000200 */ #define HSP_ERRINFR_DMERR HSP_ERRINFR_DMERR_Msk /*!< DMERR (Data memory access error flag) */ -/*!< MAHBERR configuration */ -#define HSP_ERRINFR_MAHBERR_Pos (11U) + +#define HSP_ERRINFR_MAHBERR_Pos (11UL) #define HSP_ERRINFR_MAHBERR_Msk (0x1UL << HSP_ERRINFR_MAHBERR_Pos) /*!< 0x00000800 */ #define HSP_ERRINFR_MAHBERR HSP_ERRINFR_MAHBERR_Msk /*!< MAHBERR (Internal AHB access error flag) */ -/*!< SAHBERR configuration */ -#define HSP_ERRINFR_SAHBERR_Pos (12U) + +#define HSP_ERRINFR_SAHBERR_Pos (12UL) #define HSP_ERRINFR_SAHBERR_Msk (0x1UL << HSP_ERRINFR_SAHBERR_Pos) /*!< 0x00001000 */ #define HSP_ERRINFR_SAHBERR HSP_ERRINFR_SAHBERR_Msk /*!< SAHBERR (Slave AHB access error flag) */ -/*!< TRGIERR configuration */ -#define HSP_ERRINFR_TRGIERR_Pos (16U) + +#define HSP_ERRINFR_TRGIERR_Pos (16UL) #define HSP_ERRINFR_TRGIERR_Msk (0x3FFUL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x03FF0000 */ #define HSP_ERRINFR_TRGIERR HSP_ERRINFR_TRGIERR_Msk /*!< TRGIERR[9:0] bits (TRGIN error information) */ #define HSP_ERRINFR_TRGIERR_0 (0x001UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00010000 */ @@ -13677,128 +14242,125 @@ typedef struct #define HSP_ERRINFR_TRGIERR_9 (0x200UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x02000000 */ /******************** Bit definition for HSP_ERR_ICR register ********************/ -/*!< TRGIOVRC configuration */ -#define HSP_ERR_ICR_TRGIOVRC_Pos (8U) +#define HSP_ERR_ICR_TRGIOVRC_Pos (8UL) #define HSP_ERR_ICR_TRGIOVRC_Msk (0x1UL << HSP_ERR_ICR_TRGIOVRC_Pos) /*!< 0x00000100 */ #define HSP_ERR_ICR_TRGIOVRC HSP_ERR_ICR_TRGIOVRC_Msk /*!< TRGIOVRC (Clear TRGIOVRF flag) */ -/*!< B0ERRC configuration */ -#define HSP_ERR_ICR_B0ERRC_Pos (12U) + +#define HSP_ERR_ICR_B0ERRC_Pos (12UL) #define HSP_ERR_ICR_B0ERRC_Msk (0x1UL << HSP_ERR_ICR_B0ERRC_Pos) /*!< 0x00001000 */ #define HSP_ERR_ICR_B0ERRC HSP_ERR_ICR_B0ERRC_Msk /*!< B0ERRC (Clear B0ERRF flag) */ -/*!< B1ERRC configuration */ -#define HSP_ERR_ICR_B1ERRC_Pos (13U) + +#define HSP_ERR_ICR_B1ERRC_Pos (13UL) #define HSP_ERR_ICR_B1ERRC_Msk (0x1UL << HSP_ERR_ICR_B1ERRC_Pos) /*!< 0x00002000 */ #define HSP_ERR_ICR_B1ERRC HSP_ERR_ICR_B1ERRC_Msk /*!< B1ERRC (Clear B1ERRF flag) */ -/*!< B2ERRC configuration */ -#define HSP_ERR_ICR_B2ERRC_Pos (14U) + +#define HSP_ERR_ICR_B2ERRC_Pos (14UL) #define HSP_ERR_ICR_B2ERRC_Msk (0x1UL << HSP_ERR_ICR_B2ERRC_Pos) /*!< 0x00004000 */ #define HSP_ERR_ICR_B2ERRC HSP_ERR_ICR_B2ERRC_Msk /*!< B2ERRC (Clear B2ERRF flag) */ -/*!< B3ERRC configuration */ -#define HSP_ERR_ICR_B3ERRC_Pos (15U) + +#define HSP_ERR_ICR_B3ERRC_Pos (15UL) #define HSP_ERR_ICR_B3ERRC_Msk (0x1UL << HSP_ERR_ICR_B3ERRC_Pos) /*!< 0x00008000 */ #define HSP_ERR_ICR_B3ERRC HSP_ERR_ICR_B3ERRC_Msk /*!< B3ERRC (Clear B3ERRF flag) */ -/*!< CAPOVRC configuration */ -#define HSP_ERR_ICR_CAPOVRC_Pos (16U) + +#define HSP_ERR_ICR_CAPOVRC_Pos (16UL) #define HSP_ERR_ICR_CAPOVRC_Msk (0x1UL << HSP_ERR_ICR_CAPOVRC_Pos) /*!< 0x00010000 */ #define HSP_ERR_ICR_CAPOVRC HSP_ERR_ICR_CAPOVRC_Msk /*!< CAPOVRC (Clear CAPOVRF flag) */ -/*!< FWERRC configuration */ -#define HSP_ERR_ICR_FWERRC_Pos (17U) + +#define HSP_ERR_ICR_FWERRC_Pos (17UL) #define HSP_ERR_ICR_FWERRC_Msk (0x1UL << HSP_ERR_ICR_FWERRC_Pos) /*!< 0x00020000 */ #define HSP_ERR_ICR_FWERRC HSP_ERR_ICR_FWERRC_Msk /*!< FWERRC (Clear FWERRF flag) */ -/*!< SCHERRC configuration */ -#define HSP_ERR_ICR_SCHERRC_Pos (18U) + +#define HSP_ERR_ICR_SCHERRC_Pos (18UL) #define HSP_ERR_ICR_SCHERRC_Msk (0x1UL << HSP_ERR_ICR_SCHERRC_Pos) /*!< 0x00040000 */ #define HSP_ERR_ICR_SCHERRC HSP_ERR_ICR_SCHERRC_Msk /*!< SCHERRC (Clear SCHERRF flag) */ -/*!< BKINC configuration */ -#define HSP_ERR_ICR_BKINC_Pos (19U) + +#define HSP_ERR_ICR_BKINC_Pos (19UL) #define HSP_ERR_ICR_BKINC_Msk (0x1UL << HSP_ERR_ICR_BKINC_Pos) /*!< 0x00080000 */ #define HSP_ERR_ICR_BKINC HSP_ERR_ICR_BKINC_Msk /*!< BKINC (Clear BKINF flag) */ -/*!< HDEGOVRC configuration */ -#define HSP_ERR_ICR_HDEGOVRC_Pos (20U) + +#define HSP_ERR_ICR_HDEGOVRC_Pos (20UL) #define HSP_ERR_ICR_HDEGOVRC_Msk (0x1UL << HSP_ERR_ICR_HDEGOVRC_Pos) /*!< 0x00100000 */ #define HSP_ERR_ICR_HDEGOVRC HSP_ERR_ICR_HDEGOVRC_Msk /*!< HDEGOVRC (Clear HDEGOVRF flag) */ -/*!< OPCOERRC configuration */ -#define HSP_ERR_ICR_OPCOERRC_Pos (22U) + +#define HSP_ERR_ICR_OPCOERRC_Pos (22UL) #define HSP_ERR_ICR_OPCOERRC_Msk (0x1UL << HSP_ERR_ICR_OPCOERRC_Pos) /*!< 0x00400000 */ #define HSP_ERR_ICR_OPCOERRC HSP_ERR_ICR_OPCOERRC_Msk /*!< OPCOERRC (Clear OPCOERRF flag) */ -/*!< ACCERRC configuration */ -#define HSP_ERR_ICR_ACCERRC_Pos (23U) + +#define HSP_ERR_ICR_ACCERRC_Pos (23UL) #define HSP_ERR_ICR_ACCERRC_Msk (0x1UL << HSP_ERR_ICR_ACCERRC_Pos) /*!< 0x00800000 */ #define HSP_ERR_ICR_ACCERRC HSP_ERR_ICR_ACCERRC_Msk /*!< ACCERRC (Clear ACCERRF flag) */ -/*!< FPUERRC configuration */ -#define HSP_ERR_ICR_FPUERRC_Pos (24U) + +#define HSP_ERR_ICR_FPUERRC_Pos (24UL) #define HSP_ERR_ICR_FPUERRC_Msk (0x1UL << HSP_ERR_ICR_FPUERRC_Pos) /*!< 0x01000000 */ #define HSP_ERR_ICR_FPUERRC HSP_ERR_ICR_FPUERRC_Msk /*!< FPUERRC (Clear FPUERRF flag) */ /******************** Bit definition for HSP_EVT_ICR register ********************/ -/*!< H2CMRDYC configuration */ -#define HSP_EVT_ICR_H2CMRDYC_Pos (0U) +#define HSP_EVT_ICR_H2CMRDYC_Pos (0UL) #define HSP_EVT_ICR_H2CMRDYC_Msk (0x1UL << HSP_EVT_ICR_H2CMRDYC_Pos) /*!< 0x00000001 */ #define HSP_EVT_ICR_H2CMRDYC HSP_EVT_ICR_H2CMRDYC_Msk /*!< H2CMRDYC (Clear H2CMRDYF flag) */ -/*!< C2HMFREEC configuration */ -#define HSP_EVT_ICR_C2HMFREEC_Pos (1U) + +#define HSP_EVT_ICR_C2HMFREEC_Pos (1UL) #define HSP_EVT_ICR_C2HMFREEC_Msk (0x1UL << HSP_EVT_ICR_C2HMFREEC_Pos) /*!< 0x00000002 */ #define HSP_EVT_ICR_C2HMFREEC HSP_EVT_ICR_C2HMFREEC_Msk /*!< C2HMFREEC (Clear C2HMFREEF flag) */ -/*!< DCDONEC configuration */ -#define HSP_EVT_ICR_DCDONEC_Pos (2U) + +#define HSP_EVT_ICR_DCDONEC_Pos (2UL) #define HSP_EVT_ICR_DCDONEC_Msk (0x1UL << HSP_EVT_ICR_DCDONEC_Pos) /*!< 0x00000004 */ #define HSP_EVT_ICR_DCDONEC HSP_EVT_ICR_DCDONEC_Msk /*!< DCDONEC (Clear DCDONEF flag) */ -/*!< CDEGRDYC configuration */ -#define HSP_EVT_ICR_CDEGRDYC_Pos (7U) + +#define HSP_EVT_ICR_CDEGRDYC_Pos (7UL) #define HSP_EVT_ICR_CDEGRDYC_Msk (0x1UL << HSP_EVT_ICR_CDEGRDYC_Pos) /*!< 0x00000080 */ #define HSP_EVT_ICR_CDEGRDYC HSP_EVT_ICR_CDEGRDYC_Msk /*!< CDEGRDYC (Clear of CDEGRDYF flag) */ -/*!< SOFWFEC configuration */ -#define HSP_EVT_ICR_SOFWFEC_Pos (8U) + +#define HSP_EVT_ICR_SOFWFEC_Pos (8UL) #define HSP_EVT_ICR_SOFWFEC_Msk (0x1UL << HSP_EVT_ICR_SOFWFEC_Pos) /*!< 0x00000100 */ #define HSP_EVT_ICR_SOFWFEC HSP_EVT_ICR_SOFWFEC_Msk /*!< SOFWFEC (Clear of SOFWFEF flag) */ -/*!< EOFWFEC configuration */ -#define HSP_EVT_ICR_EOFWFEC_Pos (9U) + +#define HSP_EVT_ICR_EOFWFEC_Pos (9UL) #define HSP_EVT_ICR_EOFWFEC_Msk (0x1UL << HSP_EVT_ICR_EOFWFEC_Pos) /*!< 0x00000200 */ #define HSP_EVT_ICR_EOFWFEC HSP_EVT_ICR_EOFWFEC_Msk /*!< EOFWFEC (Clear of EOFWFEF flag) */ -/*!< SOTECP0C configuration */ -#define HSP_EVT_ICR_SOTECP0C_Pos (16U) + +#define HSP_EVT_ICR_SOTECP0C_Pos (16UL) #define HSP_EVT_ICR_SOTECP0C_Msk (0x1UL << HSP_EVT_ICR_SOTECP0C_Pos) /*!< 0x00010000 */ #define HSP_EVT_ICR_SOTECP0C HSP_EVT_ICR_SOTECP0C_Msk /*!< SOTECP0C (Clear SOTECP0F flag) */ -/*!< SOTECP1C configuration */ -#define HSP_EVT_ICR_SOTECP1C_Pos (17U) + +#define HSP_EVT_ICR_SOTECP1C_Pos (17UL) #define HSP_EVT_ICR_SOTECP1C_Msk (0x1UL << HSP_EVT_ICR_SOTECP1C_Pos) /*!< 0x00020000 */ #define HSP_EVT_ICR_SOTECP1C HSP_EVT_ICR_SOTECP1C_Msk /*!< SOTECP1C (Clear SOTECP1F flag) */ -/*!< SOTECP2C configuration */ -#define HSP_EVT_ICR_SOTECP2C_Pos (18U) + +#define HSP_EVT_ICR_SOTECP2C_Pos (18UL) #define HSP_EVT_ICR_SOTECP2C_Msk (0x1UL << HSP_EVT_ICR_SOTECP2C_Pos) /*!< 0x00040000 */ #define HSP_EVT_ICR_SOTECP2C HSP_EVT_ICR_SOTECP2C_Msk /*!< SOTECP2C (Clear SOTECP2F flag) */ -/*!< SOTECP3C configuration */ -#define HSP_EVT_ICR_SOTECP3C_Pos (19U) + +#define HSP_EVT_ICR_SOTECP3C_Pos (19UL) #define HSP_EVT_ICR_SOTECP3C_Msk (0x1UL << HSP_EVT_ICR_SOTECP3C_Pos) /*!< 0x00080000 */ #define HSP_EVT_ICR_SOTECP3C HSP_EVT_ICR_SOTECP3C_Msk /*!< SOTECP3C (Clear SOTECP3F flag) */ -/*!< EOTECP0C configuration */ -#define HSP_EVT_ICR_EOTECP0C_Pos (20U) + +#define HSP_EVT_ICR_EOTECP0C_Pos (20UL) #define HSP_EVT_ICR_EOTECP0C_Msk (0x1UL << HSP_EVT_ICR_EOTECP0C_Pos) /*!< 0x00100000 */ #define HSP_EVT_ICR_EOTECP0C HSP_EVT_ICR_EOTECP0C_Msk /*!< EOTECP0C (Clear EOTECP0F flag) */ -/*!< EOTECP1C configuration */ -#define HSP_EVT_ICR_EOTECP1C_Pos (21U) + +#define HSP_EVT_ICR_EOTECP1C_Pos (21UL) #define HSP_EVT_ICR_EOTECP1C_Msk (0x1UL << HSP_EVT_ICR_EOTECP1C_Pos) /*!< 0x00200000 */ #define HSP_EVT_ICR_EOTECP1C HSP_EVT_ICR_EOTECP1C_Msk /*!< EOTECP1C (Clear EOTECP1F flag) */ -/*!< EOTECP2C configuration */ -#define HSP_EVT_ICR_EOTECP2C_Pos (22U) + +#define HSP_EVT_ICR_EOTECP2C_Pos (22UL) #define HSP_EVT_ICR_EOTECP2C_Msk (0x1UL << HSP_EVT_ICR_EOTECP2C_Pos) /*!< 0x00400000 */ #define HSP_EVT_ICR_EOTECP2C HSP_EVT_ICR_EOTECP2C_Msk /*!< EOTECP2C (Clear EOTECP2F flag) */ -/*!< EOTECP3C configuration */ -#define HSP_EVT_ICR_EOTECP3C_Pos (23U) + +#define HSP_EVT_ICR_EOTECP3C_Pos (23UL) #define HSP_EVT_ICR_EOTECP3C_Msk (0x1UL << HSP_EVT_ICR_EOTECP3C_Pos) /*!< 0x00800000 */ #define HSP_EVT_ICR_EOTECP3C HSP_EVT_ICR_EOTECP3C_Msk /*!< EOTECP3C (Clear EOTECP3F flag) */ -/*!< TOVLPC configuration */ -#define HSP_EVT_ICR_TOVLPC_Pos (28U) + +#define HSP_EVT_ICR_TOVLPC_Pos (28UL) #define HSP_EVT_ICR_TOVLPC_Msk (0x1UL << HSP_EVT_ICR_TOVLPC_Pos) /*!< 0x10000000 */ #define HSP_EVT_ICR_TOVLPC HSP_EVT_ICR_TOVLPC_Msk /*!< TOVLPC (Clear TOVLPF flag) */ -/*!< FPUSATC configuration */ -#define HSP_EVT_ICR_FPUSATC_Pos (31U) + +#define HSP_EVT_ICR_FPUSATC_Pos (31UL) #define HSP_EVT_ICR_FPUSATC_Msk (0x1UL << HSP_EVT_ICR_FPUSATC_Pos) /*!< 0x80000000 */ #define HSP_EVT_ICR_FPUSATC HSP_EVT_ICR_FPUSATC_Msk /*!< FPUSATC (Clear FPUSATF flag) */ /******************** Bit definition for HSP_PFCTEVT_ICR register ********************/ -/*!< PFCTC configuration */ -#define HSP_PFCTEVT_ICR_PFCTC_Pos (0U) +#define HSP_PFCTEVT_ICR_PFCTC_Pos (0UL) #define HSP_PFCTEVT_ICR_PFCTC_Msk (0xFFFFFFFFUL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0xFFFFFFFF */ #define HSP_PFCTEVT_ICR_PFCTC HSP_PFCTEVT_ICR_PFCTC_Msk /*!< PFCTC[31:0] bits (Clear PFCTF[31:0] flag) */ #define HSP_PFCTEVT_ICR_PFCTC_0 (0x00001UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000001 */ @@ -13835,358 +14397,29 @@ typedef struct #define HSP_PFCTEVT_ICR_PFCTC_31 (0x80000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x80000000 */ /******************** Bit definition for HSP_FWVERR register ********************/ -/*!< CROMINREV configuration */ -#define HSP_FWVERR_CROMINREV_Pos (0U) -#define HSP_FWVERR_CROMINREV_Msk (0xFUL << HSP_FWVERR_CROMINREV_Pos) /*!< 0x0000000F */ -#define HSP_FWVERR_CROMINREV HSP_FWVERR_CROMINREV_Msk /*!< CROMINREV[3:0] bits (Code ROM Minor revision) */ -#define HSP_FWVERR_CROMINREV_0 (0x01UL << HSP_FWVERR_CROMINREV_Pos) /*!< 0x00000001 */ -#define HSP_FWVERR_CROMINREV_1 (0x02UL << HSP_FWVERR_CROMINREV_Pos) /*!< 0x00000002 */ -#define HSP_FWVERR_CROMINREV_2 (0x04UL << HSP_FWVERR_CROMINREV_Pos) /*!< 0x00000004 */ -#define HSP_FWVERR_CROMINREV_3 (0x08UL << HSP_FWVERR_CROMINREV_Pos) /*!< 0x00000008 */ -/*!< CROMAJREV configuration */ -#define HSP_FWVERR_CROMAJREV_Pos (4U) -#define HSP_FWVERR_CROMAJREV_Msk (0xFUL << HSP_FWVERR_CROMAJREV_Pos) /*!< 0x000000F0 */ -#define HSP_FWVERR_CROMAJREV HSP_FWVERR_CROMAJREV_Msk /*!< CROMAJREV[3:0] bits (Code ROM Major revision) */ -#define HSP_FWVERR_CROMAJREV_0 (0x01UL << HSP_FWVERR_CROMAJREV_Pos) /*!< 0x00000010 */ -#define HSP_FWVERR_CROMAJREV_1 (0x02UL << HSP_FWVERR_CROMAJREV_Pos) /*!< 0x00000020 */ -#define HSP_FWVERR_CROMAJREV_2 (0x04UL << HSP_FWVERR_CROMAJREV_Pos) /*!< 0x00000040 */ -#define HSP_FWVERR_CROMAJREV_3 (0x08UL << HSP_FWVERR_CROMAJREV_Pos) /*!< 0x00000080 */ -/*!< CRAMINREV configuration */ -#define HSP_FWVERR_CRAMINREV_Pos (8U) -#define HSP_FWVERR_CRAMINREV_Msk (0xFUL << HSP_FWVERR_CRAMINREV_Pos) /*!< 0x00000F00 */ -#define HSP_FWVERR_CRAMINREV HSP_FWVERR_CRAMINREV_Msk /*!< CRAMINREV[3:0] bits (Code RAM Minor revision) */ -#define HSP_FWVERR_CRAMINREV_0 (0x01UL << HSP_FWVERR_CRAMINREV_Pos) /*!< 0x00000100 */ -#define HSP_FWVERR_CRAMINREV_1 (0x02UL << HSP_FWVERR_CRAMINREV_Pos) /*!< 0x00000200 */ -#define HSP_FWVERR_CRAMINREV_2 (0x04UL << HSP_FWVERR_CRAMINREV_Pos) /*!< 0x00000400 */ -#define HSP_FWVERR_CRAMINREV_3 (0x08UL << HSP_FWVERR_CRAMINREV_Pos) /*!< 0x00000800 */ -/*!< CRAMAJREV configuration */ -#define HSP_FWVERR_CRAMAJREV_Pos (12U) -#define HSP_FWVERR_CRAMAJREV_Msk (0xFUL << HSP_FWVERR_CRAMAJREV_Pos) /*!< 0x0000F000 */ +#define HSP_FWVERR_CRAMINREV_Pos (0UL) +#define HSP_FWVERR_CRAMINREV_Msk (0xFFUL << HSP_FWVERR_CRAMINREV_Pos) /*!< 0x000000FF */ +#define HSP_FWVERR_CRAMINREV HSP_FWVERR_CRAMINREV_Msk /*!< CRAMINREV[7:0] bits (Code RAM Minor revision) */ + +#define HSP_FWVERR_CRAMAJREV_Pos (8UL) +#define HSP_FWVERR_CRAMAJREV_Msk (0xFUL << HSP_FWVERR_CRAMAJREV_Pos) /*!< 0x00000F00 */ #define HSP_FWVERR_CRAMAJREV HSP_FWVERR_CRAMAJREV_Msk /*!< CRAMAJREV[3:0] bits (Code RAM Major revision) */ -#define HSP_FWVERR_CRAMAJREV_0 (0x01UL << HSP_FWVERR_CRAMAJREV_Pos) /*!< 0x00001000 */ -#define HSP_FWVERR_CRAMAJREV_1 (0x02UL << HSP_FWVERR_CRAMAJREV_Pos) /*!< 0x00002000 */ -#define HSP_FWVERR_CRAMAJREV_2 (0x04UL << HSP_FWVERR_CRAMAJREV_Pos) /*!< 0x00004000 */ -#define HSP_FWVERR_CRAMAJREV_3 (0x08UL << HSP_FWVERR_CRAMAJREV_Pos) /*!< 0x00008000 */ -/*!< DROMINREV configuration */ -#define HSP_FWVERR_DROMINREV_Pos (16U) -#define HSP_FWVERR_DROMINREV_Msk (0xFUL << HSP_FWVERR_DROMINREV_Pos) /*!< 0x000F0000 */ + +#define HSP_FWVERR_CROMINREV_Pos (12UL) +#define HSP_FWVERR_CROMINREV_Msk (0xFFUL << HSP_FWVERR_CROMINREV_Pos) /*!< 0x000FF000 */ +#define HSP_FWVERR_CROMINREV HSP_FWVERR_CROMINREV_Msk /*!< CROMINREV[7:0] bits (Code ROM Minor revision) */ + +#define HSP_FWVERR_CROMAJREV_Pos (20UL) +#define HSP_FWVERR_CROMAJREV_Msk (0xFUL << HSP_FWVERR_CROMAJREV_Pos) /*!< 0x000F0000 */ +#define HSP_FWVERR_CROMAJREV HSP_FWVERR_CROMAJREV_Msk /*!< CROMAJREV[3:0] bits (Code ROM Major revision) */ + +#define HSP_FWVERR_DROMINREV_Pos (24UL) +#define HSP_FWVERR_DROMINREV_Msk (0xFUL << HSP_FWVERR_DROMINREV_Pos) /*!< 0x00F00000 */ #define HSP_FWVERR_DROMINREV HSP_FWVERR_DROMINREV_Msk /*!< DROMINREV[3:0] bits (Data ROM Minor revision) */ -#define HSP_FWVERR_DROMINREV_0 (0x01UL << HSP_FWVERR_DROMINREV_Pos) /*!< 0x00010000 */ -#define HSP_FWVERR_DROMINREV_1 (0x02UL << HSP_FWVERR_DROMINREV_Pos) /*!< 0x00020000 */ -#define HSP_FWVERR_DROMINREV_2 (0x04UL << HSP_FWVERR_DROMINREV_Pos) /*!< 0x00040000 */ -#define HSP_FWVERR_DROMINREV_3 (0x08UL << HSP_FWVERR_DROMINREV_Pos) /*!< 0x00080000 */ -/*!< DROMAJREV configuration */ -#define HSP_FWVERR_DROMAJREV_Pos (20U) -#define HSP_FWVERR_DROMAJREV_Msk (0xFUL << HSP_FWVERR_DROMAJREV_Pos) /*!< 0x00F00000 */ + +#define HSP_FWVERR_DROMAJREV_Pos (28UL) +#define HSP_FWVERR_DROMAJREV_Msk (0xFUL << HSP_FWVERR_DROMAJREV_Pos) /*!< 0x0F000000 */ #define HSP_FWVERR_DROMAJREV HSP_FWVERR_DROMAJREV_Msk /*!< DROMAJREV[3:0] bits (Data ROM Major revision) */ -#define HSP_FWVERR_DROMAJREV_0 (0x01UL << HSP_FWVERR_DROMAJREV_Pos) /*!< 0x00100000 */ -#define HSP_FWVERR_DROMAJREV_1 (0x02UL << HSP_FWVERR_DROMAJREV_Pos) /*!< 0x00200000 */ -#define HSP_FWVERR_DROMAJREV_2 (0x04UL << HSP_FWVERR_DROMAJREV_Pos) /*!< 0x00400000 */ -#define HSP_FWVERR_DROMAJREV_3 (0x08UL << HSP_FWVERR_DROMAJREV_Pos) /*!< 0x00800000 */ - -/******************** Bit definition for HSP_SPEVERR register ********************/ -/*!< SPEVER configuration */ -#define HSP_SPEVERR_SPEVER_Pos (0U) -#define HSP_SPEVERR_SPEVER_Msk (0xFFFFFFFFUL << HSP_SPEVERR_SPEVER_Pos) /*!< 0xFFFFFFFF */ -#define HSP_SPEVERR_SPEVER HSP_SPEVERR_SPEVER_Msk /*!< SPEVER[31:0] bits (SPE version ) */ -#define HSP_SPEVERR_SPEVER_0 (0x00001UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00000001 */ -#define HSP_SPEVERR_SPEVER_1 (0x00002UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00000002 */ -#define HSP_SPEVERR_SPEVER_2 (0x00004UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00000004 */ -#define HSP_SPEVERR_SPEVER_3 (0x00008UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00000008 */ -#define HSP_SPEVERR_SPEVER_4 (0x00010UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00000010 */ -#define HSP_SPEVERR_SPEVER_5 (0x00020UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00000020 */ -#define HSP_SPEVERR_SPEVER_6 (0x00040UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00000040 */ -#define HSP_SPEVERR_SPEVER_7 (0x00080UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00000080 */ -#define HSP_SPEVERR_SPEVER_8 (0x00100UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00000100 */ -#define HSP_SPEVERR_SPEVER_9 (0x00200UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00000200 */ -#define HSP_SPEVERR_SPEVER_10 (0x00400UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00000400 */ -#define HSP_SPEVERR_SPEVER_11 (0x00800UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00000800 */ -#define HSP_SPEVERR_SPEVER_12 (0x01000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00001000 */ -#define HSP_SPEVERR_SPEVER_13 (0x02000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00002000 */ -#define HSP_SPEVERR_SPEVER_14 (0x04000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00004000 */ -#define HSP_SPEVERR_SPEVER_15 (0x08000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00008000 */ -#define HSP_SPEVERR_SPEVER_16 (0x10000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00010000 */ -#define HSP_SPEVERR_SPEVER_17 (0x20000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00020000 */ -#define HSP_SPEVERR_SPEVER_18 (0x40000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00040000 */ -#define HSP_SPEVERR_SPEVER_19 (0x80000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00080000 */ -#define HSP_SPEVERR_SPEVER_20 (0x100000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00100000 */ -#define HSP_SPEVERR_SPEVER_21 (0x200000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00200000 */ -#define HSP_SPEVERR_SPEVER_22 (0x400000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00400000 */ -#define HSP_SPEVERR_SPEVER_23 (0x800000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x00800000 */ -#define HSP_SPEVERR_SPEVER_24 (0x1000000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x01000000 */ -#define HSP_SPEVERR_SPEVER_25 (0x2000000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x02000000 */ -#define HSP_SPEVERR_SPEVER_26 (0x4000000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x04000000 */ -#define HSP_SPEVERR_SPEVER_27 (0x8000000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x08000000 */ -#define HSP_SPEVERR_SPEVER_28 (0x10000000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x10000000 */ -#define HSP_SPEVERR_SPEVER_29 (0x20000000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x20000000 */ -#define HSP_SPEVERR_SPEVER_30 (0x40000000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x40000000 */ -#define HSP_SPEVERR_SPEVER_31 (0x80000000UL << HSP_SPEVERR_SPEVER_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for HSP_HWCFGR4 register ********************/ -/*!< NUM_DMA_REQ configuration */ -#define HSP_HWCFGR4_NUM_DMA_REQ_Pos (0U) -#define HSP_HWCFGR4_NUM_DMA_REQ_Msk (0xFFUL << HSP_HWCFGR4_NUM_DMA_REQ_Pos) /*!< 0x000000FF */ -#define HSP_HWCFGR4_NUM_DMA_REQ HSP_HWCFGR4_NUM_DMA_REQ_Msk /*!< NUM_DMA_REQ[7:0] bits (Number of DMA request supported) */ -#define HSP_HWCFGR4_NUM_DMA_REQ_0 (0x001UL << HSP_HWCFGR4_NUM_DMA_REQ_Pos) /*!< 0x00000001 */ -#define HSP_HWCFGR4_NUM_DMA_REQ_1 (0x002UL << HSP_HWCFGR4_NUM_DMA_REQ_Pos) /*!< 0x00000002 */ -#define HSP_HWCFGR4_NUM_DMA_REQ_2 (0x004UL << HSP_HWCFGR4_NUM_DMA_REQ_Pos) /*!< 0x00000004 */ -#define HSP_HWCFGR4_NUM_DMA_REQ_3 (0x008UL << HSP_HWCFGR4_NUM_DMA_REQ_Pos) /*!< 0x00000008 */ -#define HSP_HWCFGR4_NUM_DMA_REQ_4 (0x010UL << HSP_HWCFGR4_NUM_DMA_REQ_Pos) /*!< 0x00000010 */ -#define HSP_HWCFGR4_NUM_DMA_REQ_5 (0x020UL << HSP_HWCFGR4_NUM_DMA_REQ_Pos) /*!< 0x00000020 */ -#define HSP_HWCFGR4_NUM_DMA_REQ_6 (0x040UL << HSP_HWCFGR4_NUM_DMA_REQ_Pos) /*!< 0x00000040 */ -#define HSP_HWCFGR4_NUM_DMA_REQ_7 (0x080UL << HSP_HWCFGR4_NUM_DMA_REQ_Pos) /*!< 0x00000080 */ -/*!< NO_DMA_STI configuration */ -#define HSP_HWCFGR4_NO_DMA_STI_Pos (8U) -#define HSP_HWCFGR4_NO_DMA_STI_Msk (0xFUL << HSP_HWCFGR4_NO_DMA_STI_Pos) /*!< 0x00000F00 */ -#define HSP_HWCFGR4_NO_DMA_STI HSP_HWCFGR4_NO_DMA_STI_Msk /*!< NO_DMA_STI[3:0] bits (HSPDMA and STI implementation) */ -#define HSP_HWCFGR4_NO_DMA_STI_0 (0x01UL << HSP_HWCFGR4_NO_DMA_STI_Pos) /*!< 0x00000100 */ -#define HSP_HWCFGR4_NO_DMA_STI_1 (0x02UL << HSP_HWCFGR4_NO_DMA_STI_Pos) /*!< 0x00000200 */ -#define HSP_HWCFGR4_NO_DMA_STI_2 (0x04UL << HSP_HWCFGR4_NO_DMA_STI_Pos) /*!< 0x00000400 */ -#define HSP_HWCFGR4_NO_DMA_STI_3 (0x08UL << HSP_HWCFGR4_NO_DMA_STI_Pos) /*!< 0x00000800 */ - -/******************** Bit definition for HSP_HWCFGR3 register ********************/ -/*!< NUM_STIAP configuration */ -#define HSP_HWCFGR3_NUM_STIAP_Pos (0U) -#define HSP_HWCFGR3_NUM_STIAP_Msk (0xFUL << HSP_HWCFGR3_NUM_STIAP_Pos) /*!< 0x0000000F */ -#define HSP_HWCFGR3_NUM_STIAP HSP_HWCFGR3_NUM_STIAP_Msk /*!< NUM_STIAP[3:0] bits (Number of STI_AP ports) */ -#define HSP_HWCFGR3_NUM_STIAP_0 (0x01UL << HSP_HWCFGR3_NUM_STIAP_Pos) /*!< 0x00000001 */ -#define HSP_HWCFGR3_NUM_STIAP_1 (0x02UL << HSP_HWCFGR3_NUM_STIAP_Pos) /*!< 0x00000002 */ -#define HSP_HWCFGR3_NUM_STIAP_2 (0x04UL << HSP_HWCFGR3_NUM_STIAP_Pos) /*!< 0x00000004 */ -#define HSP_HWCFGR3_NUM_STIAP_3 (0x08UL << HSP_HWCFGR3_NUM_STIAP_Pos) /*!< 0x00000008 */ -/*!< NUM_STIHP configuration */ -#define HSP_HWCFGR3_NUM_STIHP_Pos (4U) -#define HSP_HWCFGR3_NUM_STIHP_Msk (0xFUL << HSP_HWCFGR3_NUM_STIHP_Pos) /*!< 0x000000F0 */ -#define HSP_HWCFGR3_NUM_STIHP HSP_HWCFGR3_NUM_STIHP_Msk /*!< NUM_STIHP[3:0] bits (Number of STI_HP ports) */ -#define HSP_HWCFGR3_NUM_STIHP_0 (0x01UL << HSP_HWCFGR3_NUM_STIHP_Pos) /*!< 0x00000010 */ -#define HSP_HWCFGR3_NUM_STIHP_1 (0x02UL << HSP_HWCFGR3_NUM_STIHP_Pos) /*!< 0x00000020 */ -#define HSP_HWCFGR3_NUM_STIHP_2 (0x04UL << HSP_HWCFGR3_NUM_STIHP_Pos) /*!< 0x00000040 */ -#define HSP_HWCFGR3_NUM_STIHP_3 (0x08UL << HSP_HWCFGR3_NUM_STIHP_Pos) /*!< 0x00000080 */ -/*!< NUM_TRIG configuration */ -#define HSP_HWCFGR3_NUM_TRIG_Pos (8U) -#define HSP_HWCFGR3_NUM_TRIG_Msk (0xFFUL << HSP_HWCFGR3_NUM_TRIG_Pos) /*!< 0x0000FF00 */ -#define HSP_HWCFGR3_NUM_TRIG HSP_HWCFGR3_NUM_TRIG_Msk /*!< NUM_TRIG[7:0] bits (Number of trigger inputs) */ -#define HSP_HWCFGR3_NUM_TRIG_0 (0x001UL << HSP_HWCFGR3_NUM_TRIG_Pos) /*!< 0x00000100 */ -#define HSP_HWCFGR3_NUM_TRIG_1 (0x002UL << HSP_HWCFGR3_NUM_TRIG_Pos) /*!< 0x00000200 */ -#define HSP_HWCFGR3_NUM_TRIG_2 (0x004UL << HSP_HWCFGR3_NUM_TRIG_Pos) /*!< 0x00000400 */ -#define HSP_HWCFGR3_NUM_TRIG_3 (0x008UL << HSP_HWCFGR3_NUM_TRIG_Pos) /*!< 0x00000800 */ -#define HSP_HWCFGR3_NUM_TRIG_4 (0x010UL << HSP_HWCFGR3_NUM_TRIG_Pos) /*!< 0x00001000 */ -#define HSP_HWCFGR3_NUM_TRIG_5 (0x020UL << HSP_HWCFGR3_NUM_TRIG_Pos) /*!< 0x00002000 */ -#define HSP_HWCFGR3_NUM_TRIG_6 (0x040UL << HSP_HWCFGR3_NUM_TRIG_Pos) /*!< 0x00004000 */ -#define HSP_HWCFGR3_NUM_TRIG_7 (0x080UL << HSP_HWCFGR3_NUM_TRIG_Pos) /*!< 0x00008000 */ -/*!< NUM_TSK_MAX configuration */ -#define HSP_HWCFGR3_NUM_TSK_MAX_Pos (16U) -#define HSP_HWCFGR3_NUM_TSK_MAX_Msk (0xFFUL << HSP_HWCFGR3_NUM_TSK_MAX_Pos) /*!< 0x00FF0000 */ -#define HSP_HWCFGR3_NUM_TSK_MAX HSP_HWCFGR3_NUM_TSK_MAX_Msk /*!< NUM_TSK_MAX[7:0] bits (Maximum number of tasks supported) */ -#define HSP_HWCFGR3_NUM_TSK_MAX_0 (0x001UL << HSP_HWCFGR3_NUM_TSK_MAX_Pos) /*!< 0x00010000 */ -#define HSP_HWCFGR3_NUM_TSK_MAX_1 (0x002UL << HSP_HWCFGR3_NUM_TSK_MAX_Pos) /*!< 0x00020000 */ -#define HSP_HWCFGR3_NUM_TSK_MAX_2 (0x004UL << HSP_HWCFGR3_NUM_TSK_MAX_Pos) /*!< 0x00040000 */ -#define HSP_HWCFGR3_NUM_TSK_MAX_3 (0x008UL << HSP_HWCFGR3_NUM_TSK_MAX_Pos) /*!< 0x00080000 */ -#define HSP_HWCFGR3_NUM_TSK_MAX_4 (0x010UL << HSP_HWCFGR3_NUM_TSK_MAX_Pos) /*!< 0x00100000 */ -#define HSP_HWCFGR3_NUM_TSK_MAX_5 (0x020UL << HSP_HWCFGR3_NUM_TSK_MAX_Pos) /*!< 0x00200000 */ -#define HSP_HWCFGR3_NUM_TSK_MAX_6 (0x040UL << HSP_HWCFGR3_NUM_TSK_MAX_Pos) /*!< 0x00400000 */ -#define HSP_HWCFGR3_NUM_TSK_MAX_7 (0x080UL << HSP_HWCFGR3_NUM_TSK_MAX_Pos) /*!< 0x00800000 */ -/*!< TSK_OFF_SIZE configuration */ -#define HSP_HWCFGR3_TSK_OFF_SIZE_Pos (24U) -#define HSP_HWCFGR3_TSK_OFF_SIZE_Msk (0xFUL << HSP_HWCFGR3_TSK_OFF_SIZE_Pos) /*!< 0x0F000000 */ -#define HSP_HWCFGR3_TSK_OFF_SIZE HSP_HWCFGR3_TSK_OFF_SIZE_Msk /*!< TSK_OFF_SIZE[3:0] bits (Size of task offset values) */ -#define HSP_HWCFGR3_TSK_OFF_SIZE_0 (0x01UL << HSP_HWCFGR3_TSK_OFF_SIZE_Pos) /*!< 0x01000000 */ -#define HSP_HWCFGR3_TSK_OFF_SIZE_1 (0x02UL << HSP_HWCFGR3_TSK_OFF_SIZE_Pos) /*!< 0x02000000 */ -#define HSP_HWCFGR3_TSK_OFF_SIZE_2 (0x04UL << HSP_HWCFGR3_TSK_OFF_SIZE_Pos) /*!< 0x04000000 */ -#define HSP_HWCFGR3_TSK_OFF_SIZE_3 (0x08UL << HSP_HWCFGR3_TSK_OFF_SIZE_Pos) /*!< 0x08000000 */ -/*!< NUM_ADC configuration */ -#define HSP_HWCFGR3_NUM_ADC_Pos (28U) -#define HSP_HWCFGR3_NUM_ADC_Msk (0xFUL << HSP_HWCFGR3_NUM_ADC_Pos) /*!< 0xF0000000 */ -#define HSP_HWCFGR3_NUM_ADC HSP_HWCFGR3_NUM_ADC_Msk /*!< NUM_ADC[3:0] bits (Number of ADC parallel interfaces) */ -#define HSP_HWCFGR3_NUM_ADC_0 (0x01UL << HSP_HWCFGR3_NUM_ADC_Pos) /*!< 0x10000000 */ -#define HSP_HWCFGR3_NUM_ADC_1 (0x02UL << HSP_HWCFGR3_NUM_ADC_Pos) /*!< 0x20000000 */ -#define HSP_HWCFGR3_NUM_ADC_2 (0x04UL << HSP_HWCFGR3_NUM_ADC_Pos) /*!< 0x40000000 */ -#define HSP_HWCFGR3_NUM_ADC_3 (0x08UL << HSP_HWCFGR3_NUM_ADC_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for HSP_HWCFGR2 register ********************/ -/*!< OPTION_REGOUT configuration */ -#define HSP_HWCFGR2_OPTION_REGOUT_Pos (0U) -#define HSP_HWCFGR2_OPTION_REGOUT_Msk (0xFFUL << HSP_HWCFGR2_OPTION_REGOUT_Pos) /*!< 0x000000FF */ -#define HSP_HWCFGR2_OPTION_REGOUT HSP_HWCFGR2_OPTION_REGOUT_Msk /*!< OPTION_REGOUT[7:0] bits (Support of HSP_OR register) */ -#define HSP_HWCFGR2_OPTION_REGOUT_0 (0x001UL << HSP_HWCFGR2_OPTION_REGOUT_Pos) /*!< 0x00000001 */ -#define HSP_HWCFGR2_OPTION_REGOUT_1 (0x002UL << HSP_HWCFGR2_OPTION_REGOUT_Pos) /*!< 0x00000002 */ -#define HSP_HWCFGR2_OPTION_REGOUT_2 (0x004UL << HSP_HWCFGR2_OPTION_REGOUT_Pos) /*!< 0x00000004 */ -#define HSP_HWCFGR2_OPTION_REGOUT_3 (0x008UL << HSP_HWCFGR2_OPTION_REGOUT_Pos) /*!< 0x00000008 */ -#define HSP_HWCFGR2_OPTION_REGOUT_4 (0x010UL << HSP_HWCFGR2_OPTION_REGOUT_Pos) /*!< 0x00000010 */ -#define HSP_HWCFGR2_OPTION_REGOUT_5 (0x020UL << HSP_HWCFGR2_OPTION_REGOUT_Pos) /*!< 0x00000020 */ -#define HSP_HWCFGR2_OPTION_REGOUT_6 (0x040UL << HSP_HWCFGR2_OPTION_REGOUT_Pos) /*!< 0x00000040 */ -#define HSP_HWCFGR2_OPTION_REGOUT_7 (0x080UL << HSP_HWCFGR2_OPTION_REGOUT_Pos) /*!< 0x00000080 */ -/*!< NUM_RESYNC_FFS configuration */ -#define HSP_HWCFGR2_NUM_RESYNC_FFS_Pos (8U) -#define HSP_HWCFGR2_NUM_RESYNC_FFS_Msk (0xFUL << HSP_HWCFGR2_NUM_RESYNC_FFS_Pos) /*!< 0x00000F00 */ -#define HSP_HWCFGR2_NUM_RESYNC_FFS HSP_HWCFGR2_NUM_RESYNC_FFS_Msk /*!< NUM_RESYNC_FFS[3:0] bits (Number of resynchronization flops for Clock Domain Crossing synchronizers.) */ -#define HSP_HWCFGR2_NUM_RESYNC_FFS_0 (0x01UL << HSP_HWCFGR2_NUM_RESYNC_FFS_Pos) /*!< 0x00000100 */ -#define HSP_HWCFGR2_NUM_RESYNC_FFS_1 (0x02UL << HSP_HWCFGR2_NUM_RESYNC_FFS_Pos) /*!< 0x00000200 */ -#define HSP_HWCFGR2_NUM_RESYNC_FFS_2 (0x04UL << HSP_HWCFGR2_NUM_RESYNC_FFS_Pos) /*!< 0x00000400 */ -#define HSP_HWCFGR2_NUM_RESYNC_FFS_3 (0x08UL << HSP_HWCFGR2_NUM_RESYNC_FFS_Pos) /*!< 0x00000800 */ -/*!< DROM_SIZE configuration */ -#define HSP_HWCFGR2_DROM_SIZE_Pos (16U) -#define HSP_HWCFGR2_DROM_SIZE_Msk (0xFFUL << HSP_HWCFGR2_DROM_SIZE_Pos) /*!< 0x00FF0000 */ -#define HSP_HWCFGR2_DROM_SIZE HSP_HWCFGR2_DROM_SIZE_Msk /*!< DROM_SIZE[7:0] bits (DROM Size) */ -#define HSP_HWCFGR2_DROM_SIZE_0 (0x001UL << HSP_HWCFGR2_DROM_SIZE_Pos) /*!< 0x00010000 */ -#define HSP_HWCFGR2_DROM_SIZE_1 (0x002UL << HSP_HWCFGR2_DROM_SIZE_Pos) /*!< 0x00020000 */ -#define HSP_HWCFGR2_DROM_SIZE_2 (0x004UL << HSP_HWCFGR2_DROM_SIZE_Pos) /*!< 0x00040000 */ -#define HSP_HWCFGR2_DROM_SIZE_3 (0x008UL << HSP_HWCFGR2_DROM_SIZE_Pos) /*!< 0x00080000 */ -#define HSP_HWCFGR2_DROM_SIZE_4 (0x010UL << HSP_HWCFGR2_DROM_SIZE_Pos) /*!< 0x00100000 */ -#define HSP_HWCFGR2_DROM_SIZE_5 (0x020UL << HSP_HWCFGR2_DROM_SIZE_Pos) /*!< 0x00200000 */ -#define HSP_HWCFGR2_DROM_SIZE_6 (0x040UL << HSP_HWCFGR2_DROM_SIZE_Pos) /*!< 0x00400000 */ -#define HSP_HWCFGR2_DROM_SIZE_7 (0x080UL << HSP_HWCFGR2_DROM_SIZE_Pos) /*!< 0x00800000 */ -/*!< CROM_SIZE configuration */ -#define HSP_HWCFGR2_CROM_SIZE_Pos (24U) -#define HSP_HWCFGR2_CROM_SIZE_Msk (0xFFUL << HSP_HWCFGR2_CROM_SIZE_Pos) /*!< 0xFF000000 */ -#define HSP_HWCFGR2_CROM_SIZE HSP_HWCFGR2_CROM_SIZE_Msk /*!< CROM_SIZE[7:0] bits (CROM Size) */ -#define HSP_HWCFGR2_CROM_SIZE_0 (0x001UL << HSP_HWCFGR2_CROM_SIZE_Pos) /*!< 0x01000000 */ -#define HSP_HWCFGR2_CROM_SIZE_1 (0x002UL << HSP_HWCFGR2_CROM_SIZE_Pos) /*!< 0x02000000 */ -#define HSP_HWCFGR2_CROM_SIZE_2 (0x004UL << HSP_HWCFGR2_CROM_SIZE_Pos) /*!< 0x04000000 */ -#define HSP_HWCFGR2_CROM_SIZE_3 (0x008UL << HSP_HWCFGR2_CROM_SIZE_Pos) /*!< 0x08000000 */ -#define HSP_HWCFGR2_CROM_SIZE_4 (0x010UL << HSP_HWCFGR2_CROM_SIZE_Pos) /*!< 0x10000000 */ -#define HSP_HWCFGR2_CROM_SIZE_5 (0x020UL << HSP_HWCFGR2_CROM_SIZE_Pos) /*!< 0x20000000 */ -#define HSP_HWCFGR2_CROM_SIZE_6 (0x040UL << HSP_HWCFGR2_CROM_SIZE_Pos) /*!< 0x40000000 */ -#define HSP_HWCFGR2_CROM_SIZE_7 (0x080UL << HSP_HWCFGR2_CROM_SIZE_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for HSP_HWCFGR1 register ********************/ -/*!< BRAM_SIZE configuration */ -#define HSP_HWCFGR1_BRAM_SIZE_Pos (0U) -#define HSP_HWCFGR1_BRAM_SIZE_Msk (0xFFFFUL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x0000FFFF */ -#define HSP_HWCFGR1_BRAM_SIZE HSP_HWCFGR1_BRAM_SIZE_Msk /*!< BRAM_SIZE[15:0] bits (BRAM size) */ -#define HSP_HWCFGR1_BRAM_SIZE_0 (0x0001UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00000001 */ -#define HSP_HWCFGR1_BRAM_SIZE_1 (0x0002UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00000002 */ -#define HSP_HWCFGR1_BRAM_SIZE_2 (0x0004UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00000004 */ -#define HSP_HWCFGR1_BRAM_SIZE_3 (0x0008UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00000008 */ -#define HSP_HWCFGR1_BRAM_SIZE_4 (0x0010UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00000010 */ -#define HSP_HWCFGR1_BRAM_SIZE_5 (0x0020UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00000020 */ -#define HSP_HWCFGR1_BRAM_SIZE_6 (0x0040UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00000040 */ -#define HSP_HWCFGR1_BRAM_SIZE_7 (0x0080UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00000080 */ -#define HSP_HWCFGR1_BRAM_SIZE_8 (0x0100UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00000100 */ -#define HSP_HWCFGR1_BRAM_SIZE_9 (0x0200UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00000200 */ -#define HSP_HWCFGR1_BRAM_SIZE_10 (0x0400UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00000400 */ -#define HSP_HWCFGR1_BRAM_SIZE_11 (0x0800UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00000800 */ -#define HSP_HWCFGR1_BRAM_SIZE_12 (0x1000UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00001000 */ -#define HSP_HWCFGR1_BRAM_SIZE_13 (0x2000UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00002000 */ -#define HSP_HWCFGR1_BRAM_SIZE_14 (0x4000UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00004000 */ -#define HSP_HWCFGR1_BRAM_SIZE_15 (0x8000UL << HSP_HWCFGR1_BRAM_SIZE_Pos) /*!< 0x00008000 */ -/*!< DRAM_SIZE configuration */ -#define HSP_HWCFGR1_DRAM_SIZE_Pos (16U) -#define HSP_HWCFGR1_DRAM_SIZE_Msk (0xFFUL << HSP_HWCFGR1_DRAM_SIZE_Pos) /*!< 0x00FF0000 */ -#define HSP_HWCFGR1_DRAM_SIZE HSP_HWCFGR1_DRAM_SIZE_Msk /*!< DRAM_SIZE[7:0] bits (DRAM Size) */ -#define HSP_HWCFGR1_DRAM_SIZE_0 (0x001UL << HSP_HWCFGR1_DRAM_SIZE_Pos) /*!< 0x00010000 */ -#define HSP_HWCFGR1_DRAM_SIZE_1 (0x002UL << HSP_HWCFGR1_DRAM_SIZE_Pos) /*!< 0x00020000 */ -#define HSP_HWCFGR1_DRAM_SIZE_2 (0x004UL << HSP_HWCFGR1_DRAM_SIZE_Pos) /*!< 0x00040000 */ -#define HSP_HWCFGR1_DRAM_SIZE_3 (0x008UL << HSP_HWCFGR1_DRAM_SIZE_Pos) /*!< 0x00080000 */ -#define HSP_HWCFGR1_DRAM_SIZE_4 (0x010UL << HSP_HWCFGR1_DRAM_SIZE_Pos) /*!< 0x00100000 */ -#define HSP_HWCFGR1_DRAM_SIZE_5 (0x020UL << HSP_HWCFGR1_DRAM_SIZE_Pos) /*!< 0x00200000 */ -#define HSP_HWCFGR1_DRAM_SIZE_6 (0x040UL << HSP_HWCFGR1_DRAM_SIZE_Pos) /*!< 0x00400000 */ -#define HSP_HWCFGR1_DRAM_SIZE_7 (0x080UL << HSP_HWCFGR1_DRAM_SIZE_Pos) /*!< 0x00800000 */ -/*!< CRAM_SIZE configuration */ -#define HSP_HWCFGR1_CRAM_SIZE_Pos (24U) -#define HSP_HWCFGR1_CRAM_SIZE_Msk (0xFFUL << HSP_HWCFGR1_CRAM_SIZE_Pos) /*!< 0xFF000000 */ -#define HSP_HWCFGR1_CRAM_SIZE HSP_HWCFGR1_CRAM_SIZE_Msk /*!< CRAM_SIZE[7:0] bits (CRAM Size) */ -#define HSP_HWCFGR1_CRAM_SIZE_0 (0x001UL << HSP_HWCFGR1_CRAM_SIZE_Pos) /*!< 0x01000000 */ -#define HSP_HWCFGR1_CRAM_SIZE_1 (0x002UL << HSP_HWCFGR1_CRAM_SIZE_Pos) /*!< 0x02000000 */ -#define HSP_HWCFGR1_CRAM_SIZE_2 (0x004UL << HSP_HWCFGR1_CRAM_SIZE_Pos) /*!< 0x04000000 */ -#define HSP_HWCFGR1_CRAM_SIZE_3 (0x008UL << HSP_HWCFGR1_CRAM_SIZE_Pos) /*!< 0x08000000 */ -#define HSP_HWCFGR1_CRAM_SIZE_4 (0x010UL << HSP_HWCFGR1_CRAM_SIZE_Pos) /*!< 0x10000000 */ -#define HSP_HWCFGR1_CRAM_SIZE_5 (0x020UL << HSP_HWCFGR1_CRAM_SIZE_Pos) /*!< 0x20000000 */ -#define HSP_HWCFGR1_CRAM_SIZE_6 (0x040UL << HSP_HWCFGR1_CRAM_SIZE_Pos) /*!< 0x40000000 */ -#define HSP_HWCFGR1_CRAM_SIZE_7 (0x080UL << HSP_HWCFGR1_CRAM_SIZE_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for HSP_VERR register ********************/ -/*!< MINREV configuration */ -#define HSP_VERR_MINREV_Pos (0U) -#define HSP_VERR_MINREV_Msk (0xFUL << HSP_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define HSP_VERR_MINREV HSP_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */ -#define HSP_VERR_MINREV_0 (0x01UL << HSP_VERR_MINREV_Pos) /*!< 0x00000001 */ -#define HSP_VERR_MINREV_1 (0x02UL << HSP_VERR_MINREV_Pos) /*!< 0x00000002 */ -#define HSP_VERR_MINREV_2 (0x04UL << HSP_VERR_MINREV_Pos) /*!< 0x00000004 */ -#define HSP_VERR_MINREV_3 (0x08UL << HSP_VERR_MINREV_Pos) /*!< 0x00000008 */ -/*!< MAJREV configuration */ -#define HSP_VERR_MAJREV_Pos (4U) -#define HSP_VERR_MAJREV_Msk (0xFUL << HSP_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define HSP_VERR_MAJREV HSP_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */ -#define HSP_VERR_MAJREV_0 (0x01UL << HSP_VERR_MAJREV_Pos) /*!< 0x00000010 */ -#define HSP_VERR_MAJREV_1 (0x02UL << HSP_VERR_MAJREV_Pos) /*!< 0x00000020 */ -#define HSP_VERR_MAJREV_2 (0x04UL << HSP_VERR_MAJREV_Pos) /*!< 0x00000040 */ -#define HSP_VERR_MAJREV_3 (0x08UL << HSP_VERR_MAJREV_Pos) /*!< 0x00000080 */ - -/******************** Bit definition for HSP_IPIDR register ********************/ -/*!< ID configuration */ -#define HSP_IPIDR_ID_Pos (0U) -#define HSP_IPIDR_ID_Msk (0xFFFFFFFFUL << HSP_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */ -#define HSP_IPIDR_ID HSP_IPIDR_ID_Msk /*!< ID[31:0] bits (HSP identifier) */ -#define HSP_IPIDR_ID_0 (0x00001UL << HSP_IPIDR_ID_Pos) /*!< 0x00000001 */ -#define HSP_IPIDR_ID_1 (0x00002UL << HSP_IPIDR_ID_Pos) /*!< 0x00000002 */ -#define HSP_IPIDR_ID_2 (0x00004UL << HSP_IPIDR_ID_Pos) /*!< 0x00000004 */ -#define HSP_IPIDR_ID_3 (0x00008UL << HSP_IPIDR_ID_Pos) /*!< 0x00000008 */ -#define HSP_IPIDR_ID_4 (0x00010UL << HSP_IPIDR_ID_Pos) /*!< 0x00000010 */ -#define HSP_IPIDR_ID_5 (0x00020UL << HSP_IPIDR_ID_Pos) /*!< 0x00000020 */ -#define HSP_IPIDR_ID_6 (0x00040UL << HSP_IPIDR_ID_Pos) /*!< 0x00000040 */ -#define HSP_IPIDR_ID_7 (0x00080UL << HSP_IPIDR_ID_Pos) /*!< 0x00000080 */ -#define HSP_IPIDR_ID_8 (0x00100UL << HSP_IPIDR_ID_Pos) /*!< 0x00000100 */ -#define HSP_IPIDR_ID_9 (0x00200UL << HSP_IPIDR_ID_Pos) /*!< 0x00000200 */ -#define HSP_IPIDR_ID_10 (0x00400UL << HSP_IPIDR_ID_Pos) /*!< 0x00000400 */ -#define HSP_IPIDR_ID_11 (0x00800UL << HSP_IPIDR_ID_Pos) /*!< 0x00000800 */ -#define HSP_IPIDR_ID_12 (0x01000UL << HSP_IPIDR_ID_Pos) /*!< 0x00001000 */ -#define HSP_IPIDR_ID_13 (0x02000UL << HSP_IPIDR_ID_Pos) /*!< 0x00002000 */ -#define HSP_IPIDR_ID_14 (0x04000UL << HSP_IPIDR_ID_Pos) /*!< 0x00004000 */ -#define HSP_IPIDR_ID_15 (0x08000UL << HSP_IPIDR_ID_Pos) /*!< 0x00008000 */ -#define HSP_IPIDR_ID_16 (0x10000UL << HSP_IPIDR_ID_Pos) /*!< 0x00010000 */ -#define HSP_IPIDR_ID_17 (0x20000UL << HSP_IPIDR_ID_Pos) /*!< 0x00020000 */ -#define HSP_IPIDR_ID_18 (0x40000UL << HSP_IPIDR_ID_Pos) /*!< 0x00040000 */ -#define HSP_IPIDR_ID_19 (0x80000UL << HSP_IPIDR_ID_Pos) /*!< 0x00080000 */ -#define HSP_IPIDR_ID_20 (0x100000UL << HSP_IPIDR_ID_Pos) /*!< 0x00100000 */ -#define HSP_IPIDR_ID_21 (0x200000UL << HSP_IPIDR_ID_Pos) /*!< 0x00200000 */ -#define HSP_IPIDR_ID_22 (0x400000UL << HSP_IPIDR_ID_Pos) /*!< 0x00400000 */ -#define HSP_IPIDR_ID_23 (0x800000UL << HSP_IPIDR_ID_Pos) /*!< 0x00800000 */ -#define HSP_IPIDR_ID_24 (0x1000000UL << HSP_IPIDR_ID_Pos) /*!< 0x01000000 */ -#define HSP_IPIDR_ID_25 (0x2000000UL << HSP_IPIDR_ID_Pos) /*!< 0x02000000 */ -#define HSP_IPIDR_ID_26 (0x4000000UL << HSP_IPIDR_ID_Pos) /*!< 0x04000000 */ -#define HSP_IPIDR_ID_27 (0x8000000UL << HSP_IPIDR_ID_Pos) /*!< 0x08000000 */ -#define HSP_IPIDR_ID_28 (0x10000000UL << HSP_IPIDR_ID_Pos) /*!< 0x10000000 */ -#define HSP_IPIDR_ID_29 (0x20000000UL << HSP_IPIDR_ID_Pos) /*!< 0x20000000 */ -#define HSP_IPIDR_ID_30 (0x40000000UL << HSP_IPIDR_ID_Pos) /*!< 0x40000000 */ -#define HSP_IPIDR_ID_31 (0x80000000UL << HSP_IPIDR_ID_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for HSP_SIDR register ********************/ -/*!< SID configuration */ -#define HSP_SIDR_SID_Pos (0U) -#define HSP_SIDR_SID_Msk (0xFFFFFFFFUL << HSP_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ -#define HSP_SIDR_SID HSP_SIDR_SID_Msk /*!< SID[31:0] bits (Size identification) */ -#define HSP_SIDR_SID_0 (0x00001UL << HSP_SIDR_SID_Pos) /*!< 0x00000001 */ -#define HSP_SIDR_SID_1 (0x00002UL << HSP_SIDR_SID_Pos) /*!< 0x00000002 */ -#define HSP_SIDR_SID_2 (0x00004UL << HSP_SIDR_SID_Pos) /*!< 0x00000004 */ -#define HSP_SIDR_SID_3 (0x00008UL << HSP_SIDR_SID_Pos) /*!< 0x00000008 */ -#define HSP_SIDR_SID_4 (0x00010UL << HSP_SIDR_SID_Pos) /*!< 0x00000010 */ -#define HSP_SIDR_SID_5 (0x00020UL << HSP_SIDR_SID_Pos) /*!< 0x00000020 */ -#define HSP_SIDR_SID_6 (0x00040UL << HSP_SIDR_SID_Pos) /*!< 0x00000040 */ -#define HSP_SIDR_SID_7 (0x00080UL << HSP_SIDR_SID_Pos) /*!< 0x00000080 */ -#define HSP_SIDR_SID_8 (0x00100UL << HSP_SIDR_SID_Pos) /*!< 0x00000100 */ -#define HSP_SIDR_SID_9 (0x00200UL << HSP_SIDR_SID_Pos) /*!< 0x00000200 */ -#define HSP_SIDR_SID_10 (0x00400UL << HSP_SIDR_SID_Pos) /*!< 0x00000400 */ -#define HSP_SIDR_SID_11 (0x00800UL << HSP_SIDR_SID_Pos) /*!< 0x00000800 */ -#define HSP_SIDR_SID_12 (0x01000UL << HSP_SIDR_SID_Pos) /*!< 0x00001000 */ -#define HSP_SIDR_SID_13 (0x02000UL << HSP_SIDR_SID_Pos) /*!< 0x00002000 */ -#define HSP_SIDR_SID_14 (0x04000UL << HSP_SIDR_SID_Pos) /*!< 0x00004000 */ -#define HSP_SIDR_SID_15 (0x08000UL << HSP_SIDR_SID_Pos) /*!< 0x00008000 */ -#define HSP_SIDR_SID_16 (0x10000UL << HSP_SIDR_SID_Pos) /*!< 0x00010000 */ -#define HSP_SIDR_SID_17 (0x20000UL << HSP_SIDR_SID_Pos) /*!< 0x00020000 */ -#define HSP_SIDR_SID_18 (0x40000UL << HSP_SIDR_SID_Pos) /*!< 0x00040000 */ -#define HSP_SIDR_SID_19 (0x80000UL << HSP_SIDR_SID_Pos) /*!< 0x00080000 */ -#define HSP_SIDR_SID_20 (0x100000UL << HSP_SIDR_SID_Pos) /*!< 0x00100000 */ -#define HSP_SIDR_SID_21 (0x200000UL << HSP_SIDR_SID_Pos) /*!< 0x00200000 */ -#define HSP_SIDR_SID_22 (0x400000UL << HSP_SIDR_SID_Pos) /*!< 0x00400000 */ -#define HSP_SIDR_SID_23 (0x800000UL << HSP_SIDR_SID_Pos) /*!< 0x00800000 */ -#define HSP_SIDR_SID_24 (0x1000000UL << HSP_SIDR_SID_Pos) /*!< 0x01000000 */ -#define HSP_SIDR_SID_25 (0x2000000UL << HSP_SIDR_SID_Pos) /*!< 0x02000000 */ -#define HSP_SIDR_SID_26 (0x4000000UL << HSP_SIDR_SID_Pos) /*!< 0x04000000 */ -#define HSP_SIDR_SID_27 (0x8000000UL << HSP_SIDR_SID_Pos) /*!< 0x08000000 */ -#define HSP_SIDR_SID_28 (0x10000000UL << HSP_SIDR_SID_Pos) /*!< 0x10000000 */ -#define HSP_SIDR_SID_29 (0x20000000UL << HSP_SIDR_SID_Pos) /*!< 0x20000000 */ -#define HSP_SIDR_SID_30 (0x40000000UL << HSP_SIDR_SID_Pos) /*!< 0x40000000 */ -#define HSP_SIDR_SID_31 (0x80000000UL << HSP_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -14194,303 +14427,303 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for I2C_CR1 register *******************/ -#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Pos (0UL) #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ -#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Pos (1UL) #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ -#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Pos (2UL) #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ -#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Pos (3UL) #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ -#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Pos (4UL) #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ -#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Pos (5UL) #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ -#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Pos (6UL) #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ -#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Pos (7UL) #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ -#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Pos (8UL) #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ -#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Pos (12UL) #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ -#define I2C_CR1_SWRST_Pos (13U) +#define I2C_CR1_SWRST_Pos (13UL) #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ -#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Pos (14UL) #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ -#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Pos (15UL) #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ -#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Pos (16UL) #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ -#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Pos (17UL) #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ -#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Pos (18UL) #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ -#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Pos (19UL) #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ -#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Pos (20UL) #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ -#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Pos (21UL) #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ -#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Pos (22UL) #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ -#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Pos (23UL) #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ -#define I2C_CR1_FMP_Pos (24U) +#define I2C_CR1_FMP_Pos (24UL) #define I2C_CR1_FMP_Msk (0x1UL << I2C_CR1_FMP_Pos) /*!< 0x01000000 */ #define I2C_CR1_FMP I2C_CR1_FMP_Msk /*!< FMP enable */ -#define I2C_CR1_ADDRACLR_Pos (30U) +#define I2C_CR1_ADDRACLR_Pos (30UL) #define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ #define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ -#define I2C_CR1_STOPFACLR_Pos (31U) +#define I2C_CR1_STOPFACLR_Pos (31UL) #define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ #define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ /****************** Bit definition for I2C_CR2 register ********************/ -#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Pos (0UL) #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ -#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Pos (10UL) #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ -#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Pos (11UL) #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ -#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Pos (12UL) #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ -#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Pos (13UL) #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ -#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Pos (14UL) #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ -#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Pos (15UL) #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ -#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Pos (16UL) #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ -#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Pos (24UL) #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ -#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Pos (25UL) #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ -#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Pos (26UL) #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ /******************* Bit definition for I2C_OAR1 register ******************/ -#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Pos (0UL) #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ -#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Pos (10UL) #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ -#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Pos (15UL) #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ /******************* Bit definition for I2C_OAR2 register ******************/ -#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Pos (1UL) #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ -#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Pos (8UL) #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ #define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */ -#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Pos (8UL) #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ -#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Pos (9UL) #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ -#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Pos (8UL) #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ -#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Pos (10UL) #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ -#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Pos (8UL) #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ -#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Pos (9UL) #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ -#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Pos (8UL) #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ -#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Pos (15UL) #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ /******************* Bit definition for I2C_TIMINGR register *******************/ -#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Pos (0UL) #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ -#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Pos (8UL) #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ -#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Pos (16UL) #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ -#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Pos (20UL) #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ -#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Pos (28UL) #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ /******************* Bit definition for I2C_TIMEOUTR register *******************/ -#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0UL) #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ -#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Pos (12UL) #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ -#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15UL) #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ -#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16UL) #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ -#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Pos (31UL) #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ /****************** Bit definition for I2C_ISR register *********************/ -#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Pos (0UL) #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ -#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Pos (1UL) #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ -#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Pos (2UL) #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ -#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Pos (3UL) #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ -#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Pos (4UL) #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ -#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Pos (5UL) #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ -#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Pos (6UL) #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ -#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Pos (7UL) #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ -#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Pos (8UL) #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ -#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Pos (9UL) #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ -#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Pos (10UL) #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ -#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Pos (11UL) #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ -#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Pos (12UL) #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ -#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Pos (13UL) #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ -#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Pos (15UL) #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ -#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Pos (16UL) #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ -#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Pos (17UL) #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ /****************** Bit definition for I2C_ICR register *********************/ -#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Pos (3UL) #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ -#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Pos (4UL) #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ -#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Pos (5UL) #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ -#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Pos (8UL) #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ -#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Pos (9UL) #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ -#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Pos (10UL) #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ -#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Pos (11UL) #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ -#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Pos (12UL) #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ -#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Pos (13UL) #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ /****************** Bit definition for I2C_PECR register *********************/ -#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Pos (0UL) #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ /****************** Bit definition for I2C_RXDR register *********************/ -#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Pos (0UL) #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ /****************** Bit definition for I2C_TXDR register *********************/ -#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Pos (0UL) #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ /****************** Bit definition for I2C_AUTOCR register ********************/ -#define I2C_AUTOCR_TCDMAEN_Pos (6U) +#define I2C_AUTOCR_TCDMAEN_Pos (6UL) #define I2C_AUTOCR_TCDMAEN_Msk (0x1UL << I2C_AUTOCR_TCDMAEN_Pos) /*!< 0x00000040 */ #define I2C_AUTOCR_TCDMAEN I2C_AUTOCR_TCDMAEN_Msk /*!< DMA request enable on Transfer Complete event */ -#define I2C_AUTOCR_TCRDMAEN_Pos (7U) +#define I2C_AUTOCR_TCRDMAEN_Pos (7UL) #define I2C_AUTOCR_TCRDMAEN_Msk (0x1UL << I2C_AUTOCR_TCRDMAEN_Pos) /*!< 0x00000080 */ #define I2C_AUTOCR_TCRDMAEN I2C_AUTOCR_TCRDMAEN_Msk /*!< DMA request enable on Transfer Complete Reload event */ -#define I2C_AUTOCR_TRIGSEL_Pos (16U) +#define I2C_AUTOCR_TRIGSEL_Pos (16UL) #define I2C_AUTOCR_TRIGSEL_Msk (0xFUL << I2C_AUTOCR_TRIGSEL_Pos) /*!< 0x000F0000 */ #define I2C_AUTOCR_TRIGSEL I2C_AUTOCR_TRIGSEL_Msk /*!< Trigger selection */ -#define I2C_AUTOCR_TRIGPOL_Pos (20U) +#define I2C_AUTOCR_TRIGPOL_Pos (20UL) #define I2C_AUTOCR_TRIGPOL_Msk (0x1UL << I2C_AUTOCR_TRIGPOL_Pos) /*!< 0x000100000 */ #define I2C_AUTOCR_TRIGPOL I2C_AUTOCR_TRIGPOL_Msk /*!< Trigger polarity */ -#define I2C_AUTOCR_TRIGEN_Pos (21U) +#define I2C_AUTOCR_TRIGEN_Pos (21UL) #define I2C_AUTOCR_TRIGEN_Msk (0x1UL << I2C_AUTOCR_TRIGEN_Pos) /*!< 0x000200000 */ #define I2C_AUTOCR_TRIGEN I2C_AUTOCR_TRIGEN_Msk /*!< Trigger enable */ @@ -14500,566 +14733,566 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for I3C_CR register *********************/ -#define I3C_CR_DCNT_Pos (0U) +#define I3C_CR_DCNT_Pos (0UL) #define I3C_CR_DCNT_Msk (0xFFFFUL << I3C_CR_DCNT_Pos) /*!< 0x0000FFFF */ #define I3C_CR_DCNT I3C_CR_DCNT_Msk /*!< Data Byte Count */ -#define I3C_CR_RNW_Pos (16U) +#define I3C_CR_RNW_Pos (16UL) #define I3C_CR_RNW_Msk (0x1UL << I3C_CR_RNW_Pos) /*!< 0x00010000 */ #define I3C_CR_RNW I3C_CR_RNW_Msk /*!< Read Not Write */ -#define I3C_CR_CCC_Pos (16U) +#define I3C_CR_CCC_Pos (16UL) #define I3C_CR_CCC_Msk (0xFFUL << I3C_CR_CCC_Pos) /*!< 0x00FF0000 */ #define I3C_CR_CCC I3C_CR_CCC_Msk /*!< 8-Bit CCC code */ -#define I3C_CR_ADD_Pos (17U) +#define I3C_CR_ADD_Pos (17UL) #define I3C_CR_ADD_Msk (0x7FUL << I3C_CR_ADD_Pos) /*!< 0x00FE0000 */ #define I3C_CR_ADD I3C_CR_ADD_Msk /*!< Target Address */ -#define I3C_CR_MTYPE_Pos (27U) +#define I3C_CR_MTYPE_Pos (27UL) #define I3C_CR_MTYPE_Msk (0xFUL << I3C_CR_MTYPE_Pos) /*!< 0xF8000000 */ #define I3C_CR_MTYPE I3C_CR_MTYPE_Msk /*!< Message Type */ #define I3C_CR_MTYPE_0 (0x1UL << I3C_CR_MTYPE_Pos) /*!< 0x08000000 */ #define I3C_CR_MTYPE_1 (0x2UL << I3C_CR_MTYPE_Pos) /*!< 0x10000000 */ #define I3C_CR_MTYPE_2 (0x4UL << I3C_CR_MTYPE_Pos) /*!< 0x20000000 */ #define I3C_CR_MTYPE_3 (0x8UL << I3C_CR_MTYPE_Pos) /*!< 0x40000000 */ -#define I3C_CR_MEND_Pos (31U) +#define I3C_CR_MEND_Pos (31UL) #define I3C_CR_MEND_Msk (0x1UL << I3C_CR_MEND_Pos) /*!< 0x80000000 */ #define I3C_CR_MEND I3C_CR_MEND_Msk /*!< Message End */ /******************* Bit definition for I3C_CFGR register *******************/ -#define I3C_CFGR_EN_Pos (0U) +#define I3C_CFGR_EN_Pos (0UL) #define I3C_CFGR_EN_Msk (0x1UL << I3C_CFGR_EN_Pos) /*!< 0x00000001 */ #define I3C_CFGR_EN I3C_CFGR_EN_Msk /*!< Peripheral Enable */ -#define I3C_CFGR_CRINIT_Pos (1U) +#define I3C_CFGR_CRINIT_Pos (1UL) #define I3C_CFGR_CRINIT_Msk (0x1UL << I3C_CFGR_CRINIT_Pos) /*!< 0x00000002 */ #define I3C_CFGR_CRINIT I3C_CFGR_CRINIT_Msk /*!< Peripheral Init mode (Target/Controller) */ -#define I3C_CFGR_NOARBH_Pos (2U) +#define I3C_CFGR_NOARBH_Pos (2UL) #define I3C_CFGR_NOARBH_Msk (0x1UL << I3C_CFGR_NOARBH_Pos) /*!< 0x00000004 */ #define I3C_CFGR_NOARBH I3C_CFGR_NOARBH_Msk /*!< No Arbitration Header (7'h7E)*/ -#define I3C_CFGR_RSTPTRN_Pos (3U) +#define I3C_CFGR_RSTPTRN_Pos (3UL) #define I3C_CFGR_RSTPTRN_Msk (0x1UL << I3C_CFGR_RSTPTRN_Pos) /*!< 0x00000008 */ #define I3C_CFGR_RSTPTRN I3C_CFGR_RSTPTRN_Msk /*!< Reset Pattern enable */ -#define I3C_CFGR_EXITPTRN_Pos (4U) +#define I3C_CFGR_EXITPTRN_Pos (4UL) #define I3C_CFGR_EXITPTRN_Msk (0x1UL << I3C_CFGR_EXITPTRN_Pos) /*!< 0x00000010 */ #define I3C_CFGR_EXITPTRN I3C_CFGR_EXITPTRN_Msk /*!< Exit Pattern enable */ -#define I3C_CFGR_HKSDAEN_Pos (5U) +#define I3C_CFGR_HKSDAEN_Pos (5UL) #define I3C_CFGR_HKSDAEN_Msk (0x1UL << I3C_CFGR_HKSDAEN_Pos) /*!< 0x00000020 */ #define I3C_CFGR_HKSDAEN I3C_CFGR_HKSDAEN_Msk /*!< High-Keeper on SDA Enable */ -#define I3C_CFGR_HJACK_Pos (7U) +#define I3C_CFGR_HJACK_Pos (7UL) #define I3C_CFGR_HJACK_Msk (0x1UL << I3C_CFGR_HJACK_Pos) /*!< 0x00000080 */ #define I3C_CFGR_HJACK I3C_CFGR_HJACK_Msk /*!< Hot Join Acknowledgment */ -#define I3C_CFGR_RXDMAEN_Pos (8U) +#define I3C_CFGR_RXDMAEN_Pos (8UL) #define I3C_CFGR_RXDMAEN_Msk (0x1UL << I3C_CFGR_RXDMAEN_Pos) /*!< 0x00000100 */ #define I3C_CFGR_RXDMAEN I3C_CFGR_RXDMAEN_Msk /*!< RX FIFO DMA mode Enable */ -#define I3C_CFGR_RXFLUSH_Pos (9U) +#define I3C_CFGR_RXFLUSH_Pos (9UL) #define I3C_CFGR_RXFLUSH_Msk (0x1UL << I3C_CFGR_RXFLUSH_Pos) /*!< 0x00000200 */ #define I3C_CFGR_RXFLUSH I3C_CFGR_RXFLUSH_Msk /*!< RX FIFO Flush */ -#define I3C_CFGR_RXTHRES_Pos (10U) +#define I3C_CFGR_RXTHRES_Pos (10UL) #define I3C_CFGR_RXTHRES_Msk (0x1UL << I3C_CFGR_RXTHRES_Pos) /*!< 0x00000400 */ #define I3C_CFGR_RXTHRES I3C_CFGR_RXTHRES_Msk /*!< RX FIFO Threshold */ -#define I3C_CFGR_TXDMAEN_Pos (12U) +#define I3C_CFGR_TXDMAEN_Pos (12UL) #define I3C_CFGR_TXDMAEN_Msk (0x1UL << I3C_CFGR_TXDMAEN_Pos) /*!< 0x00001000 */ #define I3C_CFGR_TXDMAEN I3C_CFGR_TXDMAEN_Msk /*!< TX FIFO DMA mode Enable */ -#define I3C_CFGR_TXFLUSH_Pos (13U) +#define I3C_CFGR_TXFLUSH_Pos (13UL) #define I3C_CFGR_TXFLUSH_Msk (0x1UL << I3C_CFGR_TXFLUSH_Pos) /*!< 0x00002000 */ #define I3C_CFGR_TXFLUSH I3C_CFGR_TXFLUSH_Msk /*!< TX FIFO Flush */ -#define I3C_CFGR_TXTHRES_Pos (14U) +#define I3C_CFGR_TXTHRES_Pos (14UL) #define I3C_CFGR_TXTHRES_Msk (0x1UL << I3C_CFGR_TXTHRES_Pos) /*!< 0x00004000 */ #define I3C_CFGR_TXTHRES I3C_CFGR_TXTHRES_Msk /*!< TX FIFO Threshold */ -#define I3C_CFGR_SDMAEN_Pos (16U) +#define I3C_CFGR_SDMAEN_Pos (16UL) #define I3C_CFGR_SDMAEN_Msk (0x1UL << I3C_CFGR_SDMAEN_Pos) /*!< 0x00010000 */ #define I3C_CFGR_SDMAEN I3C_CFGR_SDMAEN_Msk /*!< Status FIFO DMA mode Enable */ -#define I3C_CFGR_SFLUSH_Pos (17U) +#define I3C_CFGR_SFLUSH_Pos (17UL) #define I3C_CFGR_SFLUSH_Msk (0x1UL << I3C_CFGR_SFLUSH_Pos) /*!< 0x00020000 */ #define I3C_CFGR_SFLUSH I3C_CFGR_SFLUSH_Msk /*!< Status FIFO Flush */ -#define I3C_CFGR_SMODE_Pos (18U) +#define I3C_CFGR_SMODE_Pos (18UL) #define I3C_CFGR_SMODE_Msk (0x1UL << I3C_CFGR_SMODE_Pos) /*!< 0x00040000 */ #define I3C_CFGR_SMODE I3C_CFGR_SMODE_Msk /*!< Status FIFO mode Enable */ -#define I3C_CFGR_TMODE_Pos (19U) +#define I3C_CFGR_TMODE_Pos (19UL) #define I3C_CFGR_TMODE_Msk (0x1UL << I3C_CFGR_TMODE_Pos) /*!< 0x00080000 */ #define I3C_CFGR_TMODE I3C_CFGR_TMODE_Msk /*!< Control FIFO mode Enable */ -#define I3C_CFGR_CDMAEN_Pos (20U) +#define I3C_CFGR_CDMAEN_Pos (20UL) #define I3C_CFGR_CDMAEN_Msk (0x1UL << I3C_CFGR_CDMAEN_Pos) /*!< 0x00100000 */ #define I3C_CFGR_CDMAEN I3C_CFGR_CDMAEN_Msk /*!< Control FIFO DMA mode Enable */ -#define I3C_CFGR_CFLUSH_Pos (21U) +#define I3C_CFGR_CFLUSH_Pos (21UL) #define I3C_CFGR_CFLUSH_Msk (0x1UL << I3C_CFGR_CFLUSH_Pos) /*!< 0x00200000 */ #define I3C_CFGR_CFLUSH I3C_CFGR_CFLUSH_Msk /*!< Control FIFO Flush */ -#define I3C_CFGR_FCFDIS_Pos (23U) +#define I3C_CFGR_FCFDIS_Pos (23UL) #define I3C_CFGR_FCFDIS_Msk (0x1UL << I3C_CFGR_FCFDIS_Pos) /*!< 0x00800000 */ #define I3C_CFGR_FCFDIS I3C_CFGR_FCFDIS_Msk /*!< FCF generation disable */ -#define I3C_CFGR_TRIGSEL_Pos (24U) +#define I3C_CFGR_TRIGSEL_Pos (24UL) #define I3C_CFGR_TRIGSEL_Msk (0xFUL << I3C_CFGR_TRIGSEL_Pos) /*!< 0x0F000000 */ #define I3C_CFGR_TRIGSEL I3C_CFGR_TRIGSEL_Msk /*!< Trigger selection */ -#define I3C_CFGR_TRIGPOL_Pos (28U) +#define I3C_CFGR_TRIGPOL_Pos (28UL) #define I3C_CFGR_TRIGPOL_Msk (0x1UL << I3C_CFGR_TRIGPOL_Pos) /*!< 0x10000000 */ #define I3C_CFGR_TRIGPOL I3C_CFGR_TRIGPOL_Msk /*!< Trigger polarity */ -#define I3C_CFGR_TRIGHWEN_Pos (29U) +#define I3C_CFGR_TRIGHWEN_Pos (29UL) #define I3C_CFGR_TRIGHWEN_Msk (0x1UL << I3C_CFGR_TRIGHWEN_Pos) /*!< 0x20000000 */ #define I3C_CFGR_TRIGHWEN I3C_CFGR_TRIGHWEN_Msk /*!< Trigger enable */ -#define I3C_CFGR_TSFSET_Pos (30U) +#define I3C_CFGR_TSFSET_Pos (30UL) #define I3C_CFGR_TSFSET_Msk (0x1UL << I3C_CFGR_TSFSET_Pos) /*!< 0x40000000 */ #define I3C_CFGR_TSFSET I3C_CFGR_TSFSET_Msk /*!< Transfer Set */ /******************* Bit definition for I3C_RDR register ********************/ -#define I3C_RDR_RDB0_Pos (0U) +#define I3C_RDR_RDB0_Pos (0UL) #define I3C_RDR_RDB0_Msk (0xFFUL << I3C_RDR_RDB0_Pos) /*!< 0x000000FF */ #define I3C_RDR_RDB0 I3C_RDR_RDB0_Msk /*!< Receive Data Byte */ /****************** Bit definition for I3C_RDWR register ********************/ -#define I3C_RDWR_RDBx_Pos (0U) +#define I3C_RDWR_RDBx_Pos (0UL) #define I3C_RDWR_RDBx_Msk (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos) /*!< 0xFFFFFFFF */ #define I3C_RDWR_RDBx I3C_RDWR_RDBx_Msk /*!< Receive Data Byte, full double word */ -#define I3C_RDWR_RDB0_Pos (0U) +#define I3C_RDWR_RDB0_Pos (0UL) #define I3C_RDWR_RDB0_Msk (0xFFUL << I3C_RDWR_RDB0_Pos) /*!< 0x000000FF */ #define I3C_RDWR_RDB0 I3C_RDWR_RDB0_Msk /*!< Receive Data Byte 0 */ -#define I3C_RDWR_RDB1_Pos (8U) +#define I3C_RDWR_RDB1_Pos (8UL) #define I3C_RDWR_RDB1_Msk (0xFFUL << I3C_RDWR_RDB1_Pos) /*!< 0x0000FF00 */ #define I3C_RDWR_RDB1 I3C_RDWR_RDB1_Msk /*!< Receive Data Byte 1 */ -#define I3C_RDWR_RDB2_Pos (16U) +#define I3C_RDWR_RDB2_Pos (16UL) #define I3C_RDWR_RDB2_Msk (0xFFUL << I3C_RDWR_RDB2_Pos) /*!< 0x00FF0000 */ #define I3C_RDWR_RDB2 I3C_RDWR_RDB2_Msk /*!< Receive Data Byte 2 */ -#define I3C_RDWR_RDB3_Pos (24U) +#define I3C_RDWR_RDB3_Pos (24UL) #define I3C_RDWR_RDB3_Msk (0xFFUL << I3C_RDWR_RDB3_Pos) /*!< 0xFF000000 */ #define I3C_RDWR_RDB3 I3C_RDWR_RDB3_Msk /*!< Receive Data Byte 3 */ /******************* Bit definition for I3C_TDR register ********************/ -#define I3C_TDR_TDB0_Pos (0U) +#define I3C_TDR_TDB0_Pos (0UL) #define I3C_TDR_TDB0_Msk (0xFFUL << I3C_TDR_TDB0_Pos) /*!< 0x000000FF */ #define I3C_TDR_TDB0 I3C_TDR_TDB0_Msk /*!< Transmit Data Byte */ /****************** Bit definition for I3C_TDWR register ********************/ -#define I3C_TDWR_TDBx_Pos (0U) +#define I3C_TDWR_TDBx_Pos (0UL) #define I3C_TDWR_TDBx_Msk (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos) /*!< 0xFFFFFFFF */ #define I3C_TDWR_TDBx I3C_TDWR_TDBx_Msk /*!< Transmit Data Byte, full double word */ -#define I3C_TDWR_TDB0_Pos (0U) +#define I3C_TDWR_TDB0_Pos (0UL) #define I3C_TDWR_TDB0_Msk (0xFFUL << I3C_TDWR_TDB0_Pos) /*!< 0x000000FF */ #define I3C_TDWR_TDB0 I3C_TDWR_TDB0_Msk /*!< Transmit Data Byte 0 */ -#define I3C_TDWR_TDB1_Pos (8U) +#define I3C_TDWR_TDB1_Pos (8UL) #define I3C_TDWR_TDB1_Msk (0xFFUL << I3C_TDWR_TDB1_Pos) /*!< 0x0000FF00 */ #define I3C_TDWR_TDB1 I3C_TDWR_TDB1_Msk /*!< Transmit Data Byte 1 */ -#define I3C_TDWR_TDB2_Pos (16U) +#define I3C_TDWR_TDB2_Pos (16UL) #define I3C_TDWR_TDB2_Msk (0xFFUL << I3C_TDWR_TDB2_Pos) /*!< 0x00FF0000 */ #define I3C_TDWR_TDB2 I3C_TDWR_TDB2_Msk /*!< Transmit Data Byte 2 */ -#define I3C_TDWR_TDB3_Pos (24U) +#define I3C_TDWR_TDB3_Pos (24UL) #define I3C_TDWR_TDB3_Msk (0xFFUL << I3C_TDWR_TDB3_Pos) /*!< 0xFF000000 */ #define I3C_TDWR_TDB3 I3C_TDWR_TDB3_Msk /*!< Transmit Data Byte 3 */ /******************* Bit definition for I3C_IBIDR register ******************/ -#define I3C_IBIDR_IBIDBx_Pos (0U) +#define I3C_IBIDR_IBIDBx_Pos (0UL) #define I3C_IBIDR_IBIDBx_Msk (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos) /*!< 0xFFFFFFFF */ #define I3C_IBIDR_IBIDBx I3C_IBIDR_IBIDBx_Msk /*!< IBI Data Byte, full double word */ -#define I3C_IBIDR_IBIDB0_Pos (0U) +#define I3C_IBIDR_IBIDB0_Pos (0UL) #define I3C_IBIDR_IBIDB0_Msk (0xFFUL << I3C_IBIDR_IBIDB0_Pos) /*!< 0x000000FF */ #define I3C_IBIDR_IBIDB0 I3C_IBIDR_IBIDB0_Msk /*!< IBI Data Byte 0 */ -#define I3C_IBIDR_IBIDB1_Pos (8U) +#define I3C_IBIDR_IBIDB1_Pos (8UL) #define I3C_IBIDR_IBIDB1_Msk (0xFFUL << I3C_IBIDR_IBIDB1_Pos) /*!< 0x0000FF00 */ #define I3C_IBIDR_IBIDB1 I3C_IBIDR_IBIDB1_Msk /*!< IBI Data Byte 1 */ -#define I3C_IBIDR_IBIDB2_Pos (16U) +#define I3C_IBIDR_IBIDB2_Pos (16UL) #define I3C_IBIDR_IBIDB2_Msk (0xFFUL << I3C_IBIDR_IBIDB2_Pos) /*!< 0x00FF0000 */ #define I3C_IBIDR_IBIDB2 I3C_IBIDR_IBIDB2_Msk /*!< IBI Data Byte 2 */ -#define I3C_IBIDR_IBIDB3_Pos (24U) +#define I3C_IBIDR_IBIDB3_Pos (24UL) #define I3C_IBIDR_IBIDB3_Msk (0xFFUL << I3C_IBIDR_IBIDB3_Pos) /*!< 0xFF000000 */ #define I3C_IBIDR_IBIDB3 I3C_IBIDR_IBIDB3_Msk /*!< IBI Data Byte 3 */ /****************** Bit definition for I3C_TGTTDR register ******************/ -#define I3C_TGTTDR_TGTTDCNT_Pos (0U) +#define I3C_TGTTDR_TGTTDCNT_Pos (0UL) #define I3C_TGTTDR_TGTTDCNT_Msk (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos) /*!< 0x0000FFFF */ #define I3C_TGTTDR_TGTTDCNT I3C_TGTTDR_TGTTDCNT_Msk /*!< Target Transmit Data Counter */ -#define I3C_TGTTDR_PRELOAD_Pos (16U) +#define I3C_TGTTDR_PRELOAD_Pos (16UL) #define I3C_TGTTDR_PRELOAD_Msk (0x1UL << I3C_TGTTDR_PRELOAD_Pos) /*!< 0x00010000 */ #define I3C_TGTTDR_PRELOAD I3C_TGTTDR_PRELOAD_Msk /*!< Transmit FIFO Preload Enable/Status */ /******************* Bit definition for I3C_SR register *********************/ -#define I3C_SR_XDCNT_Pos (0U) +#define I3C_SR_XDCNT_Pos (0UL) #define I3C_SR_XDCNT_Msk (0xFFFFUL << I3C_SR_XDCNT_Pos) /*!< 0x0000FFFF */ #define I3C_SR_XDCNT I3C_SR_XDCNT_Msk /*!< Transfer Data Byte Count status */ -#define I3C_SR_ABT_Pos (17U) +#define I3C_SR_ABT_Pos (17UL) #define I3C_SR_ABT_Msk (0x1UL << I3C_SR_ABT_Pos) /*!< 0x00020000 */ #define I3C_SR_ABT I3C_SR_ABT_Msk /*!< Target Abort Indication */ -#define I3C_SR_DIR_Pos (18U) +#define I3C_SR_DIR_Pos (18UL) #define I3C_SR_DIR_Msk (0x1UL << I3C_SR_DIR_Pos) /*!< 0x00040000 */ #define I3C_SR_DIR I3C_SR_DIR_Msk /*!< Message Direction */ -#define I3C_SR_MID_Pos (24U) +#define I3C_SR_MID_Pos (24UL) #define I3C_SR_MID_Msk (0xFFUL << I3C_SR_MID_Pos) /*!< 0xFF000000 */ #define I3C_SR_MID I3C_SR_MID_Msk /*!< Message Identifier */ /******************* Bit definition for I3C_SER register ********************/ -#define I3C_SER_CODERR_Pos (0U) +#define I3C_SER_CODERR_Pos (0UL) #define I3C_SER_CODERR_Msk (0xFUL << I3C_SER_CODERR_Pos) /*!< 0x0000000F */ #define I3C_SER_CODERR I3C_SER_CODERR_Msk /*!< Protocol Error Code */ #define I3C_SER_CODERR_0 (0x1UL << I3C_SER_CODERR_Pos) /*!< 0x00000001 */ #define I3C_SER_CODERR_1 (0x2UL << I3C_SER_CODERR_Pos) /*!< 0x00000002 */ #define I3C_SER_CODERR_2 (0x4UL << I3C_SER_CODERR_Pos) /*!< 0x00000004 */ #define I3C_SER_CODERR_3 (0x8UL << I3C_SER_CODERR_Pos) /*!< 0x00000008 */ -#define I3C_SER_PERR_Pos (4U) +#define I3C_SER_PERR_Pos (4UL) #define I3C_SER_PERR_Msk (0x1UL << I3C_SER_PERR_Pos) /*!< 0x00000010 */ #define I3C_SER_PERR I3C_SER_PERR_Msk /*!< Protocol Error */ -#define I3C_SER_STALL_Pos (5U) +#define I3C_SER_STALL_Pos (5UL) #define I3C_SER_STALL_Msk (0x1UL << I3C_SER_STALL_Pos) /*!< 0x00000020 */ #define I3C_SER_STALL I3C_SER_STALL_Msk /*!< SCL Stall Error */ -#define I3C_SER_DOVR_Pos (6U) +#define I3C_SER_DOVR_Pos (6UL) #define I3C_SER_DOVR_Msk (0x1UL << I3C_SER_DOVR_Pos) /*!< 0x00000040 */ #define I3C_SER_DOVR I3C_SER_DOVR_Msk /*!< RX/TX FIFO Overrun */ -#define I3C_SER_COVR_Pos (7U) +#define I3C_SER_COVR_Pos (7UL) #define I3C_SER_COVR_Msk (0x1UL << I3C_SER_COVR_Pos) /*!< 0x00000080 */ #define I3C_SER_COVR I3C_SER_COVR_Msk /*!< Status/Control FIFO Overrun */ -#define I3C_SER_ANACK_Pos (8U) +#define I3C_SER_ANACK_Pos (8UL) #define I3C_SER_ANACK_Msk (0x1UL << I3C_SER_ANACK_Pos) /*!< 0x00000100 */ #define I3C_SER_ANACK I3C_SER_ANACK_Msk /*!< Address Not Acknowledged */ -#define I3C_SER_DNACK_Pos (9U) +#define I3C_SER_DNACK_Pos (9UL) #define I3C_SER_DNACK_Msk (0x1UL << I3C_SER_DNACK_Pos) /*!< 0x00000200 */ #define I3C_SER_DNACK I3C_SER_DNACK_Msk /*!< Data Not Acknowledged */ -#define I3C_SER_DERR_Pos (10U) +#define I3C_SER_DERR_Pos (10UL) #define I3C_SER_DERR_Msk (0x1UL << I3C_SER_DERR_Pos) /*!< 0x00000400 */ #define I3C_SER_DERR I3C_SER_DERR_Msk /*!< Data Error during the controller-role hand-off procedure */ /******************* Bit definition for I3C_RMR register ********************/ -#define I3C_RMR_IBIRDCNT_Pos (0U) +#define I3C_RMR_IBIRDCNT_Pos (0UL) #define I3C_RMR_IBIRDCNT_Msk (0x7UL << I3C_RMR_IBIRDCNT_Pos) /*!< 0x00000007 */ #define I3C_RMR_IBIRDCNT I3C_RMR_IBIRDCNT_Msk /*!< Data Count when reading IBI data */ -#define I3C_RMR_RCODE_Pos (8U) +#define I3C_RMR_RCODE_Pos (8UL) #define I3C_RMR_RCODE_Msk (0xFFUL << I3C_RMR_RCODE_Pos) /*!< 0x0000FF00 */ #define I3C_RMR_RCODE I3C_RMR_RCODE_Msk /*!< CCC code of received command */ -#define I3C_RMR_RADD_Pos (17U) +#define I3C_RMR_RADD_Pos (17UL) #define I3C_RMR_RADD_Msk (0x7FUL << I3C_RMR_RADD_Pos) /*!< 0x00FE0000 */ #define I3C_RMR_RADD I3C_RMR_RADD_Msk /*!< Target Address Received during accepted IBI or Controller-role request */ /******************* Bit definition for I3C_EVR register ********************/ -#define I3C_EVR_CFEF_Pos (0U) +#define I3C_EVR_CFEF_Pos (0UL) #define I3C_EVR_CFEF_Msk (0x1UL << I3C_EVR_CFEF_Pos) /*!< 0x00000001 */ #define I3C_EVR_CFEF I3C_EVR_CFEF_Msk /*!< Control FIFO Empty Flag */ -#define I3C_EVR_TXFEF_Pos (1U) +#define I3C_EVR_TXFEF_Pos (1UL) #define I3C_EVR_TXFEF_Msk (0x1UL << I3C_EVR_TXFEF_Pos) /*!< 0x00000002 */ #define I3C_EVR_TXFEF I3C_EVR_TXFEF_Msk /*!< TX FIFO Empty Flag */ -#define I3C_EVR_CFNFF_Pos (2U) +#define I3C_EVR_CFNFF_Pos (2UL) #define I3C_EVR_CFNFF_Msk (0x1UL << I3C_EVR_CFNFF_Pos) /*!< 0x00000004 */ #define I3C_EVR_CFNFF I3C_EVR_CFNFF_Msk /*!< Control FIFO Not Full Flag */ -#define I3C_EVR_SFNEF_Pos (3U) +#define I3C_EVR_SFNEF_Pos (3UL) #define I3C_EVR_SFNEF_Msk (0x1UL << I3C_EVR_SFNEF_Pos) /*!< 0x00000008 */ #define I3C_EVR_SFNEF I3C_EVR_SFNEF_Msk /*!< Status FIFO Not Empty Flag */ -#define I3C_EVR_TXFNFF_Pos (4U) +#define I3C_EVR_TXFNFF_Pos (4UL) #define I3C_EVR_TXFNFF_Msk (0x1UL << I3C_EVR_TXFNFF_Pos) /*!< 0x00000010 */ #define I3C_EVR_TXFNFF I3C_EVR_TXFNFF_Msk /*!< TX FIFO Not Full Flag */ -#define I3C_EVR_RXFNEF_Pos (5U) +#define I3C_EVR_RXFNEF_Pos (5UL) #define I3C_EVR_RXFNEF_Msk (0x1UL << I3C_EVR_RXFNEF_Pos) /*!< 0x00000020 */ #define I3C_EVR_RXFNEF I3C_EVR_RXFNEF_Msk /*!< RX FIFO Not Empty Flag */ -#define I3C_EVR_TXLASTF_Pos (6U) +#define I3C_EVR_TXLASTF_Pos (6UL) #define I3C_EVR_TXLASTF_Msk (0x1UL << I3C_EVR_TXLASTF_Pos) /*!< 0x00000040 */ #define I3C_EVR_TXLASTF I3C_EVR_TXLASTF_Msk /*!< Last TX byte available in FIFO */ -#define I3C_EVR_RXLASTF_Pos (7U) +#define I3C_EVR_RXLASTF_Pos (7UL) #define I3C_EVR_RXLASTF_Msk (0x1UL << I3C_EVR_RXLASTF_Pos) /*!< 0x00000080 */ #define I3C_EVR_RXLASTF I3C_EVR_RXLASTF_Msk /*!< Last RX byte read from FIFO */ -#define I3C_EVR_FCF_Pos (9U) +#define I3C_EVR_FCF_Pos (9UL) #define I3C_EVR_FCF_Msk (0x1UL << I3C_EVR_FCF_Pos) /*!< 0x00000200 */ #define I3C_EVR_FCF I3C_EVR_FCF_Msk /*!< Frame Complete Flag */ -#define I3C_EVR_RXTGTENDF_Pos (10U) +#define I3C_EVR_RXTGTENDF_Pos (10UL) #define I3C_EVR_RXTGTENDF_Msk (0x1UL << I3C_EVR_RXTGTENDF_Pos) /*!< 0x00000400 */ #define I3C_EVR_RXTGTENDF I3C_EVR_RXTGTENDF_Msk /*!< Reception Target End Flag */ -#define I3C_EVR_ERRF_Pos (11U) +#define I3C_EVR_ERRF_Pos (11UL) #define I3C_EVR_ERRF_Msk (0x1UL << I3C_EVR_ERRF_Pos) /*!< 0x00000800 */ #define I3C_EVR_ERRF I3C_EVR_ERRF_Msk /*!< Error Flag */ -#define I3C_EVR_IBIF_Pos (15U) +#define I3C_EVR_IBIF_Pos (15UL) #define I3C_EVR_IBIF_Msk (0x1UL << I3C_EVR_IBIF_Pos) /*!< 0x00008000 */ #define I3C_EVR_IBIF I3C_EVR_IBIF_Msk /*!< IBI Flag */ -#define I3C_EVR_IBIENDF_Pos (16U) +#define I3C_EVR_IBIENDF_Pos (16UL) #define I3C_EVR_IBIENDF_Msk (0x1UL << I3C_EVR_IBIENDF_Pos) /*!< 0x00010000 */ #define I3C_EVR_IBIENDF I3C_EVR_IBIENDF_Msk /*!< IBI End Flag */ -#define I3C_EVR_CRF_Pos (17U) +#define I3C_EVR_CRF_Pos (17UL) #define I3C_EVR_CRF_Msk (0x1UL << I3C_EVR_CRF_Pos) /*!< 0x00020000 */ #define I3C_EVR_CRF I3C_EVR_CRF_Msk /*!< Controller-role Request Flag */ -#define I3C_EVR_CRUPDF_Pos (18U) +#define I3C_EVR_CRUPDF_Pos (18UL) #define I3C_EVR_CRUPDF_Msk (0x1UL << I3C_EVR_CRUPDF_Pos) /*!< 0x00040000 */ #define I3C_EVR_CRUPDF I3C_EVR_CRUPDF_Msk /*!< Controller-role Update Flag */ -#define I3C_EVR_HJF_Pos (19U) +#define I3C_EVR_HJF_Pos (19UL) #define I3C_EVR_HJF_Msk (0x1UL << I3C_EVR_HJF_Pos) /*!< 0x00080000 */ #define I3C_EVR_HJF I3C_EVR_HJF_Msk /*!< Hot Join Flag */ -#define I3C_EVR_WKPF_Pos (21U) +#define I3C_EVR_WKPF_Pos (21UL) #define I3C_EVR_WKPF_Msk (0x1UL << I3C_EVR_WKPF_Pos) /*!< 0x00200000 */ #define I3C_EVR_WKPF I3C_EVR_WKPF_Msk /*!< Wake Up Flag */ -#define I3C_EVR_GETF_Pos (22U) +#define I3C_EVR_GETF_Pos (22UL) #define I3C_EVR_GETF_Msk (0x1UL << I3C_EVR_GETF_Pos) /*!< 0x00400000 */ #define I3C_EVR_GETF I3C_EVR_GETF_Msk /*!< Get type CCC received Flag */ -#define I3C_EVR_STAF_Pos (23U) +#define I3C_EVR_STAF_Pos (23UL) #define I3C_EVR_STAF_Msk (0x1UL << I3C_EVR_STAF_Pos) /*!< 0x00800000 */ #define I3C_EVR_STAF I3C_EVR_STAF_Msk /*!< Get Status Flag */ -#define I3C_EVR_DAUPDF_Pos (24U) +#define I3C_EVR_DAUPDF_Pos (24UL) #define I3C_EVR_DAUPDF_Msk (0x1UL << I3C_EVR_DAUPDF_Pos) /*!< 0x01000000 */ #define I3C_EVR_DAUPDF I3C_EVR_DAUPDF_Msk /*!< Dynamic Address Update Flag */ -#define I3C_EVR_MWLUPDF_Pos (25U) +#define I3C_EVR_MWLUPDF_Pos (25UL) #define I3C_EVR_MWLUPDF_Msk (0x1UL << I3C_EVR_MWLUPDF_Pos) /*!< 0x02000000 */ #define I3C_EVR_MWLUPDF I3C_EVR_MWLUPDF_Msk /*!< Max Write Length Update Flag */ -#define I3C_EVR_MRLUPDF_Pos (26U) +#define I3C_EVR_MRLUPDF_Pos (26UL) #define I3C_EVR_MRLUPDF_Msk (0x1UL << I3C_EVR_MRLUPDF_Pos) /*!< 0x04000000 */ #define I3C_EVR_MRLUPDF I3C_EVR_MRLUPDF_Msk /*!< Max Read Length Update Flag */ -#define I3C_EVR_RSTF_Pos (27U) +#define I3C_EVR_RSTF_Pos (27UL) #define I3C_EVR_RSTF_Msk (0x1UL << I3C_EVR_RSTF_Pos) /*!< 0x08000000 */ #define I3C_EVR_RSTF I3C_EVR_RSTF_Msk /*!< Reset Flag, due to Reset pattern received */ -#define I3C_EVR_ASUPDF_Pos (28U) +#define I3C_EVR_ASUPDF_Pos (28UL) #define I3C_EVR_ASUPDF_Msk (0x1UL << I3C_EVR_ASUPDF_Pos) /*!< 0x10000000 */ #define I3C_EVR_ASUPDF I3C_EVR_ASUPDF_Msk /*!< Activity State Flag */ -#define I3C_EVR_INTUPDF_Pos (29U) +#define I3C_EVR_INTUPDF_Pos (29UL) #define I3C_EVR_INTUPDF_Msk (0x1UL << I3C_EVR_INTUPDF_Pos) /*!< 0x20000000 */ #define I3C_EVR_INTUPDF I3C_EVR_INTUPDF_Msk /*!< Interrupt Update Flag */ -#define I3C_EVR_DEFF_Pos (30U) +#define I3C_EVR_DEFF_Pos (30UL) #define I3C_EVR_DEFF_Msk (0x1UL << I3C_EVR_DEFF_Pos) /*!< 0x40000000 */ #define I3C_EVR_DEFF I3C_EVR_DEFF_Msk /*!< List of Targets Command Received Flag */ -#define I3C_EVR_GRPF_Pos (31U) +#define I3C_EVR_GRPF_Pos (31UL) #define I3C_EVR_GRPF_Msk (0x1UL << I3C_EVR_GRPF_Pos) /*!< 0x80000000 */ #define I3C_EVR_GRPF I3C_EVR_GRPF_Msk /*!< List of Group Addresses Command Received Flag */ /******************* Bit definition for I3C_IER register ********************/ -#define I3C_IER_CFNFIE_Pos (2U) +#define I3C_IER_CFNFIE_Pos (2UL) #define I3C_IER_CFNFIE_Msk (0x1UL << I3C_IER_CFNFIE_Pos) /*!< 0x00000004 */ #define I3C_IER_CFNFIE I3C_IER_CFNFIE_Msk /*!< Control FIFO Not Full Interrupt Enable */ -#define I3C_IER_SFNEIE_Pos (3U) +#define I3C_IER_SFNEIE_Pos (3UL) #define I3C_IER_SFNEIE_Msk (0x1UL << I3C_IER_SFNEIE_Pos) /*!< 0x00000008 */ #define I3C_IER_SFNEIE I3C_IER_SFNEIE_Msk /*!< Status FIFO Not Empty Interrupt Enable */ -#define I3C_IER_TXFNFIE_Pos (4U) +#define I3C_IER_TXFNFIE_Pos (4UL) #define I3C_IER_TXFNFIE_Msk (0x1UL << I3C_IER_TXFNFIE_Pos) /*!< 0x00000010 */ #define I3C_IER_TXFNFIE I3C_IER_TXFNFIE_Msk /*!< TX FIFO Not Full Interrupt Enable */ -#define I3C_IER_RXFNEIE_Pos (5U) +#define I3C_IER_RXFNEIE_Pos (5UL) #define I3C_IER_RXFNEIE_Msk (0x1UL << I3C_IER_RXFNEIE_Pos) /*!< 0x00000020 */ #define I3C_IER_RXFNEIE I3C_IER_RXFNEIE_Msk /*!< RX FIFO Not Empty Interrupt Enable */ -#define I3C_IER_FCIE_Pos (9U) +#define I3C_IER_FCIE_Pos (9UL) #define I3C_IER_FCIE_Msk (0x1UL << I3C_IER_FCIE_Pos) /*!< 0x00000200 */ #define I3C_IER_FCIE I3C_IER_FCIE_Msk /*!< Frame Complete Interrupt Enable */ -#define I3C_IER_RXTGTENDIE_Pos (10U) +#define I3C_IER_RXTGTENDIE_Pos (10UL) #define I3C_IER_RXTGTENDIE_Msk (0x1UL << I3C_IER_RXTGTENDIE_Pos) /*!< 0x00000400 */ #define I3C_IER_RXTGTENDIE I3C_IER_RXTGTENDIE_Msk /*!< Reception Target End Interrupt Enable */ -#define I3C_IER_ERRIE_Pos (11U) +#define I3C_IER_ERRIE_Pos (11UL) #define I3C_IER_ERRIE_Msk (0x1UL << I3C_IER_ERRIE_Pos) /*!< 0x00000800 */ #define I3C_IER_ERRIE I3C_IER_ERRIE_Msk /*!< Error Interrupt Enable */ -#define I3C_IER_IBIIE_Pos (15U) +#define I3C_IER_IBIIE_Pos (15UL) #define I3C_IER_IBIIE_Msk (0x1UL << I3C_IER_IBIIE_Pos) /*!< 0x00008000 */ #define I3C_IER_IBIIE I3C_IER_IBIIE_Msk /*!< IBI Interrupt Enable */ -#define I3C_IER_IBIENDIE_Pos (16U) +#define I3C_IER_IBIENDIE_Pos (16UL) #define I3C_IER_IBIENDIE_Msk (0x1UL << I3C_IER_IBIENDIE_Pos) /*!< 0x00010000 */ #define I3C_IER_IBIENDIE I3C_IER_IBIENDIE_Msk /*!< IBI End Interrupt Enable */ -#define I3C_IER_CRIE_Pos (17U) +#define I3C_IER_CRIE_Pos (17UL) #define I3C_IER_CRIE_Msk (0x1UL << I3C_IER_CRIE_Pos) /*!< 0x00020000 */ #define I3C_IER_CRIE I3C_IER_CRIE_Msk /*!< Controller-role Interrupt Enable */ -#define I3C_IER_CRUPDIE_Pos (18U) +#define I3C_IER_CRUPDIE_Pos (18UL) #define I3C_IER_CRUPDIE_Msk (0x1UL << I3C_IER_CRUPDIE_Pos) /*!< 0x00040000 */ #define I3C_IER_CRUPDIE I3C_IER_CRUPDIE_Msk /*!< Controller-role Update Interrupt Enable */ -#define I3C_IER_HJIE_Pos (19U) +#define I3C_IER_HJIE_Pos (19UL) #define I3C_IER_HJIE_Msk (0x1UL << I3C_IER_HJIE_Pos) /*!< 0x00080000 */ #define I3C_IER_HJIE I3C_IER_HJIE_Msk /*!< Hot Join Interrupt Enable */ -#define I3C_IER_WKPIE_Pos (21U) +#define I3C_IER_WKPIE_Pos (21UL) #define I3C_IER_WKPIE_Msk (0x1UL << I3C_IER_WKPIE_Pos) /*!< 0x00200000 */ #define I3C_IER_WKPIE I3C_IER_WKPIE_Msk /*!< Wake Up Interrupt Enable */ -#define I3C_IER_GETIE_Pos (22U) +#define I3C_IER_GETIE_Pos (22UL) #define I3C_IER_GETIE_Msk (0x1UL << I3C_IER_GETIE_Pos) /*!< 0x00400000 */ #define I3C_IER_GETIE I3C_IER_GETIE_Msk /*!< Get type CCC received Interrupt Enable */ -#define I3C_IER_STAIE_Pos (23U) +#define I3C_IER_STAIE_Pos (23UL) #define I3C_IER_STAIE_Msk (0x1UL << I3C_IER_STAIE_Pos) /*!< 0x00800000 */ #define I3C_IER_STAIE I3C_IER_STAIE_Msk /*!< Get Status Interrupt Enable */ -#define I3C_IER_DAUPDIE_Pos (24U) +#define I3C_IER_DAUPDIE_Pos (24UL) #define I3C_IER_DAUPDIE_Msk (0x1UL << I3C_IER_DAUPDIE_Pos) /*!< 0x01000000 */ #define I3C_IER_DAUPDIE I3C_IER_DAUPDIE_Msk /*!< Dynamic Address Update Interrupt Enable */ -#define I3C_IER_MWLUPDIE_Pos (25U) +#define I3C_IER_MWLUPDIE_Pos (25UL) #define I3C_IER_MWLUPDIE_Msk (0x1UL << I3C_IER_MWLUPDIE_Pos) /*!< 0x02000000 */ #define I3C_IER_MWLUPDIE I3C_IER_MWLUPDIE_Msk /*!< Max Write Length Update Interrupt Enable */ -#define I3C_IER_MRLUPDIE_Pos (26U) +#define I3C_IER_MRLUPDIE_Pos (26UL) #define I3C_IER_MRLUPDIE_Msk (0x1UL << I3C_IER_MRLUPDIE_Pos) /*!< 0x04000000 */ #define I3C_IER_MRLUPDIE I3C_IER_MRLUPDIE_Msk /*!< Max Read Length Update Interrupt Enable */ -#define I3C_IER_RSTIE_Pos (27U) +#define I3C_IER_RSTIE_Pos (27UL) #define I3C_IER_RSTIE_Msk (0x1UL << I3C_IER_RSTIE_Pos) /*!< 0x08000000 */ #define I3C_IER_RSTIE I3C_IER_RSTIE_Msk /*!< Reset Interrupt Enabled, due to Reset pattern received */ -#define I3C_IER_ASUPDIE_Pos (28U) +#define I3C_IER_ASUPDIE_Pos (28UL) #define I3C_IER_ASUPDIE_Msk (0x1UL << I3C_IER_ASUPDIE_Pos) /*!< 0x10000000 */ #define I3C_IER_ASUPDIE I3C_IER_ASUPDIE_Msk /*!< Activity State Interrupt Enable */ -#define I3C_IER_INTUPDIE_Pos (29U) +#define I3C_IER_INTUPDIE_Pos (29UL) #define I3C_IER_INTUPDIE_Msk (0x1UL << I3C_IER_INTUPDIE_Pos) /*!< 0x20000000 */ #define I3C_IER_INTUPDIE I3C_IER_INTUPDIE_Msk /*!< Interrupt Update Interrupt Enable */ -#define I3C_IER_DEFIE_Pos (30U) +#define I3C_IER_DEFIE_Pos (30UL) #define I3C_IER_DEFIE_Msk (0x1UL << I3C_IER_DEFIE_Pos) /*!< 0x40000000 */ #define I3C_IER_DEFIE I3C_IER_DEFIE_Msk /*!< List of Targets Command Received Interrupt Enable */ -#define I3C_IER_GRPIE_Pos (31U) +#define I3C_IER_GRPIE_Pos (31UL) #define I3C_IER_GRPIE_Msk (0x1UL << I3C_IER_GRPIE_Pos) /*!< 0x80000000 */ #define I3C_IER_GRPIE I3C_IER_GRPIE_Msk /*!< List of Group Addresses Command Received Interrupt Enable */ /******************* Bit definition for I3C_CEVR register *******************/ -#define I3C_CEVR_CFCF_Pos (9U) +#define I3C_CEVR_CFCF_Pos (9UL) #define I3C_CEVR_CFCF_Msk (0x1UL << I3C_CEVR_CFCF_Pos) /*!< 0x00000200 */ #define I3C_CEVR_CFCF I3C_CEVR_CFCF_Msk /*!< Frame Complete Clear Flag */ -#define I3C_CEVR_CRXTGTENDF_Pos (10U) +#define I3C_CEVR_CRXTGTENDF_Pos (10UL) #define I3C_CEVR_CRXTGTENDF_Msk (0x1UL << I3C_CEVR_CRXTGTENDF_Pos) /*!< 0x00000400 */ #define I3C_CEVR_CRXTGTENDF I3C_CEVR_CRXTGTENDF_Msk /*!< Reception Target End Clear Flag */ -#define I3C_CEVR_CERRF_Pos (11U) +#define I3C_CEVR_CERRF_Pos (11UL) #define I3C_CEVR_CERRF_Msk (0x1UL << I3C_CEVR_CERRF_Pos) /*!< 0x00000800 */ #define I3C_CEVR_CERRF I3C_CEVR_CERRF_Msk /*!< Error Clear Flag */ -#define I3C_CEVR_CIBIF_Pos (15U) +#define I3C_CEVR_CIBIF_Pos (15UL) #define I3C_CEVR_CIBIF_Msk (0x1UL << I3C_CEVR_CIBIF_Pos) /*!< 0x00008000 */ #define I3C_CEVR_CIBIF I3C_CEVR_CIBIF_Msk /*!< IBI Clear Flag */ -#define I3C_CEVR_CIBIENDF_Pos (16U) +#define I3C_CEVR_CIBIENDF_Pos (16UL) #define I3C_CEVR_CIBIENDF_Msk (0x1UL << I3C_CEVR_CIBIENDF_Pos) /*!< 0x00010000 */ #define I3C_CEVR_CIBIENDF I3C_CEVR_CIBIENDF_Msk /*!< IBI End Clear Flag */ -#define I3C_CEVR_CCRF_Pos (17U) +#define I3C_CEVR_CCRF_Pos (17UL) #define I3C_CEVR_CCRF_Msk (0x1UL << I3C_CEVR_CCRF_Pos) /*!< 0x00020000 */ #define I3C_CEVR_CCRF I3C_CEVR_CCRF_Msk /*!< Controller-role Clear Flag */ -#define I3C_CEVR_CCRUPDF_Pos (18U) +#define I3C_CEVR_CCRUPDF_Pos (18UL) #define I3C_CEVR_CCRUPDF_Msk (0x1UL << I3C_CEVR_CCRUPDF_Pos) /*!< 0x00040000 */ #define I3C_CEVR_CCRUPDF I3C_CEVR_CCRUPDF_Msk /*!< Controller-role Update Clear Flag */ -#define I3C_CEVR_CHJF_Pos (19U) +#define I3C_CEVR_CHJF_Pos (19UL) #define I3C_CEVR_CHJF_Msk (0x1UL << I3C_CEVR_CHJF_Pos) /*!< 0x00080000 */ #define I3C_CEVR_CHJF I3C_CEVR_CHJF_Msk /*!< Hot Join Clear Flag */ -#define I3C_CEVR_CWKPF_Pos (21U) +#define I3C_CEVR_CWKPF_Pos (21UL) #define I3C_CEVR_CWKPF_Msk (0x1UL << I3C_CEVR_CWKPF_Pos) /*!< 0x00200000 */ #define I3C_CEVR_CWKPF I3C_CEVR_CWKPF_Msk /*!< Wake Up Clear Flag */ -#define I3C_CEVR_CGETF_Pos (22U) +#define I3C_CEVR_CGETF_Pos (22UL) #define I3C_CEVR_CGETF_Msk (0x1UL << I3C_CEVR_CGETF_Pos) /*!< 0x00400000 */ #define I3C_CEVR_CGETF I3C_CEVR_CGETF_Msk /*!< Get type CCC received Clear Flag */ -#define I3C_CEVR_CSTAF_Pos (23U) +#define I3C_CEVR_CSTAF_Pos (23UL) #define I3C_CEVR_CSTAF_Msk (0x1UL << I3C_CEVR_CSTAF_Pos) /*!< 0x00800000 */ #define I3C_CEVR_CSTAF I3C_CEVR_CSTAF_Msk /*!< Get Status Clear Flag */ -#define I3C_CEVR_CDAUPDF_Pos (24U) +#define I3C_CEVR_CDAUPDF_Pos (24UL) #define I3C_CEVR_CDAUPDF_Msk (0x1UL << I3C_CEVR_CDAUPDF_Pos) /*!< 0x01000000 */ #define I3C_CEVR_CDAUPDF I3C_CEVR_CDAUPDF_Msk /*!< Dynamic Address Update Clear Flag */ -#define I3C_CEVR_CMWLUPDF_Pos (25U) +#define I3C_CEVR_CMWLUPDF_Pos (25UL) #define I3C_CEVR_CMWLUPDF_Msk (0x1UL << I3C_CEVR_CMWLUPDF_Pos) /*!< 0x02000000 */ #define I3C_CEVR_CMWLUPDF I3C_CEVR_CMWLUPDF_Msk /*!< Max Write Length Update Clear Flag */ -#define I3C_CEVR_CMRLUPDF_Pos (26U) +#define I3C_CEVR_CMRLUPDF_Pos (26UL) #define I3C_CEVR_CMRLUPDF_Msk (0x1UL << I3C_CEVR_CMRLUPDF_Pos) /*!< 0x04000000 */ #define I3C_CEVR_CMRLUPDF I3C_CEVR_CMRLUPDF_Msk /*!< Max Read Length Update Clear Flag */ -#define I3C_CEVR_CRSTF_Pos (27U) +#define I3C_CEVR_CRSTF_Pos (27UL) #define I3C_CEVR_CRSTF_Msk (0x1UL << I3C_CEVR_CRSTF_Pos) /*!< 0x08000000 */ #define I3C_CEVR_CRSTF I3C_CEVR_CRSTF_Msk /*!< Reset Flag, due to Reset pattern received */ -#define I3C_CEVR_CASUPDF_Pos (28U) +#define I3C_CEVR_CASUPDF_Pos (28UL) #define I3C_CEVR_CASUPDF_Msk (0x1UL << I3C_CEVR_CASUPDF_Pos) /*!< 0x10000000 */ #define I3C_CEVR_CASUPDF I3C_CEVR_CASUPDF_Msk /*!< Activity State Clear Flag */ -#define I3C_CEVR_CINTUPDF_Pos (29U) +#define I3C_CEVR_CINTUPDF_Pos (29UL) #define I3C_CEVR_CINTUPDF_Msk (0x1UL << I3C_CEVR_CINTUPDF_Pos) /*!< 0x20000000 */ #define I3C_CEVR_CINTUPDF I3C_CEVR_CINTUPDF_Msk /*!< Interrupt Update Clear Flag */ -#define I3C_CEVR_CDEFF_Pos (30U) +#define I3C_CEVR_CDEFF_Pos (30UL) #define I3C_CEVR_CDEFF_Msk (0x1UL << I3C_CEVR_CDEFF_Pos) /*!< 0x40000000 */ #define I3C_CEVR_CDEFF I3C_CEVR_CDEFF_Msk /*!< List of Targets Command Received Clear Flag */ -#define I3C_CEVR_CGRPF_Pos (31U) +#define I3C_CEVR_CGRPF_Pos (31UL) #define I3C_CEVR_CGRPF_Msk (0x1UL << I3C_CEVR_CGRPF_Pos) /*!< 0x80000000 */ #define I3C_CEVR_CGRPF I3C_CEVR_CGRPF_Msk /*!< List of Group Addresses Command Received Clear Flag */ /******************* Bit definition for I3C_MISR register *******************/ -#define I3C_MISR_CFNFMIS_Pos (2U) +#define I3C_MISR_CFNFMIS_Pos (2UL) #define I3C_MISR_CFNFMIS_Msk (0x1UL << I3C_MISR_CFNFMIS_Pos) /*!< 0x00000004 */ #define I3C_MISR_CFNFMIS I3C_MISR_CFNFMIS_Msk /*!< Control FIFO Not Full Mask Interrupt Status */ -#define I3C_MISR_SFNEMIS_Pos (3U) +#define I3C_MISR_SFNEMIS_Pos (3UL) #define I3C_MISR_SFNEMIS_Msk (0x1UL << I3C_MISR_SFNEMIS_Pos) /*!< 0x00000008 */ #define I3C_MISR_SFNEMIS I3C_MISR_SFNEMIS_Msk /*!< Status FIFO Not Empty Mask Interrupt Status */ -#define I3C_MISR_TXFNFMIS_Pos (4U) +#define I3C_MISR_TXFNFMIS_Pos (4UL) #define I3C_MISR_TXFNFMIS_Msk (0x1UL << I3C_MISR_TXFNFMIS_Pos) /*!< 0x00000010 */ #define I3C_MISR_TXFNFMIS I3C_MISR_TXFNFMIS_Msk /*!< TX FIFO Not Full Mask Interrupt Status */ -#define I3C_MISR_RXFNEMIS_Pos (5U) +#define I3C_MISR_RXFNEMIS_Pos (5UL) #define I3C_MISR_RXFNEMIS_Msk (0x1UL << I3C_MISR_RXFNEMIS_Pos) /*!< 0x00000020 */ #define I3C_MISR_RXFNEMIS I3C_MISR_RXFNEMIS_Msk /*!< RX FIFO Not Empty Mask Interrupt Status */ -#define I3C_MISR_FCMIS_Pos (9U) +#define I3C_MISR_FCMIS_Pos (9UL) #define I3C_MISR_FCMIS_Msk (0x1UL << I3C_MISR_FCMIS_Pos) /*!< 0x00000200 */ #define I3C_MISR_FCMIS I3C_MISR_FCMIS_Msk /*!< Frame Complete Mask Interrupt Status */ -#define I3C_MISR_RXTGTENDMIS_Pos (10U) +#define I3C_MISR_RXTGTENDMIS_Pos (10UL) #define I3C_MISR_RXTGTENDMIS_Msk (0x1UL << I3C_MISR_RXTGTENDMIS_Pos) /*!< 0x00000400 */ #define I3C_MISR_RXTGTENDMIS I3C_MISR_RXTGTENDMIS_Msk /*!< Reception Target End Mask Interrupt Status */ -#define I3C_MISR_ERRMIS_Pos (11U) +#define I3C_MISR_ERRMIS_Pos (11UL) #define I3C_MISR_ERRMIS_Msk (0x1UL << I3C_MISR_ERRMIS_Pos) /*!< 0x00000800 */ #define I3C_MISR_ERRMIS I3C_MISR_ERRMIS_Msk /*!< Error Mask Interrupt Status */ -#define I3C_MISR_IBIMIS_Pos (15U) +#define I3C_MISR_IBIMIS_Pos (15UL) #define I3C_MISR_IBIMIS_Msk (0x1UL << I3C_MISR_IBIMIS_Pos) /*!< 0x00008000 */ #define I3C_MISR_IBIMIS I3C_MISR_IBIMIS_Msk /*!< IBI Mask Interrupt Status */ -#define I3C_MISR_IBIENDMIS_Pos (16U) +#define I3C_MISR_IBIENDMIS_Pos (16UL) #define I3C_MISR_IBIENDMIS_Msk (0x1UL << I3C_MISR_IBIENDMIS_Pos) /*!< 0x00010000 */ #define I3C_MISR_IBIENDMIS I3C_MISR_IBIENDMIS_Msk /*!< IBI End Mask Interrupt Status */ -#define I3C_MISR_CRMIS_Pos (17U) +#define I3C_MISR_CRMIS_Pos (17UL) #define I3C_MISR_CRMIS_Msk (0x1UL << I3C_MISR_CRMIS_Pos) /*!< 0x00020000 */ #define I3C_MISR_CRMIS I3C_MISR_CRMIS_Msk /*!< Controller-role Mask Interrupt Status */ -#define I3C_MISR_CRUPDMIS_Pos (18U) +#define I3C_MISR_CRUPDMIS_Pos (18UL) #define I3C_MISR_CRUPDMIS_Msk (0x1UL << I3C_MISR_CRUPDMIS_Pos) /*!< 0x00040000 */ #define I3C_MISR_CRUPDMIS I3C_MISR_CRUPDMIS_Msk /*!< Controller-role Update Mask Interrupt Status */ -#define I3C_MISR_HJMIS_Pos (19U) +#define I3C_MISR_HJMIS_Pos (19UL) #define I3C_MISR_HJMIS_Msk (0x1UL << I3C_MISR_HJMIS_Pos) /*!< 0x00080000 */ #define I3C_MISR_HJMIS I3C_MISR_HJMIS_Msk /*!< Hot Join Mask Interrupt Status */ -#define I3C_MISR_WKPMIS_Pos (21U) +#define I3C_MISR_WKPMIS_Pos (21UL) #define I3C_MISR_WKPMIS_Msk (0x1UL << I3C_MISR_WKPMIS_Pos) /*!< 0x00200000 */ #define I3C_MISR_WKPMIS I3C_MISR_WKPMIS_Msk /*!< Wake Up Mask Interrupt Status */ -#define I3C_MISR_GETMIS_Pos (22U) +#define I3C_MISR_GETMIS_Pos (22UL) #define I3C_MISR_GETMIS_Msk (0x1UL << I3C_MISR_GETMIS_Pos) /*!< 0x00400000 */ #define I3C_MISR_GETMIS I3C_MISR_GETMIS_Msk /*!< Get type CCC received Mask Interrupt Status */ -#define I3C_MISR_STAMIS_Pos (23U) +#define I3C_MISR_STAMIS_Pos (23UL) #define I3C_MISR_STAMIS_Msk (0x1UL << I3C_MISR_STAMIS_Pos) /*!< 0x00800000 */ #define I3C_MISR_STAMIS I3C_MISR_STAMIS_Msk /*!< Get Status Mask Interrupt Status */ -#define I3C_MISR_DAUPDMIS_Pos (24U) +#define I3C_MISR_DAUPDMIS_Pos (24UL) #define I3C_MISR_DAUPDMIS_Msk (0x1UL << I3C_MISR_DAUPDMIS_Pos) /*!< 0x01000000 */ #define I3C_MISR_DAUPDMIS I3C_MISR_DAUPDMIS_Msk /*!< Dynamic Address Update Mask Interrupt Status */ -#define I3C_MISR_MWLUPDMIS_Pos (25U) +#define I3C_MISR_MWLUPDMIS_Pos (25UL) #define I3C_MISR_MWLUPDMIS_Msk (0x1UL << I3C_MISR_MWLUPDMIS_Pos) /*!< 0x02000000 */ #define I3C_MISR_MWLUPDMIS I3C_MISR_MWLUPDMIS_Msk /*!< Max Write Length Update Mask Interrupt Status */ -#define I3C_MISR_MRLUPDMIS_Pos (26U) +#define I3C_MISR_MRLUPDMIS_Pos (26UL) #define I3C_MISR_MRLUPDMIS_Msk (0x1UL << I3C_MISR_MRLUPDMIS_Pos) /*!< 0x04000000 */ #define I3C_MISR_MRLUPDMIS I3C_MISR_MRLUPDMIS_Msk /*!< Max Read Length Update Mask Interrupt Status */ -#define I3C_MISR_RSTMIS_Pos (27U) +#define I3C_MISR_RSTMIS_Pos (27UL) #define I3C_MISR_RSTMIS_Msk (0x1UL << I3C_MISR_RSTMIS_Pos) /*!< 0x08000000 */ #define I3C_MISR_RSTMIS I3C_MISR_RSTMIS_Msk /*!< Reset Mask Interrupt Status, due to Reset pattern received */ -#define I3C_MISR_ASUPDMIS_Pos (28U) +#define I3C_MISR_ASUPDMIS_Pos (28UL) #define I3C_MISR_ASUPDMIS_Msk (0x1UL << I3C_MISR_ASUPDMIS_Pos) /*!< 0x10000000 */ #define I3C_MISR_ASUPDMIS I3C_MISR_ASUPDMIS_Msk /*!< Activity State Mask Interrupt Status */ -#define I3C_MISR_INTUPDMIS_Pos (29U) +#define I3C_MISR_INTUPDMIS_Pos (29UL) #define I3C_MISR_INTUPDMIS_Msk (0x1UL << I3C_MISR_INTUPDMIS_Pos) /*!< 0x20000000 */ #define I3C_MISR_INTUPDMIS I3C_MISR_INTUPDMIS_Msk /*!< Interrupt Update Mask Interrupt Status */ -#define I3C_MISR_DEFMIS_Pos (30U) +#define I3C_MISR_DEFMIS_Pos (30UL) #define I3C_MISR_DEFMIS_Msk (0x1UL << I3C_MISR_DEFMIS_Pos) /*!< 0x40000000 */ #define I3C_MISR_DEFMIS I3C_MISR_DEFMIS_Msk /*!< List of Targets Command Received Mask Interrupt Status */ -#define I3C_MISR_GRPMIS_Pos (31U) +#define I3C_MISR_GRPMIS_Pos (31UL) #define I3C_MISR_GRPMIS_Msk (0x1UL << I3C_MISR_GRPMIS_Pos) /*!< 0x80000000 */ #define I3C_MISR_GRPMIS I3C_MISR_GRPMIS_Msk /*!< List of Group Addresses Command Received Mask Interrupt Status */ /****************** Bit definition for I3C_DEVR0 register *******************/ -#define I3C_DEVR0_DAVAL_Pos (0U) +#define I3C_DEVR0_DAVAL_Pos (0UL) #define I3C_DEVR0_DAVAL_Msk (0x1UL << I3C_DEVR0_DAVAL_Pos) /*!< 0x00000001 */ #define I3C_DEVR0_DAVAL I3C_DEVR0_DAVAL_Msk /*!< Dynamic Address Validity */ -#define I3C_DEVR0_DA_Pos (1U) +#define I3C_DEVR0_DA_Pos (1UL) #define I3C_DEVR0_DA_Msk (0x7FUL << I3C_DEVR0_DA_Pos) /*!< 0x000000FE */ #define I3C_DEVR0_DA I3C_DEVR0_DA_Msk /*!< Own Target Device Address */ -#define I3C_DEVR0_IBIEN_Pos (16U) +#define I3C_DEVR0_IBIEN_Pos (16UL) #define I3C_DEVR0_IBIEN_Msk (0x1UL << I3C_DEVR0_IBIEN_Pos) /*!< 0x00010000 */ #define I3C_DEVR0_IBIEN I3C_DEVR0_IBIEN_Msk /*!< IBI Enable */ -#define I3C_DEVR0_CREN_Pos (17U) +#define I3C_DEVR0_CREN_Pos (17UL) #define I3C_DEVR0_CREN_Msk (0x1UL << I3C_DEVR0_CREN_Pos) /*!< 0x00020000 */ #define I3C_DEVR0_CREN I3C_DEVR0_CREN_Msk /*!< Controller-role Enable */ -#define I3C_DEVR0_HJEN_Pos (19U) +#define I3C_DEVR0_HJEN_Pos (19UL) #define I3C_DEVR0_HJEN_Msk (0x1UL << I3C_DEVR0_HJEN_Pos) /*!< 0x00080000 */ #define I3C_DEVR0_HJEN I3C_DEVR0_HJEN_Msk /*!< Hot Join Enable */ -#define I3C_DEVR0_AS_Pos (20U) +#define I3C_DEVR0_AS_Pos (20UL) #define I3C_DEVR0_AS_Msk (0x3UL << I3C_DEVR0_AS_Pos) /*!< 0x00300000 */ #define I3C_DEVR0_AS I3C_DEVR0_AS_Msk /*!< Activity State value update after ENTAx received */ #define I3C_DEVR0_AS_0 (0x1UL << I3C_DEVR0_AS_Pos) /*!< 0x00100000 */ #define I3C_DEVR0_AS_1 (0x2UL << I3C_DEVR0_AS_Pos) /*!< 0x00200000 */ -#define I3C_DEVR0_RSTACT_Pos (22U) +#define I3C_DEVR0_RSTACT_Pos (22UL) #define I3C_DEVR0_RSTACT_Msk (0x3UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00C000000 */ #define I3C_DEVR0_RSTACT I3C_DEVR0_RSTACT_Msk /*!< Reset Action value update after RSTACT received */ #define I3C_DEVR0_RSTACT_0 (0x1UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00400000 */ #define I3C_DEVR0_RSTACT_1 (0x2UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00800000 */ -#define I3C_DEVR0_RSTVAL_Pos (24U) +#define I3C_DEVR0_RSTVAL_Pos (24UL) #define I3C_DEVR0_RSTVAL_Msk (0x1UL << I3C_DEVR0_RSTVAL_Pos) /*!< 0x01000000 */ #define I3C_DEVR0_RSTVAL I3C_DEVR0_RSTVAL_Msk /*!< Reset Action Valid */ /****************** Bit definition for I3C_DEVRX register *******************/ -#define I3C_DEVRX_DA_Pos (1U) +#define I3C_DEVRX_DA_Pos (1UL) #define I3C_DEVRX_DA_Msk (0x7FUL << I3C_DEVRX_DA_Pos) /*!< 0x000000FE */ #define I3C_DEVRX_DA I3C_DEVRX_DA_Msk /*!< Dynamic Address Target x */ -#define I3C_DEVRX_IBIACK_Pos (16U) +#define I3C_DEVRX_IBIACK_Pos (16UL) #define I3C_DEVRX_IBIACK_Msk (0x1UL << I3C_DEVRX_IBIACK_Pos) /*!< 0x00010000 */ #define I3C_DEVRX_IBIACK I3C_DEVRX_IBIACK_Msk /*!< IBI Acknowledge from Target x */ -#define I3C_DEVRX_CRACK_Pos (17U) +#define I3C_DEVRX_CRACK_Pos (17UL) #define I3C_DEVRX_CRACK_Msk (0x1UL << I3C_DEVRX_CRACK_Pos) /*!< 0x00020000 */ #define I3C_DEVRX_CRACK I3C_DEVRX_CRACK_Msk /*!< Controller-role Acknowledge from Target x */ -#define I3C_DEVRX_IBIDEN_Pos (18U) +#define I3C_DEVRX_IBIDEN_Pos (18UL) #define I3C_DEVRX_IBIDEN_Msk (0x1UL << I3C_DEVRX_IBIDEN_Pos) /*!< 0x00040000 */ #define I3C_DEVRX_IBIDEN I3C_DEVRX_IBIDEN_Msk /*!< IBI Additional Data Enable */ -#define I3C_DEVRX_SUSP_Pos (19U) +#define I3C_DEVRX_SUSP_Pos (19UL) #define I3C_DEVRX_SUSP_Msk (0x1UL << I3C_DEVRX_SUSP_Pos) /*!< 0x00080000 */ #define I3C_DEVRX_SUSP I3C_DEVRX_SUSP_Msk /*!< Suspended Transfer */ -#define I3C_DEVRX_DIS_Pos (31U) +#define I3C_DEVRX_DIS_Pos (31UL) #define I3C_DEVRX_DIS_Msk (0x1UL << I3C_DEVRX_DIS_Pos) /*!< 0x80000000 */ #define I3C_DEVRX_DIS I3C_DEVRX_DIS_Msk /*!< Disable Register access */ /****************** Bit definition for I3C_MAXRLR register ******************/ -#define I3C_MAXRLR_MRL_Pos (0U) +#define I3C_MAXRLR_MRL_Pos (0UL) #define I3C_MAXRLR_MRL_Msk (0xFFFFUL << I3C_MAXRLR_MRL_Pos) /*!< 0x0000FFFF */ #define I3C_MAXRLR_MRL I3C_MAXRLR_MRL_Msk /*!< Maximum Read Length */ -#define I3C_MAXRLR_IBIP_Pos (16U) +#define I3C_MAXRLR_IBIP_Pos (16UL) #define I3C_MAXRLR_IBIP_Msk (0x7UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00070000 */ #define I3C_MAXRLR_IBIP I3C_MAXRLR_IBIP_Msk /*!< IBI Payload size */ #define I3C_MAXRLR_IBIP_0 (0x1UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00010000 */ @@ -15067,138 +15300,138 @@ typedef struct #define I3C_MAXRLR_IBIP_2 (0x4UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00040000 */ /****************** Bit definition for I3C_MAXWLR register ******************/ -#define I3C_MAXWLR_MWL_Pos (0U) +#define I3C_MAXWLR_MWL_Pos (0UL) #define I3C_MAXWLR_MWL_Msk (0xFFFFUL << I3C_MAXWLR_MWL_Pos) /*!< 0x0000FFFF */ #define I3C_MAXWLR_MWL I3C_MAXWLR_MWL_Msk /*!< Maximum Write Length */ /**************** Bit definition for I3C_TIMINGR0 register ******************/ -#define I3C_TIMINGR0_SCLL_PP_Pos (0U) +#define I3C_TIMINGR0_SCLL_PP_Pos (0UL) #define I3C_TIMINGR0_SCLL_PP_Msk (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos) /*!< 0x000000FF */ #define I3C_TIMINGR0_SCLL_PP I3C_TIMINGR0_SCLL_PP_Msk /*!< SCL Low duration during I3C Push-Pull phases */ -#define I3C_TIMINGR0_SCLH_I3C_Pos (8U) +#define I3C_TIMINGR0_SCLH_I3C_Pos (8UL) #define I3C_TIMINGR0_SCLH_I3C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos) /*!< 0x0000FF00 */ #define I3C_TIMINGR0_SCLH_I3C I3C_TIMINGR0_SCLH_I3C_Msk /*!< SCL High duration during I3C Open-drain and Push-Pull phases */ -#define I3C_TIMINGR0_SCLL_OD_Pos (16U) +#define I3C_TIMINGR0_SCLL_OD_Pos (16UL) #define I3C_TIMINGR0_SCLL_OD_Msk (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos) /*!< 0x00FF0000 */ #define I3C_TIMINGR0_SCLL_OD I3C_TIMINGR0_SCLL_OD_Msk /*!< SCL Low duration during I3C Open-drain phases and I2C transfer */ -#define I3C_TIMINGR0_SCLH_I2C_Pos (24U) +#define I3C_TIMINGR0_SCLH_I2C_Pos (24UL) #define I3C_TIMINGR0_SCLH_I2C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos) /*!< 0xFF000000 */ #define I3C_TIMINGR0_SCLH_I2C I3C_TIMINGR0_SCLH_I2C_Msk /*!< SCL High duration during I2C transfer */ /**************** Bit definition for I3C_TIMINGR1 register ******************/ -#define I3C_TIMINGR1_AVAL_Pos (0U) +#define I3C_TIMINGR1_AVAL_Pos (0UL) #define I3C_TIMINGR1_AVAL_Msk (0xFFUL << I3C_TIMINGR1_AVAL_Pos) /*!< 0x000000FF */ #define I3C_TIMINGR1_AVAL I3C_TIMINGR1_AVAL_Msk /*!< Timing for I3C Bus Idle or Available condition */ -#define I3C_TIMINGR1_ASNCR_Pos (8U) +#define I3C_TIMINGR1_ASNCR_Pos (8UL) #define I3C_TIMINGR1_ASNCR_Msk (0x3UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000300 */ #define I3C_TIMINGR1_ASNCR I3C_TIMINGR1_ASNCR_Msk /*!< Activity State of the New Controller */ #define I3C_TIMINGR1_ASNCR_0 (0x1UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000100 */ #define I3C_TIMINGR1_ASNCR_1 (0x2UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000200 */ -#define I3C_TIMINGR1_FREE_Pos (16U) +#define I3C_TIMINGR1_FREE_Pos (16UL) #define I3C_TIMINGR1_FREE_Msk (0x7FUL << I3C_TIMINGR1_FREE_Pos) /*!< 0x007F0000 */ #define I3C_TIMINGR1_FREE I3C_TIMINGR1_FREE_Msk /*!< Timing for I3C Bus Free condition */ -#define I3C_TIMINGR1_SDA_HD_Pos (28U) +#define I3C_TIMINGR1_SDA_HD_Pos (28UL) #define I3C_TIMINGR1_SDA_HD_Msk (0x3UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x30000000 */ #define I3C_TIMINGR1_SDA_HD I3C_TIMINGR1_SDA_HD_Msk /*!< SDA Hold Duration */ #define I3C_TIMINGR1_SDA_HD_0 (0x1UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x10000000 */ #define I3C_TIMINGR1_SDA_HD_1 (0x2UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x20000000 */ /**************** Bit definition for I3C_TIMINGR2 register ******************/ -#define I3C_TIMINGR2_STALLT_Pos (0U) +#define I3C_TIMINGR2_STALLT_Pos (0UL) #define I3C_TIMINGR2_STALLT_Msk (0x1UL << I3C_TIMINGR2_STALLT_Pos) /*!< 0x00000001 */ #define I3C_TIMINGR2_STALLT I3C_TIMINGR2_STALLT_Msk /*!< Stall on T bit */ -#define I3C_TIMINGR2_STALLD_Pos (1U) +#define I3C_TIMINGR2_STALLD_Pos (1UL) #define I3C_TIMINGR2_STALLD_Msk (0x1UL << I3C_TIMINGR2_STALLD_Pos) /*!< 0x00000002 */ #define I3C_TIMINGR2_STALLD I3C_TIMINGR2_STALLD_Msk /*!< Stall on PAR bit of data bytes */ -#define I3C_TIMINGR2_STALLC_Pos (2U) +#define I3C_TIMINGR2_STALLC_Pos (2UL) #define I3C_TIMINGR2_STALLC_Msk (0x1UL << I3C_TIMINGR2_STALLC_Pos) /*!< 0x00000004 */ #define I3C_TIMINGR2_STALLC I3C_TIMINGR2_STALLC_Msk /*!< Stall on PAR bit of CCC byte */ -#define I3C_TIMINGR2_STALLA_Pos (3U) +#define I3C_TIMINGR2_STALLA_Pos (3UL) #define I3C_TIMINGR2_STALLA_Msk (0x1UL << I3C_TIMINGR2_STALLA_Pos) /*!< 0x00000008 */ #define I3C_TIMINGR2_STALLA I3C_TIMINGR2_STALLA_Msk /*!< Stall on ACK bit */ -#define I3C_TIMINGR2_STALLR_Pos (4U) +#define I3C_TIMINGR2_STALLR_Pos (4UL) #define I3C_TIMINGR2_STALLR_Msk (0x1UL << I3C_TIMINGR2_STALLR_Pos) /*!< 0x00000010 */ #define I3C_TIMINGR2_STALLR I3C_TIMINGR2_STALLR_Msk /*!< Stall on I2C Read ACK bit */ -#define I3C_TIMINGR2_STALLS_Pos (5U) +#define I3C_TIMINGR2_STALLS_Pos (5UL) #define I3C_TIMINGR2_STALLS_Msk (0x1UL << I3C_TIMINGR2_STALLS_Pos) /*!< 0x00000020 */ #define I3C_TIMINGR2_STALLS I3C_TIMINGR2_STALLS_Msk /*!< Stall on I2C Write ACK bit */ -#define I3C_TIMINGR2_STALLL_Pos (6U) +#define I3C_TIMINGR2_STALLL_Pos (6UL) #define I3C_TIMINGR2_STALLL_Msk (0x1UL << I3C_TIMINGR2_STALLL_Pos) /*!< 0x00000040 */ #define I3C_TIMINGR2_STALLL I3C_TIMINGR2_STALLL_Msk /*!< Stall on I2C Address ACK bit */ -#define I3C_TIMINGR2_STALL_Pos (8U) +#define I3C_TIMINGR2_STALL_Pos (8UL) #define I3C_TIMINGR2_STALL_Msk (0xFFUL << I3C_TIMINGR2_STALL_Pos) /*!< 0x0000FF00 */ #define I3C_TIMINGR2_STALL I3C_TIMINGR2_STALL_Msk /*!< Controller Stall duration */ /******************* Bit definition for I3C_BCR register ********************/ -#define I3C_BCR_BCR_Pos (0U) +#define I3C_BCR_BCR_Pos (0UL) #define I3C_BCR_BCR_Msk (0xFFUL << I3C_BCR_BCR_Pos) /*!< 0x000000FF */ #define I3C_BCR_BCR I3C_BCR_BCR_Msk /*!< Bus Characteristics */ -#define I3C_BCR_BCR0_Pos (0U) +#define I3C_BCR_BCR0_Pos (0UL) #define I3C_BCR_BCR0_Msk (0x1UL << I3C_BCR_BCR0_Pos) /*!< 0x00000001 */ #define I3C_BCR_BCR0 I3C_BCR_BCR0_Msk /*!< Max Data Speed Limitation */ -#define I3C_BCR_BCR1_Pos (1U) +#define I3C_BCR_BCR1_Pos (1UL) #define I3C_BCR_BCR1_Msk (0x1UL << I3C_BCR_BCR1_Pos) /*!< 0x00000002 */ #define I3C_BCR_BCR1 I3C_BCR_BCR1_Msk /*!< IBI Request capable */ -#define I3C_BCR_BCR2_Pos (2U) +#define I3C_BCR_BCR2_Pos (2UL) #define I3C_BCR_BCR2_Msk (0x1UL << I3C_BCR_BCR2_Pos) /*!< 0x00000004 */ #define I3C_BCR_BCR2 I3C_BCR_BCR2_Msk /*!< IBI Payload additional Mandatory Data Byte */ -#define I3C_BCR_BCR3_Pos (3U) +#define I3C_BCR_BCR3_Pos (3UL) #define I3C_BCR_BCR3_Msk (0x1UL << I3C_BCR_BCR3_Pos) /*!< 0x00000008 */ #define I3C_BCR_BCR3 I3C_BCR_BCR3_Msk /*!< Offline capable */ -#define I3C_BCR_BCR4_Pos (4U) +#define I3C_BCR_BCR4_Pos (4UL) #define I3C_BCR_BCR4_Msk (0x1UL << I3C_BCR_BCR4_Pos) /*!< 0x00000010 */ #define I3C_BCR_BCR4 I3C_BCR_BCR4_Msk /*!< Virtual target support */ -#define I3C_BCR_BCR5_Pos (5U) +#define I3C_BCR_BCR5_Pos (5UL) #define I3C_BCR_BCR5_Msk (0x1UL << I3C_BCR_BCR5_Pos) /*!< 0x00000020 */ #define I3C_BCR_BCR5 I3C_BCR_BCR5_Msk /*!< Advanced capabilities */ -#define I3C_BCR_BCR6_Pos (6U) +#define I3C_BCR_BCR6_Pos (6UL) #define I3C_BCR_BCR6_Msk (0x1UL << I3C_BCR_BCR6_Pos) /*!< 0x00000040 */ #define I3C_BCR_BCR6 I3C_BCR_BCR6_Msk /*!< Device Role shared during Dynamic Address Assignment */ /******************* Bit definition for I3C_DCR register ********************/ -#define I3C_DCR_DCR_Pos (0U) +#define I3C_DCR_DCR_Pos (0UL) #define I3C_DCR_DCR_Msk (0xFFUL << I3C_DCR_DCR_Pos) /*!< 0x000000FF */ #define I3C_DCR_DCR I3C_DCR_DCR_Msk /*!< Devices Characteristics */ /***************** Bit definition for I3C_GETCAPR register ******************/ -#define I3C_GETCAPR_CAPPEND_Pos (14U) +#define I3C_GETCAPR_CAPPEND_Pos (14UL) #define I3C_GETCAPR_CAPPEND_Msk (0x1UL << I3C_GETCAPR_CAPPEND_Pos) /*!< 0x00004000 */ #define I3C_GETCAPR_CAPPEND I3C_GETCAPR_CAPPEND_Msk /*!< IBI Request with Mandatory Data Byte */ /***************** Bit definition for I3C_CRCAPR register *******************/ -#define I3C_CRCAPR_CAPDHOFF_Pos (3U) +#define I3C_CRCAPR_CAPDHOFF_Pos (3UL) #define I3C_CRCAPR_CAPDHOFF_Msk (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos) /*!< 0x00000008 */ #define I3C_CRCAPR_CAPDHOFF I3C_CRCAPR_CAPDHOFF_Msk /*!< Controller-role handoff needed */ -#define I3C_CRCAPR_CAPGRP_Pos (9U) +#define I3C_CRCAPR_CAPGRP_Pos (9UL) #define I3C_CRCAPR_CAPGRP_Msk (0x1UL << I3C_CRCAPR_CAPGRP_Pos) /*!< 0x00000200 */ #define I3C_CRCAPR_CAPGRP I3C_CRCAPR_CAPGRP_Msk /*!< Group Address handoff supported */ /**************** Bit definition for I3C_GETMXDSR register ******************/ -#define I3C_GETMXDSR_HOFFAS_Pos (0U) +#define I3C_GETMXDSR_HOFFAS_Pos (0UL) #define I3C_GETMXDSR_HOFFAS_Msk (0x3UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000003 */ #define I3C_GETMXDSR_HOFFAS I3C_GETMXDSR_HOFFAS_Msk /*!< Handoff Activity State */ #define I3C_GETMXDSR_HOFFAS_0 (0x1UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000001 */ #define I3C_GETMXDSR_HOFFAS_1 (0x2UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000002 */ -#define I3C_GETMXDSR_FMT_Pos (8U) +#define I3C_GETMXDSR_FMT_Pos (8UL) #define I3C_GETMXDSR_FMT_Msk (0x3UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000300 */ #define I3C_GETMXDSR_FMT I3C_GETMXDSR_FMT_Msk /*!< Get Max Data Speed response in format 2 */ #define I3C_GETMXDSR_FMT_0 (0x1UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000100 */ #define I3C_GETMXDSR_FMT_1 (0x2UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000200 */ -#define I3C_GETMXDSR_RDTURN_Pos (16U) +#define I3C_GETMXDSR_RDTURN_Pos (16UL) #define I3C_GETMXDSR_RDTURN_Msk (0xFFUL << I3C_GETMXDSR_RDTURN_Pos) /*!< 0x00FF0000 */ #define I3C_GETMXDSR_RDTURN I3C_GETMXDSR_RDTURN_Msk /*!< Max Read Turnaround Middle Byte */ -#define I3C_GETMXDSR_TSCO_Pos (24U) +#define I3C_GETMXDSR_TSCO_Pos (24UL) #define I3C_GETMXDSR_TSCO_Msk (0x1UL << I3C_GETMXDSR_TSCO_Pos) /*!< 0x01000000 */ #define I3C_GETMXDSR_TSCO I3C_GETMXDSR_TSCO_Msk /*!< Clock-to-data Turnaround time */ /****************** Bit definition for I3C_EPIDR register *******************/ -#define I3C_EPIDR_MIPIID_Pos (12U) +#define I3C_EPIDR_MIPIID_Pos (12UL) #define I3C_EPIDR_MIPIID_Msk (0xFUL << I3C_EPIDR_MIPIID_Pos) /*!< 0x0000F000 */ #define I3C_EPIDR_MIPIID I3C_EPIDR_MIPIID_Msk /*!< MIPI Instance ID */ -#define I3C_EPIDR_IDTSEL_Pos (16U) +#define I3C_EPIDR_IDTSEL_Pos (16UL) #define I3C_EPIDR_IDTSEL_Msk (0x1UL << I3C_EPIDR_IDTSEL_Pos) /*!< 0x00010000 */ #define I3C_EPIDR_IDTSEL I3C_EPIDR_IDTSEL_Msk /*!< ID Type Selector */ -#define I3C_EPIDR_MIPIMID_Pos (17U) +#define I3C_EPIDR_MIPIMID_Pos (17UL) #define I3C_EPIDR_MIPIMID_Msk (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos) /*!< 0xFFFE0000 */ #define I3C_EPIDR_MIPIMID I3C_EPIDR_MIPIMID_Msk /*!< MIPI Manufacturer ID */ @@ -15208,85 +15441,85 @@ typedef struct /* */ /******************************************************************************/ /****************** Bit definition for ICACHE_CR register *******************/ -#define ICACHE_CR_EN_Pos (0U) +#define ICACHE_CR_EN_Pos (0UL) #define ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) /*!< 0x00000001 */ #define ICACHE_CR_EN ICACHE_CR_EN_Msk /*!< Enable */ -#define ICACHE_CR_CACHEINV_Pos (1U) +#define ICACHE_CR_CACHEINV_Pos (1UL) #define ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ #define ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk /*!< Cache invalidation */ -#define ICACHE_CR_WAYSEL_Pos (2U) +#define ICACHE_CR_WAYSEL_Pos (2UL) #define ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) /*!< 0x00000004 */ #define ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk /*!< Ways selection */ -#define ICACHE_CR_HITMEN_Pos (16U) +#define ICACHE_CR_HITMEN_Pos (16UL) #define ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) /*!< 0x00010000 */ #define ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk /*!< Hit monitor enable */ -#define ICACHE_CR_MISSMEN_Pos (17U) +#define ICACHE_CR_MISSMEN_Pos (17UL) #define ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) /*!< 0x00020000 */ #define ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk /*!< Miss monitor enable */ -#define ICACHE_CR_HITMRST_Pos (18U) +#define ICACHE_CR_HITMRST_Pos (18UL) #define ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) /*!< 0x00040000 */ #define ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk /*!< Hit monitor reset */ -#define ICACHE_CR_MISSMRST_Pos (19U) +#define ICACHE_CR_MISSMRST_Pos (19UL) #define ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) /*!< 0x00080000 */ #define ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk /*!< Miss monitor reset */ /****************** Bit definition for ICACHE_SR register *******************/ -#define ICACHE_SR_BUSYF_Pos (0U) +#define ICACHE_SR_BUSYF_Pos (0UL) #define ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ #define ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk /*!< Busy flag */ -#define ICACHE_SR_BSYENDF_Pos (1U) +#define ICACHE_SR_BSYENDF_Pos (1UL) #define ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ #define ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk /*!< Busy end flag */ -#define ICACHE_SR_ERRF_Pos (2U) +#define ICACHE_SR_ERRF_Pos (2UL) #define ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) /*!< 0x00000004 */ #define ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk /*!< Cache error flag */ /****************** Bit definition for ICACHE_IER register ******************/ -#define ICACHE_IER_BSYENDIE_Pos (1U) +#define ICACHE_IER_BSYENDIE_Pos (1UL) #define ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ #define ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */ -#define ICACHE_IER_ERRIE_Pos (2U) +#define ICACHE_IER_ERRIE_Pos (2UL) #define ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ #define ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk /*!< Cache error interrupt enable */ /****************** Bit definition for ICACHE_FCR register ******************/ -#define ICACHE_FCR_CBSYENDF_Pos (1U) +#define ICACHE_FCR_CBSYENDF_Pos (1UL) #define ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ #define ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk /*!< Busy end flag clear */ -#define ICACHE_FCR_CERRF_Pos (2U) +#define ICACHE_FCR_CERRF_Pos (2UL) #define ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ #define ICACHE_FCR_CERRF ICACHE_FCR_CERRF_Msk /*!< Cache error flag clear */ /****************** Bit definition for ICACHE_HMONR register ****************/ -#define ICACHE_HMONR_HITMON_Pos (0U) +#define ICACHE_HMONR_HITMON_Pos (0UL) #define ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */ #define ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk /*!< Cache hit monitor register */ /****************** Bit definition for ICACHE_MMONR register ****************/ -#define ICACHE_MMONR_MISSMON_Pos (0U) +#define ICACHE_MMONR_MISSMON_Pos (0UL) #define ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */ #define ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk /*!< Cache miss monitor register */ /****************** Bit definition for ICACHE_CRRx register *****************/ -#define ICACHE_CRRx_BASEADDR_Pos (0U) +#define ICACHE_CRRx_BASEADDR_Pos (0UL) #define ICACHE_CRRx_BASEADDR_Msk (0xFFUL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x000000FF */ #define ICACHE_CRRx_BASEADDR ICACHE_CRRx_BASEADDR_Msk /*!< Base address of region X to remap */ -#define ICACHE_CRRx_RSIZE_Pos (9U) +#define ICACHE_CRRx_RSIZE_Pos (9UL) #define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00 */ #define ICACHE_CRRx_RSIZE ICACHE_CRRx_RSIZE_Msk /*!< Region X size */ #define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200 */ #define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400 */ #define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800 */ -#define ICACHE_CRRx_REN_Pos (15U) +#define ICACHE_CRRx_REN_Pos (15UL) #define ICACHE_CRRx_REN_Msk (0x1UL << ICACHE_CRRx_REN_Pos) /*!< 0x00008000 */ #define ICACHE_CRRx_REN ICACHE_CRRx_REN_Msk /*!< Region X enable */ -#define ICACHE_CRRx_REMAPADDR_Pos (16U) +#define ICACHE_CRRx_REMAPADDR_Pos (16UL) #define ICACHE_CRRx_REMAPADDR_Msk (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x07FF0000 */ #define ICACHE_CRRx_REMAPADDR ICACHE_CRRx_REMAPADDR_Msk /*!< Remap address of Region X to be remapped */ -#define ICACHE_CRRx_MSTSEL_Pos (28U) +#define ICACHE_CRRx_MSTSEL_Pos (28UL) #define ICACHE_CRRx_MSTSEL_Msk (0x1UL << ICACHE_CRRx_MSTSEL_Pos) /*!< 0x10000000 */ #define ICACHE_CRRx_MSTSEL ICACHE_CRRx_MSTSEL_Msk /*!< Region X AHB cache master selection */ -#define ICACHE_CRRx_HBURST_Pos (31U) +#define ICACHE_CRRx_HBURST_Pos (31UL) #define ICACHE_CRRx_HBURST_Msk (0x1UL << ICACHE_CRRx_HBURST_Pos) /*!< 0x80000000 */ #define ICACHE_CRRx_HBURST ICACHE_CRRx_HBURST_Msk /*!< Region X output burst type */ @@ -15296,12 +15529,12 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Pos (0UL) #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -19507,85 +19740,85 @@ typedef struct #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -19594,124 +19827,124 @@ typedef struct #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Pos (5UL) #define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_TAMPTSCR register ******************/ -#define RTC_TAMPTSCR_TAMP1TS_Pos (0U) +#define RTC_TAMPTSCR_TAMP1TS_Pos (0UL) #define RTC_TAMPTSCR_TAMP1TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP1TS_Pos) /*!< 0x00000001 */ #define RTC_TAMPTSCR_TAMP1TS RTC_TAMPTSCR_TAMP1TS_Msk -#define RTC_TAMPTSCR_TAMP2TS_Pos (1U) +#define RTC_TAMPTSCR_TAMP2TS_Pos (1UL) #define RTC_TAMPTSCR_TAMP2TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP2TS_Pos) /*!< 0x00000002 */ #define RTC_TAMPTSCR_TAMP2TS RTC_TAMPTSCR_TAMP2TS_Msk -#define RTC_TAMPTSCR_TAMP3TS_Pos (2U) +#define RTC_TAMPTSCR_TAMP3TS_Pos (2UL) #define RTC_TAMPTSCR_TAMP3TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP3TS_Pos) /*!< 0x00000004 */ #define RTC_TAMPTSCR_TAMP3TS RTC_TAMPTSCR_TAMP3TS_Msk -#define RTC_TAMPTSCR_TAMP4TS_Pos (3U) +#define RTC_TAMPTSCR_TAMP4TS_Pos (3UL) #define RTC_TAMPTSCR_TAMP4TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP4TS_Pos) /*!< 0x00000008 */ #define RTC_TAMPTSCR_TAMP4TS RTC_TAMPTSCR_TAMP4TS_Msk -#define RTC_TAMPTSCR_TAMP5TS_Pos (4U) +#define RTC_TAMPTSCR_TAMP5TS_Pos (4UL) #define RTC_TAMPTSCR_TAMP5TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP5TS_Pos) /*!< 0x00000010 */ #define RTC_TAMPTSCR_TAMP5TS RTC_TAMPTSCR_TAMP5TS_Msk -#define RTC_TAMPTSCR_ITAMPTS_Pos (16U) +#define RTC_TAMPTSCR_ITAMPTS_Pos (16UL) #define RTC_TAMPTSCR_ITAMPTS_Msk (0x1UL << RTC_TAMPTSCR_ITAMPTS_Pos) /*!< 0x00010000 */ #define RTC_TAMPTSCR_ITAMPTS RTC_TAMPTSCR_ITAMPTS_Msk /******************** Bits definition for RTC_TSIDR register ******************/ -#define RTC_TSIDR_TSID_Pos (0U) +#define RTC_TSIDR_TSID_Pos (0UL) #define RTC_TSIDR_TSID_Msk (0x3FUL << RTC_TSIDR_TSID_Pos) /*!< 0x0000003F */ #define RTC_TSIDR_TSID RTC_TSIDR_TSID_Msk #define RTC_TSIDR_TSID_0 (0x1UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000001 */ @@ -19722,12 +19955,12 @@ typedef struct #define RTC_TSIDR_TSID_5 (0x20UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000020 */ /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -19737,49 +19970,49 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for SAI_xCR1 register *******************/ -#define SAI_xCR1_MODE_Pos (0U) +#define SAI_xCR1_MODE_Pos (0UL) #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*! Release Notes for STM32U3xx CMSIS - - +
-

Release Notes for -STM32U3xx CMSIS

-

Copyright © 2024 STMicroelectronics
+

Release Notes for STM32U3xx CMSIS

+

Copyright © 2024 - 2026 STMicroelectronics

- +

Purpose

-

This driver provides the CMSIS device for the STM32U3xx product. This -covers

+

This driver provides the CMSIS device for the STM32U3xx product. This covers

  • STM32U375xx devices
  • STM32U385xx devices
-

This driver is composed of the description of the registers under -“Include” directory.

-

Various template files are provided to easily build an application. -They can be adapted to fit applications requirements.

+

This driver is composed of the description of the registers under “Include” directory.

+

Various template files are provided to easily build an application. They can be adapted to fit applications requirements.

    -
  • Templates/system_stm32u3xx.c contains the initialization code -referred as SystemInit.
    • -
  • Startup files are provided as example for EWARM©, MDK-ARM©, -STM32CubeIDE©.
    • -
  • Linker files are provided as example for EWARM©, MDK-ARM©, -STM32CubeIDE©.
    • +
  • Templates/system_stm32u3xx.c contains the initialization code referred as SystemInit.
    • +
  • Startup files are provided as example for EWARM©, MDK-ARM©, STM32CubeIDE©.
    • +
  • Linker files are provided as example for EWARM©, MDK-ARM©, STM32CubeIDE©.
-
-

Update history

+
+

Update history

- - +
-

Maintenance Release

+

Official Release

    -
  • Maintenance release of CMSIS for STM32U3xx firmware -package supporting STM32U385xx/STM32U375xx devices
    • +
  • Official release of CMSIS for STM32U3xx firmware package supporting STM32U385xx/STM32U375xx/STM32U3B5xx/STM32U3C5xx devices
    • +
  • CMSIS Device Release version of bits and registers definition aligned with RM0487

Contents

    +
  • First official release of STM32U3B5xx/STM32U3C5xx
    • +
  • Add COMP2 output-blanking PWM assignment
    • +
  • Fix Missing OR operator in IS_TIM_CCXN_INSTANCE definition
    • +
  • Set stack limit (MSPLIM) in CMSIS Device templates
    • +
  • Remove “section_static_hsp_data_bram_start” & “section_static_hsp_data_bram_end” useless symbols
    • +
  • Fix wrong memory region for HSP_DATA_BRAM
    • +
  • Add missing bit fields in flash
    • +
  • Update scatter file with correct flash size
    • +
  • Add Begin/End symbols for HSP_DATA_BRAM memory region
    • +
  • Add clock defaults to system file
    • +
  • Add/Update TSC registers for U3 derivatives
    • +
  • Add/Update DBGMCU registers
    • +
  • Add SYSCFG_CFGR1_TSC_G2_IO3 and SYSCFG_CFGR1_TSC_G2_IO1 bit definitions in SYSCFG_CFGR1
    • +
  • Fix wrong macro value for VREFBUF_CSR_VRS_2
    • +
  • Update TIM8 IRQ Handler name and remove unused AES IRQ handler
    • +
  • Add I2C4 macros for STM32U3 2M
    • +
  • Rename “HSP_BKO0CFGR_xxxx” constants by “HSP_BKOCFGR_xxxx”
    • +
  • Fix wrong macro HSPI1 to HSP1 in DBGMCU_AHB1FZR_DBG_HSP1
    • +
  • CMSIS update removing ADC DIFSEL register
    • +
  • Fix MPCBB registers for SRAM3
    • +
  • CMSIS correction for TIM8_S Definition
    • +
  • Add SPI4 instance for STM32U3 2M
    • +
  • Update FLASH linker files with correct flash size
    • +
+

Known Limitations

+
    +
  • None
    • +
+
+
+
+ +
+

Maintenance Release

+
    +
  • Maintenance release of CMSIS for STM32U3xx firmware package supporting STM32U385xx/STM32U375xx devices
    • +
+

Contents

+
    +
  • Add PKA on STM32U375xx
    • +
  • Add CCB sanity check feature on STM32U385xx
    • +
  • Swap bit position FLASH MEM and FLASH REG in GTZC1 TZIC registers
    • +
+

Known Limitations

+
    +
  • None
    • +
+
+
+
+ +
+

Maintenance Release

+
    +
  • Maintenance release of CMSIS for STM32U3xx firmware package supporting STM32U385xx/STM32U375xx devices
    • +
+

Contents

+
  • Fix PWR_I3CPUCR2_PG14_I3CPU_Pos value
  • Suppress unused bit
  • Minor fix on comments
-

Known Limitations

+

Known Limitations

  • None
- - +

First Release

    -
  • First official release of CMSIS for STM32U3xx -firmware package supporting STM32U385xx/STM32U375xx -devices
    • +
  • First official release of CMSIS for STM32U3xx firmware package supporting STM32U385xx/STM32U375xx devices
-

Contents

+

Contents

  • First official release of CMSIS devices drivers
    • Support of STM32U385xx/STM32U375xx devices
-

Known Limitations

+

Known Limitations

  • None
-
+