i32.load/i32.store wasm_to_ir produces unmapped vreg (latent #93-class bug)

[avrabe]

Discovery

The defensive-panic change in PR #101 catches a previously-silent miscompile. When PR #101 is rebased on top of v0.2.1, the existing test compile_i32_memory in crates/synth-cli/tests/wast_compile.rs fails with:

thread 'main' panicked at crates/synth-synthesis/src/optimizer_bridge.rs:1355:21:
synth internal compiler error: vreg v3 has no assigned ARM register and no spill slot.
This is a wasm_to_ir bug — likely a wasm op whose result is unmapped (see issue #93).

Reproducer: tests/wast/i32_memory.wast — basic store-then-load roundtrip with just local.get; local.get; i32.store; local.get; i32.load.

Same class as #93

PR #97 fixed three wasm ops with this shape (I64ExtendI32U/S, I32WrapI64). This is more of the same — at least one of I32Load/I32Store has a wasm_to_ir gap.

Pre-PR-#101 the silent R0 fallback produced miscompiled code that structural-only tests didn't catch. Exactly the gap closed #74 flagged — "zero tests verify compiled code produces correct results" — and which #99's new semantic tests start to close.

Blocks

• PR fix(opt): defensive panic on unmapped vreg instead of silent R0 fallback #101 (defensive panic) — won't merge until this is fixed.
• PR feat(fuzz): cargo-fuzz harnesses for ARM instruction selection (#82) #100 cargo-fuzz harness wasm_to_ir_roundtrip_op_coverage is designed to catch this class.

Labels

bug i32 codegen memory