Describe the bug
This chip has only a single VSS connection from the pads to the core ring on each side, whereas VDD has five.
This depends on the configuration of the PDN straps in the core area, as these block the pad-to-core connections. By choosing a different configuration, I can make the connections more balanced between VDD/VSS,
However, it would be great if pdngen could make better pad-to-core connections on its own.
I'm wondering how pdngen decides certain things like where to connect the pads to the core ring (pitch), which thickness to use (I have seen it use thinner straps), whether the I/O boundaries block straps, and how these decisions could be improved.
Perhaps it would be possible to add VDD/VSS connections alternatingly, so that there is an approximately equal number of connections to both?
Or perhaps it would be possible to merge the pad-to-core connections with the core power straps so they don't block each other so easily?
Another issue is that the IHP PDK uses I/O cells where access to power comes from the top.
By using the two topmost metal layers (TopMetal1 and TopMetal2) for the core ring, only horizontal pad-to-core connections are possible.
Is there a way to improve this situation? Could we perhaps only use TopMetal1 for the core ring? Is this already possible? But then this would require to use TopMetal2/Metal5 for the core area, which would remove routing resources from Metal5 (and Metal5 has a larger IR drop).
Or would it really require a feature such as #7192 to solve this problem?
Expected Behavior
It is possible to connect to the core ring from all sides, and there are plenty of balanced VDD/VSS connections.
Environment
OpenROAD version dcf36133a369abc8f3c5e5738cd4d82e4903c0e0 from 2026-02-17
To Reproduce
Here is a reproducible for the chip shown above: reproducible.zip
Simply ./run.sh
Relevant log output
Screenshots
No response
Additional Context
No response
Describe the bug
This chip has only a single VSS connection from the pads to the core ring on each side, whereas VDD has five.
This depends on the configuration of the PDN straps in the core area, as these block the pad-to-core connections. By choosing a different configuration, I can make the connections more balanced between VDD/VSS,
However, it would be great if pdngen could make better pad-to-core connections on its own.
I'm wondering how pdngen decides certain things like where to connect the pads to the core ring (pitch), which thickness to use (I have seen it use thinner straps), whether the I/O boundaries block straps, and how these decisions could be improved.
Perhaps it would be possible to add VDD/VSS connections alternatingly, so that there is an approximately equal number of connections to both?
Or perhaps it would be possible to merge the pad-to-core connections with the core power straps so they don't block each other so easily?
Another issue is that the IHP PDK uses I/O cells where access to power comes from the top.
By using the two topmost metal layers (TopMetal1 and TopMetal2) for the core ring, only horizontal pad-to-core connections are possible.
Is there a way to improve this situation? Could we perhaps only use TopMetal1 for the core ring? Is this already possible? But then this would require to use TopMetal2/Metal5 for the core area, which would remove routing resources from Metal5 (and Metal5 has a larger IR drop).
Or would it really require a feature such as #7192 to solve this problem?
Expected Behavior
It is possible to connect to the core ring from all sides, and there are plenty of balanced VDD/VSS connections.
Environment
To Reproduce
Here is a reproducible for the chip shown above: reproducible.zip
Simply
./run.shRelevant log output
Screenshots
No response
Additional Context
No response