Can the interpolator help

[thejpster]

https://github.com/Wren6991/PicoDVI uses the interpolator engine to do some shifts and adds much faster than the CPU can.

Can it help us do the font lookups? 16-bits from VGA memory in, plus the glyph row, two memory addresses come out (one for the 8 bits of glyph, one for the colour lookup table start-point). Or, 8 bits go in, four CLUT addresses come out?

[CHiPs44]

It's used in MEMU https://github.com/Memotech-Bill/MEMU to put 2 4bpp pixels into a 32 bits value in the scanline buffer, perhaps it will help you?

[thejpster]

Oooh, interesting!

[thejpster]

Damn, I forgot about this. I need to revisit it.

Also I found https://forums.raspberrypi.com//viewtopic.php?f=145&t=305712&p=1848868#p1848706.

/*
 * Copyright (c) 2020 Graham Sanderson
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
 
#include "hardware/regs/sio.h"
#include "hardware/regs/addressmap.h"

.cpu cortex-m0plus
.thumb

.section .time_critical.pal16

#define INTERP_OFFSET0(x) (x - SIO_INTERP0_ACCUM0_OFFSET)
#define INTERP_OFFSET1(x) (INTERP_OFFSET0(x) + SIO_INTERP1_ACCUM0_OFFSET - SIO_INTERP0_ACCUM0_OFFSET)

// setup: note palette is 256 entries of 32bits; i.e. all 2 pixel combinations
//
// interp_config c = interp_default_config();
// interp_config_set_shift(&c, 22);
// interp_config_set_mask(&c, 2, 9);
// interp_set_config(interp0, 0, &c);
// interp_config_set_shift(&c, 14);
// interp_config_set_cross_input(&c, true);
// interp_set_config(interp0, 1, &c);
// interp_set_base(interp0, 0, (uintptr_t)palette256);
// interp_set_base(interp0, 1, (uintptr_t)palette256);

// dest - pixel buffer 16bpp
// src - source pixel buffer 4bpp (must be 32 bit aligned)
// count - is number of pixels to convert / 8
// extern void convert_from_pal16(uint32_t *dest, uint8_t *src, uint count);

.global convert_from_pal16
.type convert_from_pal16,%function
.thumb_func
convert_from_pal16:
    push {r4-r7, lr}
    add r2, r1
    ldr r7, =(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET)

1:
    ldmia r1!, {r3}
    str r3, [r7, #INTERP_OFFSET0(SIO_INTERP0_ACCUM0_OFFSET)]
    ldr r6, [r7, #INTERP_OFFSET0(SIO_INTERP0_PEEK_LANE0_OFFSET)]
    ldr r5, [r7, #INTERP_OFFSET0(SIO_INTERP0_PEEK_LANE1_OFFSET)]
    ldr r6, [r6]
    ldr r5, [r5]
    lsl r3, #16
    str r3, [r7, #INTERP_OFFSET0(SIO_INTERP0_ACCUM0_OFFSET)]
    ldr r4, [r7, #INTERP_OFFSET0(SIO_INTERP0_PEEK_LANE0_OFFSET)]
    ldr r3, [r7, #INTERP_OFFSET0(SIO_INTERP0_PEEK_LANE1_OFFSET)]
    ldr r4, [r4]
    ldr r3, [r3]
    stmia r0!, {r3, r4, r5, r6}
    cmp r1, r2
    blo 1b

    pop {r4-r7, pc}