FIFO interface with FPGA doumentation question

[mhanuel26]

@whitequark Hi Catherine,

I am wondering if there is some documentation regarding the external FIFO interface with the FPGA, any example test or usage you can point me to will be appreciated.!

Thank you in advance,
Manuel

[whitequark]

I don't understand the question, sorry. What is "external FIFO interface with the FPGA"?

[mhanuel26]

@whitequark

I understand the MCU CY7C68013A has a parallel bus type of interface with the FPGA, after looking at the MCU datasheet it seem the interface is referenced as GPIF or External FIFO. The MCU has 8 bit lines D0-D7 and some control lines WR, RD, OE, FLAGx, PKTEND, A0, A1.
I am wondering how is that been use in the project.

I will appreciate your comments,

[wanda-phi]

we use the FX2 with the external FIFO mode. on the FPGA side, the interface is implemented in https://github.com/GlasgowEmbedded/glasgow/blob/main/software/glasgow/gateware/fx2_crossbar.py and that file has some long comments that describe it in detail. there are 4 FIFOs available (two OUT, two IN), and an applet can request the individual FIFOs from the crossbar at build time, with most applets using one OUT and one IN. if you use the --trace feature, the analyzer consumes an additional IN FIFO.

currently the applet FIFOs directly correspond to FX2 FIFOs (and thus USB endpoints), but there are plans to change it (#354) which will be necessary for multi-applet support

[mhanuel26]

@wanda-phi , @whitequark

Thank you for your comments, what would be the simplest applet to test this for?

Wondering if there is an applet that can stream some data from the FPGA into a host PC using the USB comms?

Can you suggest a place to start looking at this?

Thank you again,

[wanda-phi]

I am not quite sure what exactly you want to test.

Depending on what exactly you need, some good applets to look at include uart (use a loopback wire to make it talk to itself if you need to) and benchmark

[mhanuel26]

Hi @wanda-phi

So is this UART applet going thru and back from the FPGA ? Such as USB --> FX2 ---> FPGA --> UART (loopback)?

I am trying to see if I can use the External FIFO interface to stream data to a host PC from the FPGA basically, such as connecting a high speed ADC to the FPGA.

Does this makes sense to you?

Thank you again,

[wanda-phi]

yes, UART will send data in both directions, at low speed

benchmark will attempt to actually saturate the FIFO interface bandwidth, in both directions

the external FIFO interface is pretty good for streaming data to the host (it can reasonably efficiently use the USB 2.0 high speed bandwidth). however, if you have realtime requirements, you may run into problems with small buffers (there's only a few kB of buffer space total on the FX2 + the FPGA); we intend to solve this problem in the future with the hyperRAM addon which is currently in development

[mhanuel26]

Hi @wanda-phi ,

Thank you for your comments,

Where is a good place to know about the future development and ask this type of questions? I was looking for a discord channel but could not find any. For instance, that hyperRAM development, is it been discussed somewhere so I can get some insights about it?

[wanda-phi]

there is a channel, and it is mentioned in the documentation (https://glasgow-embedded.org/latest/community.html#community)

[whitequark]

Note that there is no support for using the FX2's FIFO interface directly. The Glasgow project requires the use of the Amaranth-based framework to interact with external devices. You can do anything you want but it will be on your own to figure out how.